Analog Design Engineer remote jobs

Rambus, a premier chip and silicon IP provider, is seeking to hire an entry level Analog/Mixed-Signal Design Engineer to join our MIC Design team in Agoura Hills, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities * Design, simulate and characterize high-performance and high-speed Analog/Mixed-Signal circuits * Research and implement optimal circuit architectures * Work with layout team to optimize for post extraction performance * Document analysis and simulation to show that design achieves electrical, timing parameters and pre-silicon verification flow * Work with the Lab/System team for circuit characterization and validation * Create behavior model for verification simulations * Work closely with Sr. Design Engineers on the team Qualifications * MS EE or PhD EE with minimum GPA of 3.0/4.0 * Course work or experience in CMOS analog/mixed-signal circuit design * Good knowledge of basic Analog circuit design principles * Some knowledge of Verilog-A, Verilog is desirable * Strong commitment and ability to work in cross functional and globally dispersed teams About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow's systems. Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership. The US salary range for this full-time position is $65,900 to $122,500. Our salary ranges are determined by role, level and location. The successful candidate's starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/. #LI-HYBRID #LI-LH1

Reliability Analog Design Engineer ] Blue Cheetah Analog Design Inc. is a growing technology start-up headquartered in Sunnyvale, California. Our mission is to generate state-of-the-art “in package” die-to-die semiconductor IP solutions for the rapidly growing chiplet ecosystem. We accomplish this by providing high performance chiplet interface semiconductor IP to our global customers, allowing them to reshape their product roadmaps to a more agile and cost effective chiplet based approach. Join our team to help usher in the chiplet era of semiconductor-based products. We provide a professional benefits package including medical, dental, vision, 401K plan with company match as well as generous holiday & vacation leave. Join a team where your impact to the collective success will be clear and the big company politics do not exist. Job Description: ● Use your Reliability analysis skills within the Analog/Mixed Signal Design domain to ensure robustness for our differentiated die-to-die chiplet IP solutions ● Drive and own our EM/IR analysis methodology for analog/mixed signal custom circuit designs in leading edge technologies ● Work closely with the design team and the layout team to close the gap on any reliability violations ● Coordinate with CAD and PDK team members to validate that the team is using the latest foundry collateral ● Train others in ramping up on EM/IR reliability analysis ● Grow your knowledge base by working in leading edge technologies and interacting with peers within our company and other partner companies driving the state-of-the-art for next gen products General Requirements: ● BS, MS, Ph.D. in electrical/ECE engineering (MSEE+ preferred) ● Experienced expert in performing EM/IR analysis with Cadence Voltus and Voltus-XFi ● Team player with the ability to analyze and present data in a clear and meaningful manner ● Self-motivated, energetic attitude to create leading-edge production quality designs and innovate design methodologies MUST HAVE Requirements: ● Multi-year experience directly performing EM/IR reliability analysis using Cadence Voltus ● Knowledge and familiarity of fundamental analog IC circuit blocks ● CMOS design experience in 28nm and lower process technologies, ideally with finfet analysis experience ● Basic circuit and Cadence EDA simulation (Spectre) skills to understand and properly configure circuit simulation stimulus ● Comfortable with viewing and manipulating layouts in Virtuoso framework Preferred Skills: ● CMOS design experience in FinFet process technologies ● High speed datacomm design experience ● Experience with other analog IC related reliability matters such as: SOA analysis; Aging analysis, ESD fundamentals ● Experience with ParagonX EDA tool Equal Opportunity: Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status. Compensation: In addition to Blue Cheetah's generous benefit package, the target base pay range for this role is between $145,000 and $225,000. Your base pay will depend on your skills, qualifications, experience, and location

Rambus, a premier chip and silicon IP provider, is seeking to hire an entry level Analog/Mixed-Signal Design Engineer to join our MIC Design team in Agoura Hills, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Design, simulate and characterize high-performance and high-speed Analog/Mixed-Signal circuits Research and implement optimal circuit architectures Work with layout team to optimize for post extraction performance Document analysis and simulation to show that design achieves electrical, timing parameters and pre-silicon verification flow Work with the Lab/System team for circuit characterization and validation Create behavior model for verification simulations Work closely with Sr. Design Engineers on the team Qualifications MS EE or PhD EE with minimum GPA of 3.0/4.0 Course work or experience in CMOS analog/mixed-signal circuit design Good knowledge of basic Analog circuit design principles Some knowledge of Verilog-A, Verilog is desirable Strong commitment and ability to work in cross functional and globally dispersed teams About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow's systems. Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership. The US salary range for this full-time position is $65,900 to $122,500. Our salary ranges are determined by role, level and location. The successful candidate's starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/. #LI-HYBRID #LI-LH1

Client: Iontra Contract period: 6 to 8 months Preferred location: Dallas or Denver or we can look at a remote working option as a last thing We need to look for a very good Analog Circuit Designer cum system validation Engineer. Must have involved in end to end Analog or mixed signal development flow Must have involved in post TO test setup, bring up of Analog or mixed signal Blocks Must have good Circuit design experience Must have good experience in architecting a Analog or mixed signal chip Job description: Working as part of a chip architecture and system architecture team supporting them in developing a Analog Design implementation, test flow both at chip level and at system level. Should work closely with EDA and IP vendors in qualifying the IPs that will go into the Design under build. It's a startup environment and the candidate is expected to be self driven, attention to details, good problem solving skills and a strong technical solution provider in the Analog or mixed signal Space.

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for. Responsibilities & Skills Responsibilities: The Analog IC Design Engineer is responsible for the design and development of analog, mixed-signal IC circuit blocks from initial specification and architecture to final, post-silicon verification to ensure specifications are met. Responsibilities include: Analog, mixed-signal circuit design and simulation Work with mask designers to deliver physical design Integration of analog/mixed-signal blocks into large, complex, digital chips Define bench-level test plans for post-silicon characterization Post-silicon measurements, characterization, and debug Lead/mentor junior engineers Qualifications: BS, MS, and/or PhD in Electrical Engineering or related fields Multiple years of experience working in analog/mixed-signal circuit design (BSEE, 8+ years, MS 6+ years, PhD 3+ years) Proven design experience in most of the following analog, mixed-signal circuits: SerDes receivers/transmitters, low-jitter PLLs, oscillators, phase interpolators, ADC/DAC, high speed clock distribution, bandgap/bias, and voltage regulators In-depth knowledge of transistor mismatch, linearity, stability, low-power and low-noise techniques Experience designing circuits in advanced FinFET technologies Proficient in AMS design flows, tools, and methodologies like Cadence schematic capture, Virtuoso, Spectre, layout, and analog behavioral modeling Detailed oriented, with excellent problem-solving skills, communication skills, and the ability to work collaboratively in a fast-paced, team environment

Manager/Lead Analog/Mixed-Signal Design Engineer Location: Remote | Headquarters: Tempe, Arizona, USA Company: Alphacore Inc. About Us Alphacore Inc. is a fast-growing innovator in high-performance microelectronics, serving critical industries such as scientific research, aerospace, defense, medical imaging, and homeland security. Our cutting-edge technology powers some of the most advanced systems in the world. Recognized by Inc. 500 as one of the fastest-growing companies in the U.S., Alphacore was also ranked #6 nationwide among Top Computer Hardware Companies. 🔗Learn more about us What You'll Do As a Manager/Lead Analog/Mixed-Signal Design Engineer, you will play a leadership role in designing and implementing high-performance analog and RF circuits, with a focus on high-speed data converters. You will be a key contributor to product innovation and technical leadership within a fast-paced, collaborative team. Your Responsibilities: Lead IC design projects for high-performance analog/RF circuits and systems. Develop and verify high-speed ADC (Analog-to-Digital Converter) architectures. Work closely with cross-functional teams, including layout, verification, and system engineering. Utilize industry-standard tools such as Cadence EDA for schematic and layout design. Support silicon validation and post-silicon debugging activities. What We're Looking For Bachelor's degree in Electronics Engineering or a related field (required) Masters or Ph.D. in Electronics Engineering or related field (preferred) Proven experience in high-speed ADC design Solid knowledge of analog/mixed-signal IC design methodologies Experience using Cadence EDA tools is a plus Excellent problem-solving and communication skills Strong team leadership and project management abilities Why Join Alphacore? Be part of a rapidly growing startup making a real-world impact Remote work flexibility contribute from anywhere Collaborate with a highly experienced, innovative, and friendly team Competitive benefits include: 401(k) plan with company match Paid time off and company holidays Medical, dental, vision, and life insurance Family care and bonding leave Opportunities to volunteer and engage with the community How to Apply Send your resume to: [email protected] Use the subject line: Manager/Lead Analog Design Engineer

The application window is expected to close on 12/31/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This is a hybrid role with three days per week at our San Jose, CA office. Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. Meet the Team We are Mixed-signal IC design group that develops high speed ()25Gb/s), and high accuracy, analog designs for optical communications products. We optimize design that will integrate into the ASIC. Our team interacts with other Acacia groups including digital/DSP design, system design, package design, and module design. Your Impact * You will architect, design, layout, measure and productize ultra-deep sub-micron-based CMOS products. * You will lead efforts for a large block on a complex chip, mentor team members and track deliverables, participate in peer review of complex IC designs and provide solid design methodology from conception to production. * You will also collaborate with packaging and hardware design team to ensure signal and power integrity specifications are met. * You will develop high speed AMS circuits and best-in-class products that push the boundaries of what is possible. Minimum qualifications: * BSEE degree with 12+ years of experience or equivalent or an MS degree with 8+ years of experience, or equivalent or a PhD with 5+ years of experience, or equivalent * Design, simulation and measurement of high speed ICs in at least 3 areas below: High Speed Serial Links utilizing serializers, deserializers, and data converters, voltage regulators, output drivers, phase locked loops, clock transmission/propagation, Opamps, programmable gain amplifiers, and equalization Preferred qualifications: * Experience with electrical transceiver applications including backplane and cable communications * Experience with FinFET technology * High-frequency layout experience a plus: Passive component design: inductors, * transformers, transmission-lines, etc. * Floorplanning (power/ground, digital/analog signal routing, etc.) experience * Custom transistor layout experience * Experience designing for manufacturability * Experience with ESD laboratory practices and methodology * Experience with Cadence (virtuoso), Spectre/APS/SpectreX, Matlab, EMX * Experience with mixed-signal simulations in AMS Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $191,400.00 to $281,400.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: * 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees * 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco * Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees * Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) * 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next * Additional paid time away may be requested to deal with critical or emergency issues for family members * Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: * .75% of incentive target for each 1% of revenue attainment up to 50% of quota; * 1.5% of incentive target for each 1% of attainment between 50% and 75%; * 1% of incentive target for each 1% of attainment between 75% and 100%; and * Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $191,400.00 - $323,600.00 Non-Metro New York state & Washington state: $176,100.00 - $287,900.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

About the Company Inspiren offers the most complete and connected ecosystem in senior living. Founded by Michael Wang, a former Green Beret turned cardiothoracic nurse, Inspiren proves that compassionate care and technology can coexist - bringing peace of mind to residents, families, and staff. Our integrated solutions seamlessly fit into existing workflows, capturing everything happening within a community. Backed by nurse specialists and powerful analytics, we provide the data operators need to make informed clinical and operational decisions - driving efficiency, profitability, and better care outcomes. About the Role We are seeking a highly-skilled Staff Design Engineer to own and lead the end-to-end hardware product development of new devices for Inspiren's ecosystem. As a senior member of the hardware engineering team, you will serve as the lead engineer from concept through mass production, driving requirements definition, establishing system architecture, prototyping, leading verification, assisting validation, and regulatory attainment. You will integrate subject-matter experts (SMEs), manage JDM partners, and deliver devices that meet the highest standards of quality, reliability, manufacturability, and cost across the lifecycle of all of Inspiren's devices and platforms. What You'll Do Product Development Project Management: Participate in and manage the development effort of multiple hardware products simultaneously, ensuring cost, schedule, budget, and performance requirements are met from concept to mass production release. Requirements Definition: Develop clear, detailed product requirements and specifications that translate user needs and business goals into actionable engineering requirements, collaborating closely with product management, hardware, firmware, software, clinical, operations, quality, and external design and manufacturing partners. Product Architecture and Specifications: Lead the design-stage work by developing system- and subsystem-level specifications, block diagrams, and architecture documents that define how the product functions end to end, collaborating closely with cross-functional partners across hardware, firmware, software, clinical, and operations; Hardware Design and Development: Own the end-to-end product development across electrical, mechanical, and firmware domains, including concept development, brainstorming, and participation in design reviews; create CAD models and detailed manufacturing drawings, apply tolerancing and engineering analysis such as FEA, and perform hands-on prototyping and iteration to drive concepts into robust, production-ready hardware designs. JDM Collaboration: Serve as the primary technical point of contact for contract manufacturers engaging in JDM activities; direct and check work, lead design reviews, lead technical discussions, and drive issue resolution. Embed Rigorous Design for Excellence (DfX) Mindset: Drive DFMA, DFT, and DFR across the design; conduct design and process FMEAs; review CAD, schematics, and drawings to ensure clarity for manufacturing and assembly; Product Quality: Develop test plans derived from product requirements, oversee prototyping and execution of tests, and lead verification activities to confirm that product performance and reliability targets are met. Regulatory Compliance: Coordinate regulatory and certification activities (e.g., safety, EMC, wireless), ensure designs conform to relevant standards, and drive products through successful certification. Supplier & NPI Support: Travel regularly to manufacturing sites to support builds, review off-tool samples and inspection reports, drive corrective actions to ensure designs meet Inspiren's specifications, regulatory requirements, and quality standards; ensure successful transition to mass production in partnership with operations and suppliers. Mentor Team Members: Provide technical guidance and mentorship, fostering a culture of excellence and innovation through a culture of continuous learning. Qualifications Educational Background: Bachelor's or Master's degree in Mechanical Engineering, Electrical Engineering, Systems Engineering, Computer Engineering, or a related engineering field Experience: 8+ years of experience in product development of connected hardware products, including leading full product lifecycles from concept through mass production with OEM and JDM partners. Technical Skills: Product Definition & Architecture: Demonstrated experience capturing requirements, writing specifications, and creating system architectures for connected hardware products. CAD and Documentation: Proficiency with CAD tools to develop 3D models, manufacturing drawings, and schematics, ensuring that necessary information for manufacturing and assembly is clearly communicated. GD&T experience a plus. Prototyping & Verification: Hands-on experience building and testing prototypes, developing verification and validation plans, and analyzing test data to drive design iterations. DFx, FMEA, and NPI: Strong background in DFMA, design and process FMEA, and phase-gate NPI processes for high-volume manufacturing. Supplier & JDM Collaboration: Proven track record interfacing with manufacturers and JDM/ODM partners to ensure manufacturability, quality, and on-time delivery, including on-site build support. Regulatory & Compliance: Working knowledge of hardware regulatory standards (e.g., safety, EMC, wireless) and experience driving products through certification. Communication: Excellent verbal and written communication skills, with the ability to convey complex ideas clearly and align diverse stakeholders. Adaptability: Comfortable working in a fast-paced, dynamic environment and adapting to changing priorities. Start-up experience is a plus. Start-up experience is a plus. Details The annual salary for this role is $200,000 - 225,000 + equity + benefits (including medical, dental, and vision) Flexible PTO Location: Remote, US or Canada Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender perception or identity, national origin, age, marital status, protected veteran status, or disability status. Compensations & Benefits At Inspiren, we are committed to fair, transparent, and equitable compensation. We know that every candidate brings a unique combination of experience, skills, and perspectives, and we take these factors into account when determining pay. While compensation may vary depending on your background, role, and location, we are proud to offer a competitive base salary and total benefits package, alongside eligibility for equity awards in the form of stock options. We believe great work deserves great rewards. Our compensation and benefits are designed to recognize your contributions and reflect the standards of leading organizations in our field. Your recruiter will be happy to walk you through the full compensation package, including what your total pay could look like, so you have a clear picture of both the immediate and long-term value of joining our team.

Join Our Team as an Avionics Circuit Design Engineer where you will work on the development of a sophisticated state-of-the-art avionics product in a world class Integrated Product Development environment. Location: This position does not support teleworking; the preferred candidate will be located near our Lockheed Martin Space facility one of the Coolest places to work: Cambridge MA, and be expected to work a flexible 9x80 schedule in the office full-time. Space is a critical domain, connecting our technologies, our security, and our humanity. While others view space as a destination, we see it as a realm of possibilities, where we can do more - we can innovate, invest, inspire, and integrate our capabilities to transform the future. At Lockheed Martin Space, we aim to harness the full potential of space to cultivate innovation, reduce costs, and push the boundaries of what technology can achieve. We're creating future-ready solutions, focusing on resiliency and urgency through our 21st Century Security vision. We're erasing boundaries and forming partnerships across industries and around the world. We're advancing spacecraft and the workforce to fuel the next generation. And we're reimagining how space can connect us, ensuring security and prosperity. Join us in shaping a new era in space and find a career that's built for you. What does this role look like? As a Circuit Design Engineer, you will work on the development of a sophisticated state-of-the-art Avionics product at a key supplier site in Cambridge MA. Key activities you will accomplish in this role: • Design/Capture electrical schematics and guide the board layouts. • Perform electrical Worst Case Analysis and Electrical Parts Stress Analysis. • Work on a cross-functional team in the development and integration of world class avionics systems. • Resolve test anomalies and troubleshooting, and generation, review and presentation of Product Certification, and also support system level testing. To be effective in this role, you will need: • Experience supporting the technical evaluation of design and requirements verification. • Experience in different phases of aerospace hardware development cycle. • Experience interacting with peers, management and government customers. • Experience in presentations and in written communication skills. • Missile design experience. • 8+ years professional experience. • While no clearance is needed to start in this position, you will need to obtain and maintain a Secret clearance, thus US Citizenship is required. Why Lockheed Martin? Our employees play an active role in strengthening the quality of life where we live and work by volunteering more than 850,000 hours annually. Learn more about Lockheed Martin's comprehensive benefits package. Find out more on how we proudly support Hiring Our Heroes. At Space we value your skills, training, and education. We believe that by applying the highest standards of business ethics and visionary thinking, everything is within our reach - and yours as a Lockheed Martin Space employee… join us to experience your future! Let's do Space! #LI-CS1 Basic Qualifications • Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education. • Experience in electronics design, with a focus on CCA design and development. • Experience as a technical lead or responsible engineer. • Ability to obtain Secret clearance thus US Citizenship is required. Desired skills • Experienced at leading teams through challenging engineering and/or programmatic issues. • Experience on Space and/or Missile Defense Missions. • Experience working with supplier in a joint development effort. • Experience in electronic systems schematic creation and interpretation, and Electronics Modeling/Simulation Tools such as SPICE. • Experience in schematic capture using Zuken or similar tools. • Experience with PSPICE, Saber or other electronics simulation tool experience. • Experience performing electronics analysis (Worst Case Analysis, Electrical Parts Stress Analysis, Failure Modes and Effects Critical Analysis). • Demonstrated good communication and presentation skills with the ability to articulate complex technical issues to peers, management, subcontractors and customers. • Demonstrated ability to work in a fast-paced, dynamic, collaborative team environment and to build consensus among peers and effective relationships with team members. • Demonstrated strong problem solving and conflict resolution skills. • Adaptable to new situations and demonstrate self-initiative in solving complex problems. • Able to work effectively in a diverse team environment. Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics. The application window will close in 90 days; applicants are encouraged to apply within 5 - 30 days of the requisition posting date in order to receive optimal consideration. * Join us at Lockheed Martin, where your mission is ours. Our customers tackle the hardest missions. Those that demand extraordinary amounts of courage, resilience and precision. They're dangerous. Critical. Sometimes they even provide an opportunity to change the world and save lives. Those are the missions we care about. As a leading technology innovation company, Lockheed Martin's vast team works with partners around the world to bring proven performance to our customers' toughest challenges. Lockheed Martin has employees based in many states throughout the U.S., and Internationally, with business locations in many nations and territories. Other Important Information By applying to this job, you are expressing interest in this position and could be considered for other career opportunities where similar skills and requirements have been identified as a match. Should this match be identified you may be contacted for this and future openings. Ability to work remotely Onsite Full-time: The work associated with this position will be performed onsite at a designated Lockheed Martin facility. Work Schedule Information Lockheed Martin supports a variety of alternate work schedules that provide additional flexibility to our employees. Schedules range from standard 40 hours over a five day work week while others may be condensed. These condensed schedules provide employees with additional time away from the office and are in addition to our Paid Time off benefits. Security Clearance Information This position requires a government security clearance, you must be a US Citizen for consideration. Pay Rate: The annual base salary range for this position in California, Massachusetts, and New York (excluding most major metropolitan areas), Colorado, Hawaii, Illinois, Maryland, Minnesota, New Jersey, Vermont, Washington or Washington DC is $139,600 - $246,100. For states not referenced above, the salary range for this position will reflect the candidate's final work location. Please note that the salary information is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market and business considerations when extending an offer. Benefits offered: Medical, Dental, Vision, Life Insurance, Short-Term Disability, Long-Term Disability, 401(k) match, Flexible Spending Accounts, EAP, Education Assistance, Parental Leave, Paid time off, and Holidays. Pay Rate: The annual base salary range for this position in California, Massachusetts, and New York (excluding most major metropolitan areas), Colorado, Hawaii, Illinois, Maryland, Minnesota, New Jersey, Vermont, Washington or Washington DC is $139,600 - $246,100. For states not referenced above, the salary range for this position will reflect the candidate's final work location. Please note that the salary information is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market and business considerations when extending an offer. Benefits offered: Medical, Dental, Vision, Life Insurance, Short-Term Disability, Long-Term Disability, 401(k) match, Flexible Spending Accounts, EAP, Education Assistance, Parental Leave, Paid time off, and Holidays. (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year. This position is incentive plan eligible.

Harness is a high-growth company that is disrupting the software delivery market. Our mission is to enable the 30 million software developers in the world to deliver code to their users reliably, efficiently, securely and quickly, increasing customers' pace of innovation while improving the developer experience. We offer solutions for every step of the software delivery lifecycle to build, test, secure, deploy and manage reliability, feature flags and cloud costs. The Harness Software Delivery Platform includes modules for CI, CD, Cloud Cost Management, Feature Flags, Service Reliability Management, Security Testing Orchestration, Chaos Engineering, Software Engineering Insights and continues to expand at an incredibly fast pace. Harness is led by technologist and entrepreneur Jyoti Bansal, who founded AppDynamics and sold it to Cisco for $3.7B. We're backed with $425M in venture financing from top-tier VC and strategic firms, including J.P. Morgan, Capital One Ventures, Citi Ventures, ServiceNow, Splunk Ventures, Norwest Venture Partners, Adage Capital Partners, Balyasny Asset Management, Gaingels, Harmonic Growth Partners, Menlo Ventures, IVP, Unusual Ventures, GV (formerly Google Ventures), Alkeon Capital, Battery Ventures, Sorenson Capital, Thomvest Ventures and Silicon Valley Bank As a Staff Growth Designer at Harness, you'll design experiences that accelerate adoption, retention, and expansion across the customer journey. You'll uncover where users lose momentum, design moments that re-engage them, and apply behavioral design principles to shape motivation, ability, and triggers. Every interaction should help users progress toward value naturally and intuitively. This role blends high-craft design with disciplined experimentation. You'll design and validate flows that feel intuitive and connected, using interaction, motion, and transitions to guide users seamlessly across states and surfaces. You'll partner closely with Product, Growth Marketing, and Engineering to uncover friction, form hypotheses, and translate behavioral insights into experiences that are fluid, purposeful, and outcome-driven. About the Role Design for impact: Create experiences that improve activation, retention, and expansion across key journeys Experiment and learn: Design, launch, and analyze A/B and multivariate tests to validate ideas and accelerate learning Collaborate across teams: Partner with Product, Growth, and Engineering to prioritize and deliver work that aligns user value with business outcomes Use data with intent: Define success metrics with analytics partners and translate findings into actionable design decisions Prototype rapidly: Build interactive prototypes and production-ready designs that bring growth ideas to life Enhance onboarding: Identify and remove friction in setup and education, ensuring users experience value early and often Drive Crossflow: Design cohesive transitions that reveal how our products work together and help users realize the full value of the platform. Scale design learning: Capture insights, build playbooks, and share patterns that help the broader team design for growth About You 4+ years in growth design within SaaS or technology environments Proven ability to design and iterate based on experimentation and user behavior Strong understanding of growth funnels, behavioral design, and motivation frameworks such as the Fogg Behavior Model Skilled in Figma and rapid prototyping tools Experience with analytics and experimentation platforms like Mixpanel, Amplitude, or FullStory Strong communicator who connects design intent to measurable outcomes Experience collaborating across Product, Growth, and Marketing to drive adoption and retention Experience with developer tools, CI/CD, or AI-driven platforms Work Location Remote from within the U.S or Hybrid from one of our offices in New York City, San Francisco, Boston, or Dallas What You Will Have at Harness Competitive salary Comprehensive healthcare benefits Flexible Spending Account (FSA) Employee Assistance Program (EAP) Flexible Time Off and Parental Leave Quarterly Harness TGIF-Off / 4 days Monthly, quarterly, and annual social and team-building events Recharge & Reset Program Monthly internet reimbursement Commuter benefit The anticipated base salary range for this position is between $170,00 and $202000 annually. Salary is determined by a combination of factors including location, level, relevant experience, and skills. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. The compensation package for this position may also include equity, and benefits. More details about our company benefits can be found at the following link: *************************************** A valid authorization to work in the U.S. is required Pay transparency$170,000-$202,000 USDHarness in the news: Harness AI Tackles Software Development's Real Bottleneck After 'Vibe Coding' Comes 'Vibe Testing' (Almost) Startup Within a Startup: Empowering Intrapreneurs for Scalable Innovation - Jyoti Bansal (Harness) Jyoti Bansal, Harness | the CUBEd Awards Eight years after selling AppDynamics to Cisco, Jyoti Bansal is pursuing an unusual merger Harness snags Split.io, as it goes all in on feature flags and experiments Exclusive: Jyoti Bansal-led Harness has raised $150 million in debt financing All qualified applicants will receive consideration for employment without regard to race, color, religion, sex or national origin. Note on Fraudulent Recruiting/Offers We have become aware that there may be fraudulent recruiting attempts being made by people posing as representatives of Harness. These scams may involve fake job postings, unsolicited emails, or messages claiming to be from our recruiters or hiring managers. Please note, we do not ask for sensitive or financial information via chat, text, or social media, and any email communications will come from the domain @harness.io. Additionally, Harness will never ask for any payment, fee to be paid, or purchases to be made by a job applicant. All applicants are encouraged to apply directly to our open jobs via our website. Interviews are generally conducted via Zoom video conference unless the candidate requests other accommodations. If you believe that you have been the target of an interview/offer scam by someone posing as a representative of Harness, please do not provide any personal or financial information and contact us immediately at *******************. You can also find additional information about this type of scam and report any fraudulent employment offers via the Federal Trade Commission's website (********************************************* or you can contact your local law enforcement agency.

Ethernovia is fundamentally changing how cars of the future are built by unifying in-vehicle networks into an end-to-end Ethernet system. Founded in 2018, we're inventing the future of automobile's communication! We are transforming automobiles' communication network to enable the autonomous driving, electrical vehicle (EV) and software defined revolutions. Our breakthrough compute, communication, and software virtualization ushers in a new era of car connectivity and capabilities. We bring together, accelerate, and unify the car's cameras/sensors, compute, and outside world to enable new advanced driver assistance features and services. Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds' leading technology investors, having secured $64m in Series A funding. (Ethernovia Raises $64 Million to Accelerate the Revolution of Vehicle Networks | Business Wire). Our financial backers include Porsche SE, Qualcomm, AMD, and Western Digital Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025. January 2024: Our CEO Ramin Shirani Named MotorTrend Software-Defined Vehicle Innovator Awards Winner (ethernovia.com) September 2023: Continental and Ethernovia Announce Partnership to Develop Automotive Switch in 7nm - Ethernovia Connected Car News: Helios, Continental, Ethernovia, Avanci, BMW, Mapbox, Porsche, SEMA, Honda, UltraSense, Flex Logix, Diodes Inc., Garmin, Toyota & Caruso | auto connected car news With talented employees on 4 continents, we have filed > 50 patents to date. Join Ethernovia's team to make a lasting impact on the future of mobility. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive their design from concept to silicon to their next car. Senior ASIC Front-End Design Engineer Summary: As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals. Work with system architects, software, hardware, and verification engineers to plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems. You will be on the leading edge of the development and definition of advanced, high-performance custom silicon that embodies functions from a wide range of protocols, algorithms, and applications. Expected to flesh out product definitions with precise specifications of: an ASIC's internal and external interactions, data flow, processing algorithms across a number of disciplines, resource management, and software interfaces. You will be a trusted self-starter who can work with very little guidance or oversight. This position is located in: United States - Remote Key Qualifications: BS and/or MS in Electrical Engineering, Computer Science, or related field Minimum 10+ years of ASIC RTL design and/or architecture experience Proven track record with the development of complex SoCs Strong understanding of digital design fundamentals and methodologies In-depth knowledge of Verilog/System Verilog and simulation tools. Self-motivated and able to work effectively both independently and in a team Additional Success Factors: Experience in any of the following areas: Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols) Video standards, protocols, processing Digital signal processing filters IP integration (SerDes, controllers, processors, etc.) Perl, TCL, C/C++, Make Personal Skills: Excellent communication/documentation skills. Attention to details. Collaboration across multidisciplinary and international teams. What You Can Expect from Ethernovia: Technology depth and breadth expansion that can't be found in a large company Opportunity to grow your career as the company grows Pre IPO stock options Cutting edge technology World class team Competitive base salary Flexible hours Medical, dental and vision insurance for employees Salary Range: The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $300,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits. #LI-Remote

Cornelis Networks delivers the world's highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world's most demanding computational challenges with our next-generation networking solutions. We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles. Cornelis Networks is hiring talented Sr. ASIC Design Engineers with deep experience in one or more of the key areas required to build the world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions. A good candidate will have 15+ years of ASIC design experience, with 10+ years of relevant experience in networking hardware design, proven expertise in 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking. Key Responsibilities: * Design and implement advanced Ethernet protocols for next-generation Ethernet switch ASICs, focusing on RTL development. * Develop microarchitecture specifications for Ethernet protocol blocks. * Implement Ethernet protocols such as Priority Flow Control, TCP, UDP, RoCEv2, VLAN, ECMP, DCQCN, ECN, and Security in Transmit and Receive pipelines using Verilog/System Verilog. * Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage. * Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure. * Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues. * Contribute to performance optimization and power-aware design strategies for Ethernet subsystems. Minimum Qualifications: * B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field. * 10+ years of industry experience in digital design with proficiency in Verilog and System Verilog. * Experience in RTL design for Ethernet protocols relevant to adapters and switches. * Familiarity with timing closure and modern physical design methodologies. * Proven ability in system-level debug and root cause analysis of technical issues. * Strong verbal and written communication skills. Preferred Qualifications: * Deep knowledge of Ethernet architecture and networking protocols (L2/L3/L4 layers). * Prior experience with Ethernet MAC integration and development of L2/L3/L4 protocols for ASICs, including system debug. * Expertise in multiple clock domain designs and asynchronous interfaces. * 10+ years of experience with scripting languages such as TCL, Python, or Perl. * Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime. Location: This is a remote position for employees residing within the United States. We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry. At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives. In addition to your base pay, you'll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave. Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Condor Computing is a brand-new member of the RISC-V revolution. Condor is aiming to fly high by building the industry's highest performance licensable RISC-V core. Our team of highly experienced CPU designers will create a new benchmark for power efficiency in high performance open-source computing. Condor is pleased to announce an exciting opportunity for a Senior RTL/Digital Design Engineer to join our team. This role offers the chance to collaborate with a talented group of architects, designers, and DV engineers as we develop the next generation of RISC-V CPUs. Here's what you'll be doing: Defining architectural frameworks Crafting microarchitectural designs Engaging in RTL design Enabling verification processes Establishing design practices that ensure first-pass success We hope you come with this background: A Master's or Bachelor's degree in electronic/electrical engineering or computer science 8+ years of experience in RTL Digital Design Experience in TL, microarchitecture, and architecture with advanced microprocessors and/or SOCs Strong microarchitecture and logic design experience, including high-speed deep sub-micron design and techniques for low power management A solid understanding of computer architecture Knowledge of physical timing in silicon devices and timing constraints for industry-standard EDA tools Familiarity with design tools for simulation, debugging, synthesis, timing analysis, and front-end RTL checking tools (like Lint, CDC/RDC, LEC, etc.) Experience with ASIC design techniques, pipelines, and basic CPU microarchitecture Experience in synthesis, physical layout concepts, static timing analysis, and clock domain crossing Proficiency in Verilog and System Verilog Strong skills in Unix and scripting languages such as make, Shell, Perl, or Python And while these aren't required, they would definitely be a plus: Strong written and verbal communication skills Good cross-site and cross-functional execution abilities Condor Computing is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law. We look forward to reviewing your application!

Job Title: Sr. Staff HW CAD Engineer Duties: Requiring limited supervision * Technical Lead for full chip integration activities * Manage development and deployment of methodologies for integration activities both internally and with ASIC design partner in leading technology nodes * Drive the overall Global Clock design including simulations and work closely with ASIC design partner in implementing the Global Clocks * Lead Sign-off activities like STA, EMIR, Physical Verification from defining the methodology to running these at block and full chip level * Manage the execution of blocks from Synthesis, P&R to Timing Sign-off, Physical Sign-off and Electrical Sign-off * Collaborate closely with the Microarchitecture/RTL team to help drive PPA improvements and resolve design issues. * Influence tools, flows and overall RTL to GDS2 physical design methodology with a data driven approach. * Will work remotely We offer competitive salaries and comprehensive benefits packages. Please email your resumes to ***************. On your resume, please clearly note ADV: [source] and job title. Groq is an equal opportunity employer. Salary Range: $270,000 - $280,000 Location: Santa Clara County #LI-DNI

Cooperidge Consulting Firm is seeking a Senior Analog/Mixed Signal ASIC Design Engineer. This position offers the opportunity to take ownership of the full lifecycle of integrated circuit design - from concept and architecture through detailed design, implementation, verification, and delivery. The engineer will contribute to innovative hardware solutions, collaborate across multiple domains, and provide technical leadership on complex projects. In this role, you will Design and simulate circuits at the transistor level Develop system-level concepts and optimize hardware for performance, power, and cost Assess feasibility of advanced requirements and algorithms Create and review design specifications and block-level implementations Guide verification, test planning, and chip-level design activities Mentor less experienced engineers and share best practices Contribute to proposals and technical development efforts Requirements Qualifications Proficiency in integrated circuit design, semiconductors, and computer architecture Hands-on experience with circuit design, simulation, and layout practices Ability to write detailed design specifications and manage small technical teams Excellent analytical and mathematical skills Strong organizational skills, attention to detail, and ability to meet deadlines Effective verbal and written communication skills Strong problem-solving skills with the ability to adapt to changing requirements Demonstrated ability to prioritize tasks and lead solutions for complex problems Education Bachelor's degree in Engineering or related field required Master's degree preferred Experience requirements: 5-7 years with BS, OR 3-5 years with MS, OR 0-2 years with PhD in ASIC Hardware Engineering or related Must be eligible to obtain and maintain a U.S. government security clearance Benefits Health Care Plan (Medical, Dental & Vision) Retirement Plan (401k, IRA) Life Insurance (Basic, Voluntary & AD&D) Paid Time Off (Vacation, Sick & Public Holidays) Family Leave (Maternity, Paternity) Short Term & Long Term Disability Training & Development Work From Home

Hardware Design/Test Engineer, Mid-level - FAA Function: Hardware Design and Testing Remote Work Option: Yes Salary Range: $90- $130k Security Requirements Must be a US citizen or a legal resident for three of the past five years. Public Trust cannot be granted without meeting the residency requirement. Must meet eligibility requirements for a US Public Trust security clearance (moderate risk), including a soft credit check and criminal background check. Please refer to the criteria listed in 5 CFR 731.202 to understand the Public Trust suitability requirements. Culture Cobec is consistently breaking the current mold for delivering services to our government clients. What does that mean? That means believing in a “people first” mentality, building high performance teams and empowering people to make informed decisions without going through a large bureaucratic system. Cobec values the well-being of employees and bestows tremendous trust in those people to negotiate work and non-work obligations. Cobec is where someone can bring their whole self to work and be themselves, never having to compromise their authenticity just to fit in. Lastly, we believe in the work we do, the goals and missions of our customers and the interpersonal relationships we have with clients, stakeholders and our people. Values and Expectations The successful candidate for this role embodies the same values as Cobec. We realize experience is important, however; Cobec believes a person's abilities and skills that align with our values (Relationships, Leadership, Passion, Accountability, Integrity, Innovation, Quality, Teamwork, Diversity, Commitment, & Respect) are the most important drivers for success in this role. In addition to exhibiting our values, a successful candidate for this role is expected to be a high performer, organized, dynamic, and have a positive attitude. Job Summary This position will provide technical support to Federal Aviation programs through the development, validation, and deployment of mission-critical hardware systems. The role requires close coordination with engineering and operations teams to ensure designs are fully tested, field-ready, and installed without jeopardizing National Airspace System (NAS) safety or performance. Years of Relevant Experience The position requires 10+ equivalent years of experience in hardware development, implementation, configuration, installation, testing, and IT networking, preferably in FAA or aerospace environments. Essential Job Functions The following duties are normal for this position. The omission of specific statements of duties does not exclude them from this position if the work is similar, related, and/or a logical assignment for this position. Other duties may be required and assigned. Design, prototype, and validate hardware components for National Airspace System modernization efforts Develop and execute test plans to evaluate hardware performance in both lab and simulated operational settings Participate in planning discussions with FAA stakeholders to coordinate field implementation schedules that maintain NAS safety Analyze test data and provide recommendations for design refinements or field installation strategies Support configuration management processes and hardware documentation updates Advise field teams and system integrators during site deployments to ensure correct hardware implementation Individuals will be required to contribute effectively to working groups through oral and written communication and cooperative working relationships. Education Requirements Bachelor's degree required, preferably electrical, mechanical, or test engineering, or a related technical discipline. Skills Requirements Knowledge of FAA systems and requirements for field installation in operational NAS environments Strong analytical, diagnostic, and documentation skills Ability to communicate complex technical issues to multidisciplinary audiences Strong communication and reporting skills for collaboration across FAA regional teams High level of proficiency with MS Office Products. Strong analytical background and excellent communication and interpersonal skills. Travel Travel required as needed by client/s and/or company to various FAA field sites. EEO Cobec, Inc. is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, sex, age, sexual orientation, gender identity, national origin, disability, veteran status or any other status protected by federal, state and local law. EEO is the Law

We are seeking a highly skilled and motivated Layout Engineer to support the development of high-performance analog and mixed-signal integrated circuits. The ideal candidate will have hands-on experience in advanced CMOS technologies and a strong experience in physical layout verification and optimization of analog blocks. Responsibilities + Execute full-custom layout for analog and mixed-signal blocks including ADCs, DACs, PLLs, LDOs, comparators, and temperature sensors. + Collaborate with circuit designers to optimize layout for performance, area, and power. + Perform floorplanning, block-level routing, and macro-level assembly. + Conduct physical verification using tools like Cadence Virtuoso, Synopsys Custom Compiler, and Calibre. + Address DRC/LVS, EMIR, and DFM issues and ensure layout meets manufacturing and reliability standards. + Support tape-out activities and post-layout simulation reviews. + Document layout strategies and contribute to design reviews. Essential Skills + Minimum 4 years of experience in analog circuit layout in advanced CMOS technologies (2-3nm, gate-all-around). + Proficiency with layout tools such as Cadence Virtuoso and Calibre. + Understanding of analog layout techniques including matching, shielding, reliability, and parasitic optimization. Additional Skills & Qualifications + 5 overall years of experience in the field. + Experience with advanced FINFET and GAA is a plus. + No degree is required to be eligible for this role. + Candidates with only digital layout or older technology experience are not suitable. Work Environment The team focuses on designing and creating layouts for analog mixed signal circuits in advanced CMOS nodes (2-3nm) supporting data center processor development. The typical day involves 80% heads-down design/layout work and 20% in meetings. The environment emphasizes analog layout rather than custom digital, working on projects in advanced CMOS technology for in-house SoC designs. Job Type & Location This is a Contract position based out of Redmond, WA. Pay and Benefits The pay range for this position is $50.00 - $60.00/hr. Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following: - Medical, dental & vision - Critical Illness, Accident, and Hospital - 401(k) Retirement Plan - Pre-tax and Roth post-tax contributions available - Life Insurance (Voluntary Life & AD&D for the employee and dependents) - Short and long-term disability - Health Spending Account (HSA) - Transportation benefits - Employee Assistance Program - Time Off/Leave (PTO, Vacation or Sick Leave) Workplace Type This is a fully remote position. Application Deadline This position is anticipated to close on Dec 19, 2025. About Actalent Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 30,000 consultants and more than 4,500 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law. If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing due to a disability, please email actalentaccommodation@actalentservices.com (%20actalentaccommodation@actalentservices.com) for other accommodation options.

Job Description We're seeking a talented Hardware Design Engineer to contribute to the development and verification of advanced digital designs. You'll work on cutting-edge ASIC and FPGA solutions, collaborating closely with cross-functional teams to bring next-generation technology to life. The position follows a flexible hybrid schedule. Responsibilities Participate in design architecture discussions and trade-off analysis. Write and verify RTL code for high-performance hardware components. Support hardware bring-up and provide technical assistance during customer engagements. Qualifications Proficient in SystemVerilog for digital design. Familiar with verification tools such as Questa, Incisive, or VCS. Experience with scripting (Python, Perl, Tcl) for process automation. Solid understanding of ASIC or FPGA logic design. Strong self-management, communication, and organizational skills. 5+ years of logic design experience and a BSEE degree. Preferred / Plus Experience with ASIC synthesis, timing constraints, CDC/RDC flows. Exposure to verification methodologies such as UVM. Familiarity with AMBA and AXI protocols.

Serving Maryland and the Greater Washington D.C. area, SageCor Solutions (SageCor) is a growing company bringing complete engineering services and true full lifecycle System Engineering services to areas requiring (or desiring) nationally-recognized expertise in high performance computing, large data analytics and cutting edge information technologies. Active TS/SCI w/ Polygraph required. Qualifications: ● Must possess an active TS/SCI Clearance with Full-Scope Polygraph ● Experience using VHDL, Verilog or SystemVerilog RTL Coding (for design and/or analysis of digital circuits) ● Experience with FPGA Design, synthesis, P&R tools (ex Vivado, Quartus) ● Experience utilizing Verilog/System and Verilog test bench development ● Experience working with Linux/Windows OS ● Knowledge of design simulation tools (Mentor, Cadence, Synopsys - 1 or more) ● Strong oral/written communication ● May provide FPGA support for vulnerability assessments, circuit analysis and/or reverse engineering efforts ● Location is onsite at Fort Meade, MD ● May have up to 20 hours of remote work per week once established and approved by the Customer Desired Skills: ● Experience with C/C++, Bash, Tcl/TK, GitLab ● Experience with FPGA design using Xilinx's Vivado Tool Suite ● Experience using soft/hard IP cores in FPGAs/ASICs (ex Zynq or Microblaze or RISC processors, memories, flash/NVM) ● Exposure to embedded software development ● Exposure to PCB design and development ● Python scripting Required Experience: Multiple openings for Junior, Senior, Principal and Sr. Principal Engineers: Minimum three (3) years' experience as a Design Engineer in integrated circuit or microelectronic component design or reverse engineering of the same is required. Bachelor's degree in electrical engineering or computer engineering from an accredited college or university is required. Five (5) years of additional hardware design engineering experience may be substituted for a bachelor's degree. Consistent with federal and state law where SageCor conducts business, SageCor Solutions provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status, or any other protected class.