Junior Engineer jobs at ARA - 9774 jobs

Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world - like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. You'll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. Visit our Careers website to learn more. At Applied Materials, we care about the health and wellbeing of our employees. We're committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Aid in the establishment and management of packaging suppliers and related processes and procedures. Develop test plans and perform laboratory testing on products, packages, and packaging materials. Support the Product Life Cycle (PLC) process by defining Design For Transportability (DFT) requirements and influencing product design. Develop and maintain global packaging standards and specifications for Applied Materials and its Supply Base. Provide advanced training and support to Packaging Engineer III. Duties will vary according to the project in progress and/or the specific goals of the department in which the incumbent works. Demonstrates depth and/or breadth of expertise in own specialized discipline or field May lead functional teams or projects with moderate resource requirements, risk, and/or complexity Impacts the achievement of customer, operational, project or service objectives; work is guided by functional policies At Applied Materials' CTO office, we are developing optical interconnect solutions for the next generation hyperscale computing and AI/ML. You will be working with a highly capable international team to develop advanced photonics packaging solution. You will lead optomechanical design, optical sub-assembly design, micro optics, fixture and tooling development. Those fixtures and tooling are expected to achieve micron level assembly accuracy. You are also expected to design / develop multi-fiber optical connectors and work with external vendors to develop connector eco-system. You are also expected to be familiar with various materials used in photonics industry, including but not limited to: glass, epoxy, silicon and other related materials. You daily activities includes working with 3D solid models, drawings, and documentation utilizing GD&T principles; assessing designs against environmental requirements; With a product focus, the individual will actively partner with other engineering disciplines and operations personnel to develop solutions that adhere to DFT and DFM requirements. D in optics, or mechanical engineering is desired. Industrial experience in optical communication industries is required. You should have expert level knowledge on optomechanical design, Solidworks or ProE, GD&T and ASME 14.5. Understanding of FEA for stress and thermal analysis, ideally understand the use of Ansys Mechanical and Icepak simulation tools Appreciation for Structured Problem Solving Full time Travel: Relocation Eligible: The salary offered to a selected candidate will be based on multiple factors including location, hire grade, job-related knowledge, skills, experience, and with consideration of internal equity of our current team members. In addition to a comprehensive benefits package, candidates may be eligible for other forms of compensation such as participation in a bonus and a stock award program, as applicable. For all sales roles, the posted salary range is the Target Total Cash (TTC) range for the role, which is the sum of base salary and target bonus amount at 100% goal achievement. Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law. In addition, Applied endeavors to make our careers site accessible to all users. If you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_****************, or by calling our HR Direct Help Line at ************, option 1, and following the prompts to speak to an HR Advisor. This contact is for accommodation requests only and cannot be used to inquire about the status of applications.

A leading airline company in San Francisco is seeking an experienced aircraft maintenance engineer to analyze and resolve technical challenges, ensure regulatory compliance, and provide detailed project management. Candidates should possess a Bachelor's degree in Engineering and have extensive knowledge in airline operations. This full-time role offers competitive compensation and a comprehensive benefits package. #J-18808-Ljbffr

Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world - like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. You'll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. Visit our Careers website to learn more. At Applied Materials, we care about the health and wellbeing of our employees. We're committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. As a Field Service Engineer [Customer Engineer] at Applied Materials, you serve as the direct liaison with customers, collaborating closely to install, maintain, and upgrade equipment. You'll use digital analytics for troubleshooting and apply basic diagnostic techniques to assess and address technical issues. Your responsibilities include performing preventative and corrective maintenance on various systems such as electrical, vacuum, mechanical, plasma, hydraulic, and gas systems. Additionally, you'll coordinate and communicate directly with customers to ensure smooth operations and exceptional service. If you like to troubleshoot hardware, solve complex problems and make equipment work better, this is the role for you. As a Field Service Engineer, you'll work in our state-of-the-art facility and at customer sites around the globe, where you are the face of Applied Materials and an integral part of a vibrant and diverse team. We train our Field Service Engineers to create and support the technology that the world relies on to manufacture semiconductor chips and related materials, every day. You'll work beside global customers to install, maintain and upgrade their Applied Materials equipment, delivering world-class support for multimillion-dollar production systems. Assist senior engineers with installing leading-edge customer equipment, performing scheduled preventative maintenance and corrective maintenance, and upgrading equipment Follow procedures you learn during your training, as well as published task plans, to test equipment and to diagnose and resolve technical problems Complete required job documentation, safety training and procedures for processing parts Professionally represent Applied Materials to the customer, using your "customer first" mindset Satisfy the company's and customer's on-site requirements, including safety, environmental and COVID-19 guidelines A high school diploma or equivalent An associate degree in electronics or engineering technologies, or equivalent work experience, or completion of military technical training and field experience Ability to read electrical and mechanical schematics Clear and effective written/verbal communications skills, with an emphasis on documenting details Proficiency in the Microsoft Office suite (Excel, Word and PowerPoint) Basic mechanical aptitude and knowledge in any of the following: pneumatics, hydraulics, electronics, vacuum, or thermodynamics Knowledge of hand tools and proper usage, including a digital multimeter 2-4 years of work experience in semiconductor industry or another equipment support industry You'll travel about 20% of the time, working with smart, awesome people like you You'll work on rotation and in shifts so that customers have ongoing support sit, stoop, kneel, crouch, twist, reach and stretch to reach equipment when needed, and stand for extended periods of time You'll need a valid driver's license and passport At Applied Materials, we care about the wellbeing of our people, and we strive to support you in ways that extend beyond your work environment. Your benefits package will be customized for your country of residence and may include: top-tier medical, dental and vision plans; disability insurance; life insurance; retirement; Additionally, all employees can take advantage of our company-sponsored global programs, including our Employee Assistance Program, Travel Accident/Medical Benefits Abroad, the company's employee stock purchase program and a subscription to wellbeing tools. We value social responsibility, too: Our worldwide "Giving" program encourages employee giving and volunteering globally, while The Applied Materials Foundation provides an employee match of up to US$3,000 per employee per year. Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We're the brain (and the brawn) behind every new technology development-whether it's building semiconductor chips for smartphones and computers, or the underpinnings for robotics, AI and even smart TV display screens. We take deep pride in our Culture of Inclusion, and we celebrate the diverse backgrounds, perspectives and experiences that help us build stronger, more resilient teams. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status or any other basis prohibited by law. Full time Travel: Relocation Eligible: The salary offered to a selected candidate will be based on multiple factors including location, hire grade, job-related knowledge, skills, experience, and with consideration of internal equity of our current team members. In addition to a comprehensive benefits package, candidates may be eligible for other forms of compensation such as participation in a bonus and a stock award program, as applicable. For all sales roles, the posted salary range is the Target Total Cash (TTC) range for the role, which is the sum of base salary and target bonus amount at 100% goal achievement. Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law. In addition, Applied endeavors to make our careers site accessible to all users. If you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_****************, or by calling our HR Direct Help Line at ************, option 1, and following the prompts to speak to an HR Advisor. This contact is for accommodation requests only and cannot be used to inquire about the status of applications.

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. Academic, educational, internship, or project experience with physical design and 3D integration technologies such as 3D-IC, 2.5D, chip stacking, vertical stacking, integrity, or Through-Silicon Vias (TSV). Experience with running industry standard tools for chip design (e.g., from Synopsys, Cadence, or Siemens EDA). Preferred qualifications Experience with advanced finfet and gate-all-around technology nodes, and enabling physical design flows in these nodes. Experience in delivering optimized digital place-and-route blocks leading to test chip or product tapeouts. Experience with programming/scripting (TCL, Python, or Perl). Expertise with Power, Performance, and Area (PPA) design trade-offs and optimizations in physical design spaces. Understanding of standard cells, SRAMs, power, noise, and IR analysis. Excellent presentation and communication skills. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Physical Design Engineer in 3D Technology, you will collaborate with technology, physical design, circuit design, and hardware architecture teams to overcome the slowing of Moore's Law while delivering ASIC's and SoC's. You will help develop new 3D technology physical design methodologies to drive best product Power Performance Area (PPA) by optimizing across technology, digital block implementation, clock distribution, floorplanning, circuits, memories, and third-party IPs. You will drive new physical design flows that co‑optimize across the entire design methodology space, including 3D and see these through from inception to maturity and tapeout. This will include high impact physical design innovations with through‑silicon vias (TSVs) requiring methodology and verification flow development and ratification. As part of this work, you will participate in the development of exceptional technology in high performance computing and ensure product success. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full‑time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google. Responsibilities Drive development of a leading edge 3D technology platform for custom, high performance ASIC's and SoC's, from design through manufacturing, packaging, and test. Optimize digital blocks for performance, power, area, and reliability using physical design and circuit techniques. Define optimal methodologies by investigating performance, power, and area across different technology nodes and implementation techniques. Work with our physical design, technology, circuits, and architecture teams and IP partners in advanced Complementary Metal‑Oxide‑Semiconductor (CMOS) nodes. Design and build custom circuits at the transistor and gate levels to support physical design and floorplan optimization. Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire. Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr

Elastic, the Search AI Company, enables everyone to find the answers they need in real time, using all their data, at scale - unleashing the potential of businesses and people. The Elastic Search AI Platform, used by more than 50% of the Fortune 500, brings together the precision of search and the intelligence of AI to enable everyone to accelerate the results that matter. By taking advantage of all structured and unstructured data - securing and protecting private information more effectively - Elastic's complete, cloud‑based solutions for search, security, and observability help organizations deliver on the promise of AI. What is the Role As a Consulting Engineer - Search, you will play a pivotal role in helping our customers realize the value of Elastic's Solutions. Acting as a trusted technical advisor, you will work with enterprises to design, deliver, and scale architectures that improve application performance, infrastructure visibility, and end‑user experience. You'll collaborate with Elastic's Professional Services, Engineering, Product, and Sales teams to accelerate adoption of the Elastic Observability platform, ensuring customers maximize the value of their data while achieving business outcomes. This is a highly impactful role, with opportunities to guide strategy, lead complex implementations, and mentor both customers and teammates. What You Will Be Doing Translate business and technical requirements into scalable, outcome‑driven solutions built on the Elastic Stack. Lead end‑to‑end delivery of customer engagements - from discovery and design through implementation, enablement, and optimization. Partner with customers to architect, deploy, and operationalize Elastic solutions that drive measurable value and adoption. Provide technical oversight, guidance, and enablement to customers and teammates throughout project lifecycles. Collaborate cross‑functionally with Sales, Product, Engineering, and Support to ensure successful outcomes and continuous improvement. Capture and share best practices, lessons learned, and solution patterns across the Elastic Services community. Contribute to internal enablement, mentoring, and a culture of continuous learning and collaboration Apply your expertise to optimize queries, tune clusters, and handle high query/indexing throughput at enterprise scale. Collaborate with product and engineering teams to identify product improvements, extensions, and defects based on field feedback Operationalize vector search (e.g., kNN, ANN, hybrid embeddings) with Elastic's vector capabilities and ML models or similar. Profile and tune queries for high‑QPS environments with sub‑second latency targets. What You Bring 5+ years as a consultant, engineer, or architect with deep expertise in Enterprise Search technologies and concepts, including generative AI. Hands‑on experience deploying Elastic Search solutions or similar platforms (Solr, Algolia, AWS OpenSearch, Palantir, Unbxd, e‑commerce site search engines). Strong experience in custom search solution design, query development, relevancy tuning, and NLP use cases. Expertise in distributed systems and large‑scale application infrastructure. Proficiency in at least one programming language; knowledge of open‑source machine learning/AI frameworks preferred. Knowledge or certification in Kubernetes, Linux, Java, databases, Docker, AWS/Azure/GCP, Kafka, Redis, VMs, Lucene. Familiarity with DevOps practices: Docker, Kubernetes, Terraform, CI/CD. Ability to manage delivery from proof‑of‑concept through production rollout, while mentoring client teams for long‑term success. Familiarity with modern NLP and AI ecosystems (transformers, Hugging Face, vector DBs like Pinecone or Weaviate) as applied to search. Strong communication and presentation skills, with experience working directly with customers to gather requirements and deliver solutions. Bachelor's, Master's, or PhD in Computer Science, Engineering, or related field, or equivalent experience. Comfortable working in highly distributed teams, both remote and on‑site when needed. May require significant travel to customer sites to support engagements and solution implementations; candidates should be comfortable with varying levels of travel based on business needs. Bonus Points: Elastic Certified Engineer certification. Experience at a Big 4 consulting firm. Hands‑on experience with Ansible, Terraform, JavaScript, ECK/Kubernetes. Familiarity with machine learning and AI applied to search solutions. Experience contributing to open‑source projects or documentation. Public speaking experience at conferences, meetups, or enterprise workshops. Compensation for this role is in the form of base salary. This role does not have a variable compensation component. The typical starting salary range for new hires in this role is listed below. In select locations (including Seattle WA, Los Angeles CA, the San Francisco Bay Area CA, and the New York City Metro Area), an alternate range may apply as specified below. These ranges represent the lowest to highest salary we reasonably and in good faith believe we would pay for this role at the time of this posting. We may ultimately pay more or less than the posted range, and the ranges may be modified in the future. An employee's position within the salary range will be based on several factors including, but not limited to, relevant education, qualifications, certifications, experience, skills, geographic location, performance, and business or organizational needs. Elastic believes that employees should have the opportunity to share in the value that we create together for our shareholders. Therefore, in addition to cash compensation, this role is currently eligible to participate in Elastic's stock program. Our total rewards package also includes a company‑matched 401k with dollar‑for‑dollar matching up to 6% of eligible earnings, along with a range of other benefits offered with a holistic emphasis on employee well‑being. The typical starting salary range for this role is: $110,900-$175,500 USD The typical starting salary range for this role in the select locations listed above is: $133,200-$210,700 USD Additional Information - We Take Care of Our People As a distributed company, diversity drives our identity. Whether you're looking to launch a new career or grow an existing one, Elastic is the type of company where you can balance great work with great life. Your age is only a number. It doesn't matter if you're just out of college or your children are; we need you for what you can do. We strive to have parity of benefits across regions and while regulations differ from place to place, we believe taking care of our people is the right thing to do. Competitive pay based on the work you do here and not your previous salary Health coverage for you and your family in many locations Ability to craft your calendar with flexible locations and schedules for many roles Generous number of vacation days each year Increase your impact - We match up to $2000 (or local currency equivalent) for financial donations and service Up to 40 hours each year to use toward volunteer projects you love Embracing parenthood with minimum of 16 weeks of parental leave Different people approach problems differently. We need that. Elastic is an equal opportunity employer and is committed to creating an inclusive culture that celebrates different perspectives, experiences, and backgrounds. Qualified applicants will receive consideration for employment without regard to race, ethnicity, color, religion, sex, pregnancy, sexual orientation, gender perception or identity, national origin, age, marital status, protected veteran status, disability status, or any other basis protected by federal, state or local law, ordinance or regulation. We welcome individuals with disabilities and strive to create an accessible and inclusive experience for all individuals. To request an accommodation during the application or the recruiting process, please email candidate_accessibility@elastic.co. We will reply to your request within 24 business hours of submission. Applicants have rights under Federal Employment Laws, view posters linked below: Family and Medical Leave Act (FMLA) Poster; Pay Transparency Nondiscrimination Provision Poster; Employee Polygraph Protection Act (EPPA) Poster and Know Your Rights (Poster) Elasticsearch develops and distributes encryption software and technology that is subject to U.S. export controls and licensing requirements for individuals who are located in or are nationals of the following sanctioned countries and regions: Belarus, Cuba, Iran, North Korea, Russia, Syria, the Crimea Region of Ukraine, the Donetsk People's Republic (“DNR”), and the Luhansk People's Republic (“LNR”). If you are located in or are a national of one of the listed countries or regions, an export license may be required as a condition of your employment in this role. Please note that national origin and/or nationality do not affect eligibility for employment with Elastic. Please see here for our Privacy Statement. #J-18808-Ljbffr

A global technology company is looking for a seasoned software engineer to enhance AI capabilities within their observability platform. Candidates should have a strong background in AI/ML systems, cloud computing, and robust technical leadership. This role is pivotal in driving innovation in data analysis and delivering scalable solutions. The ideal candidate will thrive in an agile environment and provide mentorship to junior engineers. Enjoy competitive salaries and benefits while contributing to impactful technology solutions. #J-18808-Ljbffr

A leading technology company in San Jose is seeking a skilled engineer to develop applications based on generative AI models such as GPT-4. This role involves collaborating with cross-functional teams to optimize performance and ensure reliability, as well as engaging in cutting-edge AI developments. The ideal candidate will have a Bachelor's or Master's degree in a relevant field and deep knowledge of machine learning methodologies. Competitive compensation, benefits, and opportunities for growth will be offered. #J-18808-Ljbffr

A leading technology company in San Jose is looking for a recent graduate or PhD candidate for an AI/ML development role. The position requires backend development skills in Go or Python and understanding of LLM infrastructure. Candidates should be ready to collaborate with cross-functional teams, optimizing models for real-world deployment. This role offers competitive salary ranges based on location, benefiting from Cisco's extensive employee perks and growth opportunities. #J-18808-Ljbffr

corporate_fare Google place Sunnyvale, CA, USA Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Apply link Copy link Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with physical design. Experience in physical design areas such as synthesis, place and route, Static Timing Analysis (STA), verification, or power analysis. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience in block/subchip level PnR for complex SoC. Experience with multiple-cycles of SoC in ASIC design. Experience with scripting languages such as Perl, Python, or Tcl. Experience with layout verification and design rules. Experience in IP integration (e.g., memories, IO's and Analog IP) with the knowledge of semiconductor device physics and transistor characteristics. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a System on a Chip (SoC) Physical Design Engineer, you will collaborate with Register-Transfer Level (RTL), Design for Testing (DFT), Floorplan, and full-chip Sign off teams. Additionally, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Participate in the Physical Design of blocks for complex Tensor Processing Unit (TPU) chips. Contribute to the design and closure of the subchip and individual blocks from Register-Transfer Level-to-Graphic Design System . Collaborate with RTL/Design and Product Development teams to achieve the best Power Performance Area (PPA) possible. This includes conducting feasibility studies for new micro-architectures as well as optimizing runs for best Quality of Results (QoR). Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr

corporate_fare Google place Sunnyvale, CA, USA Apply Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with physical design. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with scripting languages such as Perl, Python, or Tcl. Experience with constraints, synthesis or clock tree synthesis (CTS). Experience in block/subchip level place and route for SoC or with multiple-cycles of SoC in ASIC design. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As a Physical Design Engineer, you will collaborate with RTL, design for testing (DFT), floorplan, and full‑chip signoff teams. Additionally, you will solve technical problems with micro‑architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full‑time position is $113,000-$161,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google. Responsibilities Participate in the physical design of blocks for TPU chips. Contribute to the design and closure of the subchip and individual blocks from RTL-to-GDS. Collaborate with RTL/Design and physical design (PD) teams to achieve the best power/performance/area (PPA) possible. Conduct feasibility studies for new microarchitectures as well as optimizing runs for best quality of result (QoR). Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire. Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr

Apply Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Qualifications PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. Academic, educational, internship, or project experience with physical design. Preferred qualifications Experience in scripting using Languages like Python, Tcl, Perl. Proficiency in fundamental SoC architecture and hardware description languages such as Verilog, facilitating effective collaboration with logic design teams to resolve timing issues. Knowledge of fundamental VLSI and physical design principles, including expertise in semiconductor device physics and transistor structures (e.g., finfet, Gate all around). Understanding of Static Timing Analysis(STA), Clock Domain Crossings (CDC), clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis. Understanding of standard cells, SRAMs, power, noise, and IR analysis. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As a Physical Design Engineer, you will collaborate with Register‑Transfer Level (RTL), Design for Testing (DFT), floorplan, and full‑chip sign off teams. Additionally, you will solve technical problems with innovative micro‑architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full‑time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Participate in the physical design of blocks for complex Tensor Processing Unit (TPU) chips. Contribute to the design and closure of the subchip and individual blocks from Register‑Transfer Level‑to‑Graphic Design System (RTL2GDSII). Collaborate with RTL/Design and Product Development teams to achieve the best Power Performance Area (PPA) possible. This includes conducting feasibility studies for new micro‑architectures as well as optimizing runs for best Quality of Results (QoR). Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr

A leading technology firm in San Francisco is looking for an innovative engineer to develop generative AI applications. This role requires a PhD in a relevant field and backend development experience, preferably in Go or Python. You will work with cutting-edge technologies and collaborate with world-class teams to create and implement AI solutions. Cisco offers a competitive salary and a collaborative work environment that fosters growth and innovation. #J-18808-Ljbffr

A leading technology company in San Francisco is seeking a professional to develop AI/ML solutions. You will work closely with various teams to implement and optimize applications based on large language models. The ideal candidate has a Bachelor's or Master's degree in a relevant field and a strong understanding of machine learning algorithms. Join us to contribute to innovative projects and collaborate in a dynamic environment. #J-18808-Ljbffr

A leading network and security company is seeking an Engineering Sr Manager to lead a team building and operating distributed cloud services. The role requires over 10 years of software engineering experience, including significant leadership experience. The successful candidate will drive engineering best practices, ensure secure and scalable solutions, and collaborate across teams. This position is hybrid, allowing flexibility in work location, and offers an attractive salary range between $216,800 and $325,200, complemented by various benefits. #J-18808-Ljbffr

A leading technology company in San Jose is seeking an experienced engineer to join their analog/mixed signal IP design team. This role involves designing next generation I/O interfaces, with a strong emphasis on mixed signal design and leading technical projects. The ideal candidate will possess a degree in Electrical Engineering and have hands-on experience with high speed designs and communication tools. This position offers competitive benefits and is not eligible for visa sponsorship. #J-18808-Ljbffr

MEP Project Engineer - High-Rise Construction (Miami, FL) G&E Partners is partnered with a leading high-rise General Contractor in Miami that is actively expanding its project teams due to a strong pipeline of luxury residential and mixed-use tower projects. This is a fully on-site role supporting complex, multi-story builds and offers long-term career progression within a growing Florida operation. Responsibilities Support MEP scopes across all phases of high-rise construction Coordinate with mechanical, electrical, plumbing, and fire protection subcontractors Review submittals, RFIs, shop drawings, and MEP schedules Track procurement and long-lead equipment (switchgear, generators, chillers, etc.) Assist with inspections, testing, and commissioning activities Work closely with Project Managers, Superintendents, and BIM/VDC teams Maintain documentation and ensure compliance with contract requirements Requirements 1-5+ years of experience in construction, ideally with a GC or large MEP subcontractor Exposure to high-rise, multifamily, hospitality, or large commercial projects preferred Strong understanding of mechanical, electrical, and plumbing systems Degree in Construction Management, Engineering, or related field preferred Comfortable working fully on-site in Miami Why Join Career-defining high-rise projects (30+ to 100+ stories) Strong project backlog and long-term stability Clear path into MEP Project Management Competitive salary, bonus, and full benefits package

A leading AI contracting platform is seeking a Senior Manager for the Solution Engineering and Technical Services team in San Francisco. This role involves leading a skilled team, collaborating with other departments to drive customer value, and supporting sales efforts. The ideal candidate will have a strong background in solution engineering, excellent leadership skills, and experience in a B2B SaaS environment. This position offers a competitive OTE range between $180,000 and $220,000 per year, along with comprehensive benefits. #J-18808-Ljbffr

A globally leading consumer device company headquartered in Cupertino, CA is looking for a hands-on Battery Electrical Test Engineer to support day-to-day lab testing and validation activities. This role is ideal for someone who thrives in a fast-paced lab environment, enjoys solving complex electrical problems, and takes pride in producing clean data and clear documentation. Job Responsibilities: • Execute battery EE-level tests and deliver accurate, detailed test reports • Generate KPIs to support daily lab operations and performance tracking • Review BMU schematics and layouts to verify conformance and assess testability • Conduct investigations and prepare supporting technical reports • Write test plans, co-develop procedures, and analyze validation data • Set up and run complex test configurations using high-accuracy lab equipment • Troubleshoot test equipment and sample issues • Use a variety of measurement tools to test batteries and cells Candidate Requirements: • Bachelor's degree in Electrical Engineering or related field • Strong understanding of EE bench test equipment (oscilloscopes, meters, data loggers, power supplies) • Extensive lab experience with an ownership-driven mindset • Data-driven decision-making skills • Strong documentation and communication skills • Experience with automated test platforms and scripting (Python or similar) • 3-5 years of relevant experience Type: Contract Duration: 12 months with extension Work Location: Cupertino, CA (100% onsite) Pay Rate: $50.00 - $65.00 (DOE)

The Mission Concepts and Capabilities (MCC) Division of Applied Research Associates, Inc. (ARA) is seeking to contingently hire a **Senior Engineer** for ARA's effort supporting the Assistant Secretary of War for Critical Technologies (OASW(CT)). This position will support the Critical Technology Area (CTA) offices within OASW(CT). This work requires a candidate with experience in systems engineering, software engineering, and/or subject matter expertise in CTA relevant fields. The candidate will perform functions such as: + Development of technology roadmaps in areas such as artificial intelligence (AI), directed energy, communication and sensing technologies, precision navigation, electronic warfare, hypersonics, biomanufacturing, and/or contested logistics + Identify opportunities to conduct short-term sprints that deliver capabilities + Development of strategy documents + Development of strategic implementation plans + Coordination with Service and interagency SMEs to cultivate partnerships that advance OASW(CT) priorities and objectives **Required Qualifications:** + BS degree in scientific or technical discipline from an accredited institution + 10+ years of relevant experience + Current DoW TOP SECRET clearance with SCI eligibility + Experience with one or more of the following: artificial intelligence (AI), directed energy, communication and sensing technologies, precision navigation, electronic warfare, hypersonics, biomanufacturing, and/or contested logistics + Experience developing and transitioning technology + Experience developing roadmaps + Experience preparing presentations for, and presenting reports to senior leaders + Experience in interfacing, communicating, and collaborating with government personnel at senior levels **Desired Qualifications:** + Master's degree from an accredited institution + Experience supporting the Office of the Secretary of War and Critical Technology Areas (CTAs) This position is contingent upon award of a contract. **COMPANY INFORMATION:** Applied Research Associates, Inc. is an employee-owned international research and engineering company recognized for providing technically superior solutions to complex and challenging problems in the physical sciences. The company, founded in Albuquerque, NM, in 1979, currently employs over 2000 professionals. ARA offices throughout the United States and Canada provide a broad range of technical expertise in defense technologies, civil technologies, computer software and simulation, systems analysis, environmental technologies, and testing and measurement. The corporation also provides sophisticated technical products for environmental site characterization, pavement analysis, and robotics. At ARA, employees are our greatest assets. The corporation realizes that employee ownership generates greater creativity and initiative along with higher performance and customer satisfaction levels. ARA gives its employees the tools, training, and opportunities to take more active roles as owners. The culture is challenging; innovation and experimentation are the norm. Employees are eligible for contributions which not only add to the company's success, but also their own through the Employee Stock Ownership Plan (ESOP). The motto, "Engineering and Science for Fun and Profit" sums up the ARA experience. For additional information and an opportunity to join this unique workplace, please visit our website at *********** . Please apply at ******************* for the **Senior Engineer** position. **Qualifications** **Behaviors** **Required** + **Team Player:** Works well as a member of a group + **Functional Expert:** Considered a thought leader on a subject + **Enthusiastic:** Shows intense and eager enjoyment and interest + **Detail Oriented:** Capable of carrying out a given task with all details necessary to get the task done well **Motivations** **Required** + **Self-Starter:** Inspired to perform without outside help + **Job Security:** Inspired to perform well by the knowledge that your job is safe + **Growth Opportunities:** Inspired to perform well by the chance to take on more responsibility + **Goal Completion:** Inspired to perform well by the completion of tasks + **Ability to Make an Impact:** Inspired to perform well by the ability to contribute to the success of a project or the organization **Education** **Required** + Bachelors or better **Experience** **Required** + 10 years: Relevant work experience Equal Opportunity Employer/Protected Veterans/Individuals with Disabilities This employer is required to notify all applicants of their rights pursuant to federal employment laws. For further information, please review the Know Your Rights (**************************** notice from the Department of Labor.