Design Verification Engineer jobs at Arrow Electronics - 4914 jobs

Description:Join Our Team as an Avionics Circuit Design Engineer where you will work on the development of a sophisticated state-of-the-art avionics product in a world class Integrated Product Development environment. Location: This position does not support teleworking; the preferred candidate will be located near our Lockheed Martin Space facility one of the Coolest places to work: Littleton CO, and be expected to work in the office. Space is a critical domain, connecting our technologies, our security, and our humanity. While others view space as a destination, we see it as a realm of possibilities, where we can do more - we can innovate, invest, inspire, and integrate our capabilities to transform the future. At Lockheed Martin Space, we aim to harness the full potential of space to cultivate innovation, reduce costs, and push the boundaries of what technology can achieve. We're creating future-ready solutions, focusing on resiliency and urgency through our 21st Century Security vision. We're erasing boundaries and forming partnerships across industries and around the world. We're advancing spacecraft and the workforce to fuel the next generation. And we're reimagining how space can connect us, ensuring security and prosperity. Join us in shaping a new era in space and find a career that's built for you. What does this role look like? As a Circuit Design Engineer, you will work on the development of a sophisticated state-of-the-art Avionics product in a world class Integrated Product Development environment. Key activities you will accomplish in this role: • Design/Capture electrical schematics and guide the board layouts. • Perform electrical Worst Case Analysis and Electrical Parts Stress Analysis. • Work on a cross-functional team in the development and integration of world class avionics systems. • Resolve test anomalies and troubleshooting, and generation, review and presentation of Product Certification, and also support system level testing. To be effective in this role, you will need: • Experience supporting the technical evaluation of design and requirements verification. • Experience in different phases of aerospace hardware development cycle. • Experience interacting with peers, management and government customers. • Experience in presentations and in written communication skills. • Missile design experience. • 5+ years professional experience; 3+ years with Masters degree. • Must have an active DoD Secret clearance, thus you are a US Citizen. Why Lockheed Martin? Our employees play an active role in strengthening the quality of life where we live and work by volunteering more than 850,000 hours annually. Learn more about Lockheed Martin's comprehensive benefits package. Find out more on how we proudly support Hiring Our Heroes. At Space we value your skills, training, and education. We believe that by applying the highest standards of business ethics and visionary thinking, everything is within our reach - and yours as a Lockheed Martin Space employee... join us to experience your future! Let's do Space! Basic Qualifications: • Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education. • Experience in electronics design, with a focus on CCA design and development. • Experience as a technical lead or responsible engineer. • Active Secret clearance thus US Citizenship is required. Desired Skills: • Experienced at leading teams through challenging engineering and/or programmatic issues. • Experience on Space and/or Missile Defense Missions. • Experience in electronic systems schematic creation and interpretation, and Electronics Modeling/Simulation Tools such as SPICE. • Experience in schematic capture using Zuken or similar tools. • Experience with PSPICE, Saber or other electronics simulation tool experience. • Experience performing electronics analysis (Worst Case Analysis, Electrical Parts Stress Analysis, Failure Modes and Effects Critical Analysis). • Demonstrated good communication and presentation skills with the ability to articulate complex technical issues to peers, management, subcontractors and customers. • Demonstrated ability to work in a fast-paced, dynamic, collaborative team environment and to build consensus among peers and effective relationships with team members. • Demonstrated strong problem solving and conflict resolution skills. • Adaptable to new situations and demonstrate self-initiative in solving complex problems. • Able to work effectively in a diverse team environment. Security Clearance Statement: This position requires a government security clearance, you must be a US Citizen for consideration. Clearance Level: Secret Other Important Information You Should Know Expression of Interest: By applying to this job, you are expressing interest in this position and could be considered for other career opportunities where similar skills and requirements have been identified as a match. Should this match be identified you may be contacted for this and future openings. Ability to Work Remotely: Onsite Full-time: The work associated with this position will be performed onsite at a designated Lockheed Martin facility. Work Schedules: Lockheed Martin supports a variety of alternate work schedules that provide additional flexibility to our employees. Schedules range from standard 40 hours over a five day work week while others may be condensed. These condensed schedules provide employees with additional time away from the office and are in addition to our Paid Time off benefits. Schedule for this Position: 9x80 every other Friday off Pay Rate: The annual base salary range for this position in California, Massachusetts, and New York (excluding most major metropolitan areas), Colorado, Hawaii, Illinois, Maryland, Minnesota, New Jersey, Vermont, Washington or Washington DC is $118,700 - $209,300. For states not referenced above, the salary range for this position will reflect the candidate's final work location. Please note that the salary information is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market and business considerations when extending an offer. Benefits offered: Medical, Dental, Vision, Life Insurance, Short-Term Disability, Long-Term Disability, 401(k) match, Flexible Spending Accounts, EAP, Education Assistance, Parental Leave, Paid time off, and Holidays. (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year. This position is incentive plan eligible. Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics. The application window will close in 90 days; applicants are encouraged to apply within 5 - 30 days of the requisition posting date in order to receive optimal consideration. Join us at Lockheed Martin, where your mission is ours. Our customers tackle the hardest missions. Those that demand extraordinary amounts of courage, resilience and precision. They're dangerous. Critical. Sometimes they even provide an opportunity to change the world and save lives. Those are the missions we care about. As a leading technology innovation company, Lockheed Martin's vast team works with partners around the world to bring proven performance to our customers' toughest challenges. Lockheed Martin has employees based in many states throughout the U.S., and Internationally, with business locations in many nations and territories. Experience Level: Experienced Professional Business Unit: SPACE Relocation Available: Possible Career Area: Electrical Engineering Type: Full-Time Shift: First

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, GPU. You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices.The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT pre-silicon verification and support for silicon bring-up of GPU core. Description As a DFT Verification engineer your primary responsibilities will include: Reviewing Architecture and Design Specifications Extracting design features and developing attributes and verification plans Working with designers to verify DFT implementation and run various checks Implementing test benches, generating advised/constrained random tests Debugging failures, running gate level simulations, supervising bugs, and closing coverage Handling schedules and supporting multi-functional engineering effort Assisting in verification flows, automation scripts and regressions Minimum Qualifications Bachelors Degree + 10 Years of Experience Preferred Qualifications Proven experience in large processors and/or GPU/SOC designs Hands‑on experience in directed or random verification, coverage analysis and assertions Proficient in scripting languages such as Perl, Python or TCL Strong Object‑Oriented Programming skills Solid Understanding of Design Verification (DV) methodologies for verifying DFT implementation in pre‑silicon Excellent skills in problem solving, communication and desire to seek new challenges Experience working under strict schedule deadlines with the ability to manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $163,300 and $290,100, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . #J-18808-Ljbffr

San Francisco Bay Area, California, United States Hardware At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple's customers daily.This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out. Description In this role, you will be responsible for ensuring bug‑free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro‑architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable. Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring‑up, DV environment bring‑up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test‑benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality. Responsibilities Study design specification and create test plan Develop infrastructure in SystemVerilog/UVM to stress the design Develop and fix failures from regressions, close bugs Use LLMs to do verification efficiently Minimum Qualifications BS degree in technical subject area with minimum 3 years of proven experience or equivalent Preferred Qualifications Strong knowledge of OOP, SystemVerilog and UVM Strong knowledge in developing scalable and portable test‑benches Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations Some working experience using LLMs for efficiency and quality Experience with power‑aware (UPF) or similar verification methodology Knowledge of one of the scripting languages such as Python, Perl, TCL Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required Knowledge of formal verification methodology is a plus but not required Knowledge of emulation for verification technologies is a plus but not required At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $147,400 and $272,100, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr

Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love to have you join us. Description As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all subject areas (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test optimally. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP: Neural Engine hardware DRAM subsystem, memory controller logic Encode and Decode systems for ProRes and other codec formats such as VP9, AV1 Hardware security, including cryptographic algorithm implementations High-Speed IO standards such as PCI Express, DisplayPort, MIPI Power management and fabric infrastructure Memory cache management Display Subsystem for variety of panels and products These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It's up to you! Minimum Qualifications Minimum of BS + 3 years relevant industry experience. Preferred Qualifications Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy Knowledge of SystemVerilog, digital simulation and debug Knowledge of computer architecture and digital design fundamentals SW programming skills with knowledge of data structures and algorithms Experience with Python, Perl, or similar scripting language Ability to work independently to deliver the project goals Knowledge of verification methodologies like UVM Experience with C/C++, assembly is a plus. Excellent interpersonal skills and the dream to tackle diverse challenges. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $139,500 and $258,100, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. #J-18808-Ljbffr

Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other's ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It's the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you'll do more than join something - you'll add something. Do you have a passion for innovation and technical excellence? Do you thrive on solving complex problems that push the boundaries of what's possible? Join our team to verify innovative, high-throughput cellular baseband modems and transceiver link controllers that power communication for millions of users worldwide. Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems. Working on innovative baseband modems and RF link controllers for Apple's SOCs, you'll craft highly reusable UVM verification environments that set the standard for quality and efficiency. You'll develop comprehensive coverage-driven and directed test cases that thoroughly validate complex IP and subsystem designs, working closely with multi-functional teams throughout the process. In this role, you'll drive methodology innovation by deploying sophisticated tools and techniques that elevate verification practices and ensure tape-out readiness. Collaborating with product development teams across Apple, you'll help deliver cellular systems that redefine industry capabilities and enhance customer experiences globally. This position offers exceptional opportunities to deepen your expertise across cellular protocols, complex IP and subsystem architectures, advanced fabric protocols, and sophisticated debug methodologies. You'll gain experience with best-in-class design verification practices, co-verification techniques with models and firmware, and industry-standard low-power architectures. We're looking for engineers with hands‑on ASIC design verification experience using reusable verification methodologies such as UVM. The ideal candidate excels at detailed test planning, adapts optimally to evolving requirements, knowledge of the latest ML based tools to improve productivity and is driven to achieve the highest quality standards. You thrive in collaborative environments and are eager to address the verification challenges inherent in complex, high-performance cellular systems. If you want to contribute to products that impact customers worldwide while advancing your technical expertise, we'd love to hear from you. Responsibilities Construct detailed test plans for various components of the design including use cases, through collaborative work with multi‑functional teams. Create coverage driven verification plans from specifications, review and refine to achieve coverage targets. Architect UVM‑based, reusable test benches with components for stimulus, checkers, VIPs and reference models. Work with DV methodology architects to improve verification flow. Implement test plans from RTL simulation bring‑up to sign‑off; report and debug failures. Maintain regressions and report the verification progress against test plans and coverage metrics. Minimum Qualifications BS and a minimum of 3 years relevant industry experience. Strong knowledge of System Verilog and UVM. Proficient in System C, C/C++, Python/perl. Experience developing and establishing DV Methodologies. Ability to develop System Verilog Testbench with UVM methodology from scratch. Experience with constraint random testing, SVA, Coverage driven verification. Test planning and problem‑solving skills. Preferred Qualifications Master of Science degree in Electrical Engineering/Computer Science. Experience in C/C++ modeling for design verification. Knowledge of 4G/5G cellular physical layer operation (3GPP). Experience with verification of embedded processor cores. Hands‑on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $139,500 and $258,100, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. #J-18808-Ljbffr

Join Apple's Wireless Connectivity team developing state-of-the-art WiFi SoCs that power hundreds of millions of Apple products worldwide. You'll be part of our vertically integrated organization shaping next-gen wireless technology from concept through production. As a Wireless PHY Design Verification Engineer, you'll ensure first-time-right silicon success through sophisticated testbenches, comprehensive scenarios, and cutting-edge verification methodologies-enabling multi-gigabit wireless technology connecting the world! Description As a Wireless PHY Design Verification Engineer, you'll verify sophisticated WiFi PHY digital systems spanning time/frequency-domain processing, hardware acceleration, calibration engines, and protocol implementation. You'll architect verification strategies for high-rate, low-power, low-latency, and multi-link wireless features enabling advanced applications across Apple's product ecosystem. You'll own subsystem verification from test planning through coverage closure-building environments, constrained random scenarios, and applying analytics methodologies to deliver exceptional wireless silicon. Responsibilities Develop sophisticated UVM environments and bus functional models for complex DSP subsystems and IEEE 802.11 protocol. Own subsystem verification from test planning and environment bring-up through feature closure. Develop UVM testbench environments, bus functional models (BFMs), assertions, and infrastructure / DPIs to utilizing algorithm models. Architect and implement constrained random scenarios exercising complex protocol interactions. Apply data-driven verification closure through coverage tracking, issue tracking, gap identification, and metrics. Drive verification strategy with cross-functional Systems / Design teams to achieve coverage closure across complex domains. Minimum Qualifications BS and a minimum of 3 years of relevant industry experience. Track record of several tapeout cycles of sophisticated designs. Experience verifying wireless, DSP, or digital communication systems. Knowledge of ASIC verification flows with SystemVerilog / UVM including testbench architecture, scenario creation, and coverage-driven methodologies. Experience developing verification environments, bringing up complex designs, and debugging simulations. Experience with constrained random testing, functional coverage implementation, and assertion-based verification. Preferred Qualifications Knowledge of IEEE 802.11 wireless protocols, Bluetooth, Cellular, or similar communication systems. Experience with applying / integrating System models utilizing DPIs. Understanding of DSP algorithms verification strategies (Bit / Cycle matching, Assertions). Experience with transaction-level modeling including packet-based approaches (scoreboarding, protocols). At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $139,500 and $258,100, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr

Join Apple's Wireless Connectivity team developing state-of-the-art WiFi SoCs that power hundreds of millions of Apple products worldwide. You'll be part of our vertically integrated organization shaping next-gen wireless technology from concept through production. As a Wireless Design Verification Engineer, you'll ensure first-time-right silicon success through sophisticated testbenches, comprehensive scenarios, and cutting-edge verification methodologies-enabling multi-gigabit wireless technology connecting the world! Description As a Wireless Verification Engineer, you will be at the core of our wireless product's success, bridging domains, driving collaborations, and developing verification solutions to ensure excellent products. In this role you will take on verification of controllers, datapaths, subsystems, protocols, low power capabilities, and SOC / integration frameworks. You will leverage and develop environments, create scenarios, and analyze metrics. You'll develop verification strategies for wireless features enabling advanced applications across Apple's product ecosystem. Responsibilities Own verification from test planning, environment bring-up, through feature closure. Develop comprehensive UVM testbench environments and BFMs spanning block to system levels. Implement constrained random scenarios exercising complex protocol, control, and datapath functionality. Drive closure by tracking regression metrics, resolving issues, and addressing coverage gaps. Partner with cross-functional Systems and Design teams to define verification strategy. Enhance simulation infrastructure automations. Minimum Qualifications BS and a minimum of 3 years of relevant industry experience. Experience with ASIC verification or complex digital IP development. Experience developing testbench environments, components, scenarios and bringing up designs in simulation. Understanding of constrained random testing, functional coverage analysis, and RTL simulation workflows. Strong problem-solving abilities and collaborative approach to engineering challenges. Preferred Qualifications Experience with bus functional models / transaction-modeling, and separately assertions. Exposure to system-level modeling or DPI-based verification approaches. Proficiency with Python, Perl, or Bash scripting for automation. Experience with Power-Aware / UPF simulations. Great teammate with excellent communication skills and desire to seek diverse technical challenges. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $139,500 and $258,100, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering Qualcomm is a global leader in wireless technology, driving innovation and shaping the future of connectivity. We are looking for talented and motivated individuals to join our team in San Diego, to contribute to cutting-edge projects and help us continue to lead the industry. Role Overview: As a CAD Engineer specializing in design verification DV, you will play a crucial role in (1) developing automation tools and flows for DV, (2) enable state of the art EDA tools for Qualcomm DV teams, (3) explore and apply the latest ML/AI technologies to improve DV workflow. You will also be responsible for creating comprehensive documentation, providing support to internal teams, and ensuring the efficiency and reliability of our automation processes. Key Responsibilities: Apply engineering principles to develop and optimize CAD tools and flows to enhance productivity, efficiency, and results. Conduct research to stay updated with the latest industry trends including ML/AI technologies and incorporate new learnings into Qualcomm workflow. Provide technical support and training to internal teams on CAD automation tools and workflows. Collaborate with cross-functional teams to identify and implement improvements in automation processes. Propose and execute innovative solutions to complex problems, contributing to the continuous improvement of our CAD automation capabilities. Personal Character Traits: Analytical: You possess strong analytical skills, enabling you to understand complex systems and identify areas for improvement. Resourceful: You are adept at finding creative solutions to challenges and are not afraid to think outside the box. Self-Motivated Learner: You are proactive in acquiring new knowledge and skills through self-guided research, training, and asking insightful questions. Problem Solver: Over time, you develop the ability to tackle higher-level problems, propose effective solutions, and execute decisions independently. Collaborative: You work well with others, sharing knowledge and supporting team members to achieve common goals. Qualifications for this Role: Bachelor's degree in computer science or electrical engineering 2+ years of ASIC design, verification, validation, or related work experience Strong programming skills in languages such as Python, TCL, GNU Make and Perl Experience with DV EDA tools such as VCS, Xcelium and Questa Preferred Qualifications: Master's degree or PhD in Computer Science or Electrical Engineering 5+ years of ASIC design, verification, CAD or related work experience Familiar with ML/AI techniques Experience in developing VLSI automation flows Knowledge of Hardware Description Languages like SystemVerilog Plus: Data science, ML/AI, VLSI CAD experience Minimum Qualifications: • Bachelor\'s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR • Master\'s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR • PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. EEO/Accessibility: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application hiring process, Qualcomm is committed to providing an accessible process. You may e-mail disability-accommodations at qualcomm dot com to request accommodations. Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00 The pay range reflects the broad minimum to maximum for this job code and location. Salary is one component of total compensation, which also includes a discretionary annual bonus program and possible RSU grants. Qualcomm offers a competitive benefits package to support you at work, at home, and at play. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc.Job Area: Engineering Group, Engineering Group > ASICS Engineering As a leading technology innovator, Qualcomm pushes the boundaries to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, validate digital/analog designs and develop a comprehensive validation/verification testbench environment for projects that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions that meet performance, security, technology, and feature requirements. As a Design Verification Engineer, you will work with Chip Architects to validate the concepts of core and sub-system level micro-architectures. You will work on a selected part of the subsystem Design Verification to ensure that it functions to the standards of being launch ready for the end Product. Role and Responsibilities Work with subsystem and SOC Architects to understand the concepts and high-level system requirements. Develop detailed Test and Coverage plans based on the Architecture and Micro-architecture. Develop Verification Methodology, ensuring scalability and portability across environments. Develop Verification environment, including all the respective components such as Stimulus, Checkers, Monitors Assertions, and Coverpoints. Develop Verification Plans and Testbenches for your functional domain. Execute Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures. Track and report DV progress using a variety of metrics, including Bugs and Coverage. Preferred Qualifications Deep knowledge of APB/AXI/SPI protocols, handshake mechanisms, cross-clock domains and clock gating. Solid understanding of memory organization, fault-tolerant design, parity schemes, error detection and error correction schemes. Advanced techniques such as: Formal, Assertions, and Silicon bring-up, is helpful. In-depth knowledge of Micro-processor functions, Network-on-Chip Architectures, and Micro-architectures. Experience in writing Testplans, portable Testbenches, Transactors, and Assembly code. Experience with different Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Mixed signal Verification. Ability to develop and work independently on a Block/Unit of the design. Qualifications Minimum Experience Level should be 2+ years in SOC-level or core-level verification with good understanding of debugging either ARM-based or RISC-V based processors, good understanding of APB/AHB/AXI protocols. Must have solid understanding of SV/UVM concepts. Prior experience in any cryptographic algorithm is preferred. Must have basic understanding of UNIX commands and Python/Perl scripting Minimum Qualifications • Bachelor\'s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master\'s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm\'s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm, which also includes a discretionary bonus program and potential RSU grants. Our benefits package supports success at work, at home, and at play. Your recruiter can discuss details, and you can review more about US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

A leading technology company in San Diego is seeking a Wireless Design Verification Engineer to join their team. This role focuses on pre-silicon RTL verification, collaborating with cross-functional teams to ensure high-quality design. The ideal candidate has a BS degree and at least 3 years of experience in verification, with a strong knowledge of Verilog and UVM. The position offers a competitive salary and comprehensive benefits package including stock options and tuition reimbursement. #J-18808-Ljbffr

San Francisco Bay Area, California, United States Hardware At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple's customers daily.This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out. Description In this role, you will be responsible for ensuring bug‑free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro‑architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable. Furthermore, you will develop verification plans for all features under your care, execute verification plans, including design bring‑up, DV environment bring‑up, regression enabling features, and debug of the test failures. You will also learn to develop block, IP and SoC level test‑benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality. Responsibilities Study design specification and create test plan Develop infrastructure in SystemVerilog/UVM to stress the design Develop and fix failures from regressions, close bugs Use LLMs to do verification efficiently Minimum Qualifications BS degree in technical subject area and a minimum 10 years relevant industry experience. Preferred Qualifications Deep knowledge of OOP, SystemVerilog and UVM Deep knowledge in developing scalable and portable test‑benches Strong experience with verification methodologies and tools such as simulators, waveform viewers, Build and run automation, coverage collection, gate level simulations Working experience using LLMs for efficiency and quality #J-18808-Ljbffr

A leading technology company in San Francisco is seeking a highly skilled design verification engineer to ensure bug-free first silicon for new products. The role involves developing methodologies for verification, creating test plans, and utilizing advanced tools and techniques, including LLMs, to enhance efficiency and quality. The ideal candidate will have a BS degree and at least 10 years of relevant experience in the field. #J-18808-Ljbffr

corporate_fare Google place Sunnyvale, CA, USA Apply Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with design verification. Experience with SystemVerilog/Verilog. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 6 years of experience with silicon design verification. Experience contributing across the entire design and verification life cycle. Experience optimizing tools, flows, and methodologies to improve efficiency. Experience with scripting languages (e.g., Python or Perl). Excellent problem solving and communication skills. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As an ASIC Design Verification Engineer, you will use design and verification expertise to verify complex digital designs. You will collaborate closely with design and verification engineers in active projects and perform direct verification. Using SystemVerilog coding and problem solving skills, you will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will be responsible for the full lifecycle of verification, from verification planning to test execution, to collecting and closing coverage. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out. Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr

A leading technology company is seeking a skilled Design Verification Engineer to focus on functional and performance verification of GPU designs in San Jose, California. This role involves developing verification plans, maintaining UVM-based environments, and collaborating with multiple teams to ensure adherence to specifications. The ideal candidate should have a Bachelor's degree and significant experience in ASIC/SoC/GPU/CPU development, particularly in verification processes. It is a 6-month onsite contract position. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD/Xilinx programmable devices. THE PERSON: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware and firmware engineers to understand the new features to be verified Take ownership of block level verification tasks Define test plans, test benches, and tests using System Verilog and UVM Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes Review functional and code coverage metrics to meet the coverage requirements Develop and improve existing verification flows and environments PREFERRED EXPERIENCE: Strong understanding of computer architecture and logic design Knowledge of Verilog, system Verilog and UVM is a must Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification Working knowledge of C/C++ and Assembly programming languages Exposure to scripting (python preferred) for post-processing and automation Experience with gate level simulation, power and reset verification ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading technology company is seeking recent graduates for an ASIC engineering role in San Francisco. You'll be part of a dynamic team, collaborating with experts in the field to develop innovative communications and network processing solutions. Candidates should have a Bachelor's degree or be nearing completion, familiar with hardware description languages, and understand ASIC design flow. Join a company that is shaping the future of technology. #J-18808-Ljbffr

Technical Lead Design Verification Engineer San Jose, CA Astera Labs (NASDAQ: ALAB)provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ****************** . We are looking fora Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You'll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms. Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Masters is preferred. ≥5 years' experience verifying and validating complex SoC for Server, Storage, and Networking applications. Knowledge of industry-standard simulators, revision control systems, and regression systems. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision. Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! Authorized to work in the US and start immediately. Required Experience Experience with full verification lifecycle based on System Verilog/UVM/C/C++. Proven ability to mix and deploy hybrid techniques as in both directed and constrained random. Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus. Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures. Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out. Preferred Experience Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc. Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Experience with directed test based methodologies, cache verification and formal methods. The base salary range is USD 147,000.00 - USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. Apply for this job * indicates a required field First Name * Last Name * Preferred First Name Email * Phone Resume/CV Enter manually Accepted file types: pdf, doc, docx, txt, rtf Enter manually Accepted file types: pdf, doc, docx, txt, rtf LinkedIn Profile Website How many years of full-time experience do you have relevant to the role? Select... Are you open to relocation and if so, to what location(s)? * I have reviewed and consented to the privacy policies. Select... #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate\'s responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred. The Person High energy candidates with strong written and verbal communication skills, and structured, well-organized work habits will be successful. Team and goal oriented are essential. Key Responsibilities Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency. Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA checks. Collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows. Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts) Preferred Experience Worked with EDA tools that enable RTL quality checks Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Ability to multitask, grasp new flows/tools/ideas. Experience in improving the methodologies. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT) Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters Strong analytical and problem-solving skills Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering Location: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

About the Team OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We're looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems-ranging from individual IP blocks to subsystems and full SoC-working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. Key Responsibilities Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. Define verification plans based on architecture and microarchitecture specs. Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. Drive bug triage, root cause analysis, and work closely with design teams on resolution. Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments. Qualifications BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification. Proven success verifying complex IP or SoC designs in industry-standard flows Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi). Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives. Familiarity with performance modeling, formal verification, or emulation is a plus. Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware. To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations. About OpenAI OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity. We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic. For additional information, please see OpenAI's Affirmative Action and Equal Employment Opportunity Policy Statement. Qualified applicants with arrest or conviction records will be considered for employment in accordance with applicable law, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations. To notify OpenAI that you believe this job posting is non-compliant, please submit a report through this form. No response will be provided to inquiries unrelated to job posting compliance. We are committed to providing reasonable accommodations to applicants with disabilities, and requests can be made via this link. OpenAI Global Applicant Privacy Policy At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology. #J-18808-Ljbffr