Design Verification Engineer jobs at Astera Labs

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Job Summary: We are seeking a highly motivated and detail-oriented Analog Mixed-Signal CAD Engineer to join our design automation team. In this role, you will develop, maintain, and support CAD tools and design flows for analog and mixed-signal IC design. You will work closely with circuit designers, layout engineers, and EDA vendors to ensure efficient and robust design environments. Key Responsibilities: Develop and maintain analog/mixed-signal design flows using industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.). Automate design tasks using scripting languages (e.g., Python, SKILL, Tcl, Perl). Support schematic, layout, simulation, and verification environments. Collaborate with design teams to understand requirements and improve design productivity. Integrate and validate PDKs (Process Design Kits) and technology files. Provide documentation, training, and support for CAD tools and flows. Interface with EDA vendors to evaluate and deploy new tools and features. Monitor and resolve CAD tool issues, ensuring high availability and performance. Required Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 3+ years of experience in analog/mixed-signal CAD or EDA tool development. Strong knowledge of analog/mixed-signal IC design methodologies. Proficiency in scripting languages such as SKILL, Python, Tcl, or Perl. Experience with Cadence Virtuoso, Spectre, and AMS simulation environments. Familiarity with PDK integration and technology file management. Excellent problem-solving, communication, and teamwork skills. Preferred Qualifications: Experience with digital-on-top (DoT) or mixed-signal verification flows. Knowledge of version control systems (e.g., Git, Perforce). Familiarity with Unix/Linux environments and shell scripting. Exposure to advanced process nodes (e.g., 7nm, 5nm). We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Job DescriptionWe're hiring experienced Design Verification Engineers to play a key role in developing and verifying the designs that will bring our next-generation AI processors to life. About Us:Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from -40 °ree;C to +125 °ree;C, making it ideal for industrial, automotive, aerospace, and defense. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. The salary range for this position is $120,000-$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location. Design Verification at Mythic:At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. DV engineers collaborate closely with RTL design, architecture modeling, custom analog IP, compiler, emulation, and post-silicon teams to ensure the full system operates as intended. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We welcome engineers at all levels of experience who are eager to tackle challenging verification problems and contribute to the success of our breakthrough AI hardware.Responsibilities Hands-on system-level and block-level verification. Development of test plans and coverage plans. Testbench development and execution using UVM or other advanced DV methodologies. Creation of verification infrastructure and flows. Leverage architecture models and emulation environments to help verify large AI network functionality on the design. Collaborate with RTL designers and architects to verify subsystems such as scheduling fabrics, interconnects, DMA engines, and memory controllers. Requirements Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science. 8+ years of industry experience developing verification testbenches. Knowledge of verification methodologies (UVM or similar). Solid understanding of computer architecture, including datapaths, memory hierarchies, and interconnects. Experience verifying one or more of the following: scheduling subsystems, high-performance interconnects, DMA engines, or memory subsystems. Understanding of Verilog, SystemVerilog, and UVM. Proven track record of first-pass silicon success. Strong communication skills, both written and spoken. Preferred Qualifications Experience with emulation or FPGA prototyping for large-scale designs. Knowledge of coverage-driven verification and advanced stimulus generation techniques. Exposure to formal verification methods and tools. Familiarity with power-aware and performance-driven verification flows. Prior experience verifying AI, DSP, or other highly parallel architectures. Strong scripting skills (Python or similar) for automation and infrastructure development. At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to life. About Us:Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from -40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. The salary range for this position is $120,000-$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location. Design Verification at Mythic:At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our custom dataflow architecture that is the backbone of our chip design. DV engineers collaborate with many teams, including RTL design, architecture modeling, custom analog IP, compiler, emulation and post-silicon to ensure the full system operates as intended. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We welcome engineers at all levels of experience who are eager to tackle challenging verification problems and contribute to the success of our breakthrough AI hardware.Responsibilities Hands on system-level and block-level verification. Development of test plans and coverage plans. Testbench development and execution using UVM or other advanced DV methodologies. Creation of verification infrastructure and flows. Leverage architecture models and emulation environments to help verify large AI network functionality on the design. Further responsibilities will depend on background and skills. Requirements Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science. 3+ years of industry experience developing verification testbenches. Knowledge of verification methodologies. Knowledge of computer architecture. Understanding of Verilog, SystemVerilog, and UVM. Proven track record of first-pass silicon success. Strong communication skills, both written and spoken. At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.

We're hiring experienced Design Verification Engineers to play a key role in developing and verifying the designs that will bring our next-generation AI processors to life. About Us:Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from -40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. The salary range for this position is $120,000-$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location. Design Verification at Mythic:At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. DV engineers collaborate closely with RTL design, architecture modeling, custom analog IP, compiler, emulation, and post-silicon teams to ensure the full system operates as intended. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We welcome engineers at all levels of experience who are eager to tackle challenging verification problems and contribute to the success of our breakthrough AI hardware.Responsibilities Hands-on system-level and block-level verification. Development of test plans and coverage plans. Testbench development and execution using UVM or other advanced DV methodologies. Creation of verification infrastructure and flows. Leverage architecture models and emulation environments to help verify large AI network functionality on the design. Collaborate with RTL designers and architects to verify subsystems such as scheduling fabrics, interconnects, DMA engines, and memory controllers. Requirements Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science. 8+ years of industry experience developing verification testbenches. Knowledge of verification methodologies (UVM or similar). Solid understanding of computer architecture, including datapaths, memory hierarchies, and interconnects. Experience verifying one or more of the following: scheduling subsystems, high-performance interconnects, DMA engines, or memory subsystems. Understanding of Verilog, SystemVerilog, and UVM. Proven track record of first-pass silicon success. Strong communication skills, both written and spoken. Preferred Qualifications Experience with emulation or FPGA prototyping for large-scale designs. Knowledge of coverage-driven verification and advanced stimulus generation techniques. Exposure to formal verification methods and tools. Familiarity with power-aware and performance-driven verification flows. Prior experience verifying AI, DSP, or other highly parallel architectures. Strong scripting skills (Python or similar) for automation and infrastructure development. At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.

Job DescriptionWe're hiring experienced Design Verification Engineers to play a key role in developing and verifying the designs that will bring our next-generation AI processors to life. About Us:Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from -40 °ree;C to +125 °ree;C, making it ideal for industrial, automotive, aerospace, and defense. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. The salary range for this position is $120,000-$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location. Design Verification at Mythic:At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. DV engineers collaborate closely with RTL design, architecture modeling, custom analog IP, compiler, emulation, and post-silicon teams to ensure the full system operates as intended. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We welcome engineers at all levels of experience who are eager to tackle challenging verification problems and contribute to the success of our breakthrough AI hardware.Responsibilities Hands-on system-level and block-level verification. Development of test plans and coverage plans. Testbench development and execution using UVM or other advanced DV methodologies. Creation of verification infrastructure and flows. Leverage architecture models and emulation environments to help verify large AI network functionality on the design. Collaborate with RTL designers and architects to verify subsystems such as scheduling fabrics, interconnects, DMA engines, and memory controllers. Requirements Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science. 8+ years of industry experience developing verification testbenches. Knowledge of verification methodologies (UVM or similar). Solid understanding of computer architecture, including datapaths, memory hierarchies, and interconnects. Experience verifying one or more of the following: scheduling subsystems, high-performance interconnects, DMA engines, or memory subsystems. Understanding of Verilog, SystemVerilog, and UVM. Proven track record of first-pass silicon success. Strong communication skills, both written and spoken. Preferred Qualifications Experience with emulation or FPGA prototyping for large-scale designs. Knowledge of coverage-driven verification and advanced stimulus generation techniques. Exposure to formal verification methods and tools. Familiarity with power-aware and performance-driven verification flows. Prior experience verifying AI, DSP, or other highly parallel architectures. Strong scripting skills (Python or similar) for automation and infrastructure development. At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.

We're hiring experienced Design Verification Engineers to play a key role in developing and verifying the designs that will bring our next-generation AI processors to life. About Us:Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from -40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. The salary range for this position is $120,000-$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location. Design Verification at Mythic:At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. DV engineers collaborate closely with RTL design, architecture modeling, custom analog IP, compiler, emulation, and post-silicon teams to ensure the full system operates as intended. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We welcome engineers at all levels of experience who are eager to tackle challenging verification problems and contribute to the success of our breakthrough AI hardware.Responsibilities Hands-on system-level and block-level verification. Development of test plans and coverage plans. Testbench development and execution using UVM or other advanced DV methodologies. Creation of verification infrastructure and flows. Leverage architecture models and emulation environments to help verify large AI network functionality on the design. Collaborate with RTL designers and architects to verify subsystems such as scheduling fabrics, interconnects, DMA engines, and memory controllers. Requirements Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science. 8+ years of industry experience developing verification testbenches. Knowledge of verification methodologies (UVM or similar). Solid understanding of computer architecture, including datapaths, memory hierarchies, and interconnects. Experience verifying one or more of the following: scheduling subsystems, high-performance interconnects, DMA engines, or memory subsystems. Understanding of Verilog, SystemVerilog, and UVM. Proven track record of first-pass silicon success. Strong communication skills, both written and spoken. Preferred Qualifications Experience with emulation or FPGA prototyping for large-scale designs. Knowledge of coverage-driven verification and advanced stimulus generation techniques. Exposure to formal verification methods and tools. Familiarity with power-aware and performance-driven verification flows. Prior experience verifying AI, DSP, or other highly parallel architectures. Strong scripting skills (Python or similar) for automation and infrastructure development. At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to life. About Us:Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from -40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. The salary range for this position is $120,000-$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location. Design Verification at Mythic:At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our custom dataflow architecture that is the backbone of our chip design. DV engineers collaborate with many teams, including RTL design, architecture modeling, custom analog IP, compiler, emulation and post-silicon to ensure the full system operates as intended. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We welcome engineers at all levels of experience who are eager to tackle challenging verification problems and contribute to the success of our breakthrough AI hardware.Responsibilities Hands on system-level and block-level verification. Development of test plans and coverage plans. Testbench development and execution using UVM or other advanced DV methodologies. Creation of verification infrastructure and flows. Leverage architecture models and emulation environments to help verify large AI network functionality on the design. Further responsibilities will depend on background and skills. Requirements Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science. 3+ years of industry experience developing verification testbenches. Knowledge of verification methodologies. Knowledge of computer architecture. Understanding of Verilog, SystemVerilog, and UVM. Proven track record of first-pass silicon success. Strong communication skills, both written and spoken. At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include global corporations across multiple industries, national labs, and top-tier healthcare systems. In January, we announced a multi-year, multi-million-dollar partnership with Mayo Clinic, underscoring our commitment to transforming AI applications across various fields. In August, we launched Cerebras Inference, the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. Key Responsibilities Work with architects, designers, post-silicon, and software engineers, to ensure a high-quality design that works for silicon. Develop and implement verification strategies, detailed tests, and coverage plans based on micro-architecture. Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage. Implement tests, manage regressions, gather coverage, and debug test failures. Collaborate with cross-functional teams, including architecture, RTL design, physical design, firmware, and validation. Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases. Continuously enhances verification infrastructure and flows to improve efficiency and quality. Contribute to the evolution of the overall verification methodology and best practices across the organization. Skills and Qualifications Advanced debugging and problem-solving skills. Deep knowledge of SystemVerilog testbench, DPI, and UVM. Excellent programming skills and knowledge of software engineering practices, including object-oriented design. Experience developing scalable and portable testbenches and components. Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulations. Proficient in scripting languages such as Python or Perl. Good interpersonal skills and the ability to work as a standout colleague are a must. Extremely self-motivated and eager to solve problems 3+ years of Design Verification experience. Desired Skills and Qualifications Knowledge of pipelined processor architecture. BS or MS in Computer Science or Electrical Engineering. 3+ years of hands-on Design Verification experience. The base salary range for this position is $120,000 to $240,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications. We are open to remote candidates. Why Join Cerebras People who are serious about software make their own hardware. At Cerebras we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we've reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras: Build a breakthrough AI platform beyond the constraints of the GPU. Publish and open source their cutting-edge AI research. Work on one of the fastest AI supercomputers in the world. Enjoy job stability with startup vitality. Our simple, non-corporate work culture that respects individual beliefs. Read our blog: Five Reasons to Join Cerebras in 2025. Apply today and become part of the forefront of groundbreaking advancements in AI! Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them. This website or its third-party tools process personal data. For more details, click here to review our CCPA disclosure notice.

Key Responsibilities * Work with architects, designers, post-silicon, and software engineers, to ensure a high-quality design that works for silicon. * Develop and implement verification strategies, detailed tests, and coverage plans based on micro-architecture. * Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage. * Implement tests, manage regressions, gather coverage, and debug test failures. * Collaborate with cross-functional teams, including architecture, RTL design, physical design, firmware, and validation. * Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases. * Continuously enhances verification infrastructure and flows to improve efficiency and quality. * Contribute to the evolution of the overall verification methodology and best practices across the organization. Skills and Qualifications * Advanced debugging and problem-solving skills. * Deep knowledge of SystemVerilog testbench, DPI, and UVM. * Excellent programming skills and knowledge of software engineering practices, including object-oriented design. * Experience developing scalable and portable testbenches and components. * Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulations. * Proficient in scripting languages such as Python or Perl. * Good interpersonal skills and the ability to work as a standout colleague are a must. * Extremely self-motivated and eager to solve problems * 3+ years of Design Verification experience. Desired Skills and Qualifications * Knowledge of pipelined processor architecture. * BS or MS in Computer Science or Electrical Engineering. * 3+ years of hands-on Design Verification experience. The base salary range for this position is $120,000 to $240,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications. We are open to remote candidates.

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Job Responsibilities and Description: The Physical Design and Verification Engineer will be responsible for RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification. Required Qualifications: Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience. Minimum 5 years of experience in digital physical design and verification. Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff. Deep knowledge on industry standards and practices in physical design including physically-aware synthesis flow, floor-planning, and place & route, metal fill, chip finishing, signal integrity checks, and dynamic EMIR-Drop analysis, and formal ESD verification. Experience in Signoff ECO flow to fix timing, noise, IR-Drop and EMIR violations. Experience in physical design verification to debug LVS/DRC/PERC issues at the chip/block level using industry standard tools. Experience in developing automation flow and scripts using Python, Perl, Makefile, Tcl and UNIX shell. Preferred Qualifications: Master of Science (M.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience. Experience working on physical design and implementation of complex ASIC systems at advanced technology nodes, preferably 16nm and below. Experience in DFT (Design For Test) flows and ATPG. Experience in I/O design flow in multi-voltage power domain. Experience in building chip floor-plan including pin placement, partitions and power grid. Experience in hierarchical synthesis, place-and-route and design closure to meet timing, area, and UPF-driven low power constraints. Experience with build tools such as CMake and Bazel. Experience with code coverage and regression setup. Expected Compensation: The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees' success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees. Base Salary Range: $158,000 - $243,000 USD What We Offer: Full-time employees are eligible for the following benefits listed below. An opportunity to change the world and work with some of the smartest and most talented experts from different fields Growth potential; we rapidly advance team members who have an outsized impact Excellent medical, dental, and vision insurance through a PPO plan Paid holidays Commuter benefits Meals provided Equity (RSUs) *Temporary Employees & Interns excluded 401(k) plan *Interns initially excluded until they work 1,000 hours Parental leave *Temporary Employees & Interns excluded Flexible time off *Temporary Employees & Interns excluded

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Job Responsibilities and Description: The Physical Design and Verification Engineer will be responsible for RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification. Required Qualifications: Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience. Minimum 5 years of experience in digital physical design and verification. Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff. Deep knowledge on industry standards and practices in physical design including physically-aware synthesis flow, floor-planning, and place & route, metal fill, chip finishing, signal integrity checks, and dynamic EMIR-Drop analysis, and formal ESD verification. Experience in Signoff ECO flow to fix timing, noise, IR-Drop and EMIR violations. Experience in physical design verification to debug LVS/DRC/PERC issues at the chip/block level using industry standard tools. Experience in developing automation flow and scripts using Python, Perl, Makefile, Tcl and UNIX shell. Preferred Qualifications: Master of Science (M.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience. Experience working on physical design and implementation of complex ASIC systems at advanced technology nodes, preferably 16nm and below. Experience in DFT (Design For Test) flows and ATPG. Experience in I/O design flow in multi-voltage power domain. Experience in building chip floor-plan including pin placement, partitions and power grid. Experience in hierarchical synthesis, place-and-route and design closure to meet timing, area, and UPF-driven low power constraints. Experience with build tools such as CMake and Bazel. Experience with code coverage and regression setup. Expected Compensation: The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees' success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees. Base Salary Range:$158,000-$243,000 USD What We Offer: Full-time employees are eligible for the following benefits listed below. An opportunity to change the world and work with some of the smartest and most talented experts from different fields Growth potential; we rapidly advance team members who have an outsized impact Excellent medical, dental, and vision insurance through a PPO plan Paid holidays Commuter benefits Meals provided Equity (RSUs) *Temporary Employees & Interns excluded 401(k) plan *Interns initially excluded until they work 1,000 hours Parental leave *Temporary Employees & Interns excluded Flexible time off *Temporary Employees & Interns excluded

Insilico is an End-to-End specialized VLSI, Embedded Design & Software services and solutions company. It operates in the “Compute” & “Connectivity” space. Insilico is founded by industry veterans, who are strong leaders and practitioners with diverse experience in all the relevant aspects of technology and execution. The management and its entire team, handpicked from among the best talents in the industry, can adapt to the evolving technologies and growing market challenges internationally. Insilico has very flexible business models to suit a plethora of client needs. With a current clientele of top semiconductor companies, Insilico has a wide and diversified spectrum of service offerings in expansive domains within the ambit of Embedded Design & Software, and in almost all areas of VLSI design, from Spec-to-Silicon, on a wide range of ASICs & CPUs/GPUs in all the latest technologies, including 7nm. Being an integral part of a larger business eco-system, Insilico has the foundation of strong financials, validated processes, robust infrastructure and a global network of reputable clientele. Insilico's service portfolio caters to products that empower the world of Communication, Networking, CPU/Servers, Automobile, Bio-Medicals, Consumer Electronics and a wide range of IOTs. Headquartered in the US, it has operations in India & APAC. Job Title: Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Job Description: Senior DV engineer responsible for defining and implementing verification methodology and verifying in any of the following key areas of our next generation ASIC: 1. PCIE verification background 2. 400G MAC verification background Additional Information All your information will be kept confidential according to EEO guidelines.

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Responsible for digital ASIC verification at block and system level Write and review test plans, develop test harnesses and test sequences Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks Responsible for test plan execution, running regressions, code and functional coverage closure Automate test case generation by using Python and MATLAB programs Contribute towards pre-silicon verification, chip bring-up and post-silicon validation Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs BASIC QUALIFICATIONS: Bachelor's degree in electrical engineering, computer science or computer engineering 2+ years of experience with design verification and test bench development PREFERRED SKILLS AND EXPERIENCE: Advanced degree in electrical engineering or computer engineering Experience with verification methodologies such as UVM Strong object-oriented programming knowledge Strong problem-solving and coding skills Experience in constrained random verification Expertise in developing test plans, implementing coverage models, and analyzing results Experience with scripting languages, e.g. Python for automation RTL design, chip bring-up, and post-silicon validation experience Ability to work in a dynamic environment with changing needs and requirements ADDITIONAL REQUIREMENTS: Must be willing to work extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Design Verification Engineer/Level I: $120,000.00 - $145,000.00/per year Design Verification Engineer/Level II: $140,000.00 - $170,000.00/per year Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year. ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here. SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to ************************ .

Insilico is an End-to-End specialized VLSI, Embedded Design & Software services and solutions company. It operates in the “Compute” & “Connectivity” space. Insilico is founded by industry veterans, who are strong leaders and practitioners with diverse experience in all the relevant aspects of technology and execution. The management and its entire team, handpicked from among the best talents in the industry, can adapt to the evolving technologies and growing market challenges internationally. Insilico has very flexible business models to suit a plethora of client needs. With a current clientele of top semiconductor companies, Insilico has a wide and diversified spectrum of service offerings in expansive domains within the ambit of Embedded Design & Software, and in almost all areas of VLSI design, from Spec-to-Silicon, on a wide range of ASICs & CPUs/GPUs in all the latest technologies, including 7nm. Being an integral part of a larger business eco-system, Insilico has the foundation of strong financials, validated processes, robust infrastructure and a global network of reputable clientele. Insilico's service portfolio caters to products that empower the world of Communication, Networking, CPU/Servers, Automobile, Bio-Medicals, Consumer Electronics and a wide range of IOTs. Headquartered in the US, it has operations in India & APAC. Job Title: Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Job Description: Senior DV engineer responsible for defining and implementing verification methodology and verifying in any of the following key areas of our next generation ASIC: 1. PCIE verification background 2. 400G MAC verification background Additional Information All your information will be kept confidential according to EEO guidelines.

About the Team: OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We're looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems-ranging from individual IP blocks to subsystems and full SoC-working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. Key Responsibilities Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. Define verification plans based on architecture and microarchitecture specs. Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. Drive bug triage, root cause analysis, and work closely with design teams on resolution. Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments. Qualifications BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification. Proven success verifying complex IP or SoC designs in industry-standard flows Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi). Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives. Familiarity with performance modeling, formal verification, or emulation is a plus. Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware. To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations. About OpenAI OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity. We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic. For additional information, please see OpenAI's Affirmative Action and Equal Employment Opportunity Policy Statement. Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations. To notify OpenAI that you believe this job posting is non-compliant, please submit a report through this form. No response will be provided to inquiries unrelated to job posting compliance. We are committed to providing reasonable accommodations to applicants with disabilities, and requests can be made via this link. OpenAI Global Applicant Privacy Policy At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.

This role is with RippleMatch's partner companies. RippleMatch partners with hundreds of companies looking to hire top talent. About RippleMatch RippleMatch is your AI-powered job matchmaker. Our platform brings opportunities directly to you by matching you with top employers and jobs you are qualified for. Tell us about your strengths and goals - we'll get you interviews! Leading employers leverage RippleMatch to build high-performing teams and Gen Z job seekers across the country trust RippleMatch to launch and grow their careers. Requirements for the role: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Hardware Engineering, or a related field. Internship or hands-on project experience in hardware design or a closely related field. Solid understanding of hardware design principles, including circuit design, PCB layout, and system integration. Proficiency with hardware development tools and software, such as Altium Designer, Eagle, or similar PCB design software. Experience in designing, prototyping, and testing electronic hardware components and systems. Strong analytical and problem-solving skills, with the ability to troubleshoot and optimize hardware designs. Proactive approach to learning new tools and techniques in hardware development. Good organizational and project management skills, capable of managing project timelines and contributing to multiple projects simultaneously. Effective communication and interpersonal skills, for collaborating with multidisciplinary teams and communicating technical information. Eagerness to stay updated with the latest advancements in hardware technologies and industry trends.

This role is with RippleMatch's partner companies. RippleMatch partners with hundreds of companies looking to hire top talent. About RippleMatch RippleMatch is your AI-powered job matchmaker. Our platform brings opportunities directly to you by matching you with top employers and jobs you are qualified for. Tell us about your strengths and goals - we'll get you interviews! Leading employers leverage RippleMatch to build high-performing teams and Gen Z job seekers across the country trust RippleMatch to launch and grow their careers. Requirements for the role: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Hardware Engineering, or a related field. Internship or hands-on project experience in hardware design or a closely related field. Solid understanding of hardware design principles, including circuit design, PCB layout, and system integration. Proficiency with hardware development tools and software, such as Altium Designer, Eagle, or similar PCB design software. Experience in designing, prototyping, and testing electronic hardware components and systems. Strong analytical and problem-solving skills, with the ability to troubleshoot and optimize hardware designs. Proactive approach to learning new tools and techniques in hardware development. Good organizational and project management skills, capable of managing project timelines and contributing to multiple projects simultaneously. Effective communication and interpersonal skills, for collaborating with multidisciplinary teams and communicating technical information. Eagerness to stay updated with the latest advancements in hardware technologies and industry trends.

This role is with RippleMatch's partner companies. RippleMatch partners with hundreds of companies looking to hire top talent. About RippleMatch RippleMatch is your AI-powered job matchmaker. Our platform brings opportunities directly to you by matching you with top employers and jobs you are qualified for. Tell us about your strengths and goals - we'll get you interviews! Leading employers leverage RippleMatch to build high-performing teams and Gen Z job seekers across the country trust RippleMatch to launch and grow their careers. Requirements for the role: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Hardware Engineering, or a related field. Internship or hands-on project experience in hardware design or a closely related field. Solid understanding of hardware design principles, including circuit design, PCB layout, and system integration. Proficiency with hardware development tools and software, such as Altium Designer, Eagle, or similar PCB design software. Experience in designing, prototyping, and testing electronic hardware components and systems. Strong analytical and problem-solving skills, with the ability to troubleshoot and optimize hardware designs. Proactive approach to learning new tools and techniques in hardware development. Good organizational and project management skills, capable of managing project timelines and contributing to multiple projects simultaneously. Effective communication and interpersonal skills, for collaborating with multidisciplinary teams and communicating technical information. Eagerness to stay updated with the latest advancements in hardware technologies and industry trends.

This role is with RippleMatch's partner companies. RippleMatch partners with hundreds of companies looking to hire top talent. About RippleMatch RippleMatch is your AI-powered job matchmaker. Our platform brings opportunities directly to you by matching you with top employers and jobs you are qualified for. Tell us about your strengths and goals - we'll get you interviews! Leading employers leverage RippleMatch to build high-performing teams and Gen Z job seekers across the country trust RippleMatch to launch and grow their careers. Requirements for the role: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Hardware Engineering, or a related field. Internship or hands-on project experience in hardware design or a closely related field. Solid understanding of hardware design principles, including circuit design, PCB layout, and system integration. Proficiency with hardware development tools and software, such as Altium Designer, Eagle, or similar PCB design software. Experience in designing, prototyping, and testing electronic hardware components and systems. Strong analytical and problem-solving skills, with the ability to troubleshoot and optimize hardware designs. Proactive approach to learning new tools and techniques in hardware development. Good organizational and project management skills, capable of managing project timelines and contributing to multiple projects simultaneously. Effective communication and interpersonal skills, for collaborating with multidisciplinary teams and communicating technical information. Eagerness to stay updated with the latest advancements in hardware technologies and industry trends.