Architect jobs at Broadcom - 87 jobs

**Please Note:** **1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)** **2. If you already have a Candidate Account, please Sign-In before you apply.** **:** The vKS Application Engineering team is responsible for enabling enterprise success with vSphere Kubernetes Service (vKS) as part of VMware Cloud Foundation (VCF). Our mission is to accelerate adoption of vKS as the enterprise-grade Kubernetes platform for modern applications in private cloud. As a vKS Application Engineer, you will be on the front lines with enterprise customers, driving the successful adoption of vSphere Kubernetes Service (vKS) on VMware Cloud Foundation (VCF). This is a hands-on, customer-facing role focused on designing and validating solutions, running proof-of-concepts, and guiding customers through their modernization journey. **Key Accountabilities** + Act as a trusted advisor for enterprise customers, guiding them through the design, validation, and deployment of vKS solutions on VCF. + Collaborate closely with field account teams to align solution architecture with customer priorities and drive successful engagement outcomes. + Lead technical discovery sessions, workshops, and proof-of-concepts to validate vKS architectures and demonstrate business value. + Partner with sales to jointly develop customer proposals that address modernization goals, workload placement, and operational transformation. + Provide prescriptive guidance on Kubernetes adoption, DevOps/CI-CD integration, and enterprise requirements such as scalability, security, and disaster recovery. + Build and share reference architectures, deployment patterns, and technical assets to accelerate customer adoption of vKS. + Deliver clear, compelling technical presentations to diverse audiences, from architects to executive decision makers. + Stay current on industry trends, competitor offerings, and evolving enterprise requirements to position vKS effectively. + Collaborate with product management and engineering to provide field feedback that influences roadmap direction. **Required Skills & Experience** + Experience in application engineering or technical sales for enterprise IT, cloud, or application platforms. + Strong expertise in Kubernetes, containers, and VMware Cloud Foundation (vSphere, vSAN, NSX as foundation). + 8-10+ years in technology-related roles, with depth in enterprise IT architecture, application modernization, or cloud-native platforms. + Demonstrated success working directly with enterprise customers to deliver technical solutions and drive platform adoption. + Excellent communication, storytelling, and presentation skills with the ability to engage both technical and business leaders. + Strong collaboration skills, able to work hand-in-hand with sales teams to advance customer opportunities. + Proven ability to identify challenges, design solutions, and articulate value in business terms. + Enthusiastic self-starter with curiosity, drive, and the ability to thrive in dynamic environments. + Ability to travel up to 50% of the time **Qualifications** + Bachelor's Degree or Master's Degree plus 12+/10+ in Computer Science, Engineering, Mathematics, or related field; or equivalent experience. + Deep knowledge of VMware Cloud Foundation and Kubernetes platforms. + Certifications in cloud-native or public cloud technologies (AWS, Azure, GCP, Red Hat OpenShift, etc.) are highly desirable. **Additional Job Description:** **Compensation and Benefits** The annual base salary range for this position is $118,800 - $171,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. **Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.** **If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.** Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library (******************************* and check out our Connected by Broadcom (************************************************************************************************************************************************* series. Follow us on Linked In Broadcom Inc (****************************************** .

Introduction A career in IBM Consulting is rooted by long-term relationships and close collaboration with clients across the globe. You'll work with visionaries across multiple industries to improve the hybrid cloud and AI journey for the most innovative and valuable companies in the world. Your ability to accelerate impact and make meaningful change for your clients is enabled by our strategic partner ecosystem and our robust technology platforms across the IBM portfolio Your role and responsibilities Support client engagements to provide subject matter expertise in Oracle Cloud Financials implementations. Assume accountability for the solution design and the successful implementation of the full solution for on Oracle Cloud ERP Projects. May include hands‑on development, design, prototyping and/or other efforts required to keep the project on a successful track. Ensure that the proposed solution meets the client's requirements, is architecturally complete, and all architectural risks are quantified within their assigned area. Required technical and professional expertise 10+ years ERP implementation experience Played a Senior Solution Architect role on a minimum of 2 full lifecycle Oracle Cloud implementation projects in the USA Public Sector domain (city/state/local/county government) experience considered an asset Knowledge and experience in GASB Accounting and Reporting, Encumbrance Accounting, Fund Accounting, Projects and Grants Accounting and Management IBM is committed to creating a diverse environment and is proud to be an equal‑opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, gender, gender identity or expression, sexual orientation, national origin, caste, genetics, pregnancy, disability, neurodivergence, age, veteran status, or other characteristics. IBM is also committed to compliance with all fair employment practices regarding citizenship and immigration status. #J-18808-Ljbffr

A global consulting firm is seeking a Senior Solution Architect specializing in Oracle Cloud Financials in San Francisco. The role requires over 10 years of ERP implementation experience with at least two full lifecycle Oracle Cloud projects. A background in the Public Sector and knowledge of GASB Accounting are advantageous. This position offers an opportunity to work with innovative companies and make a significant impact on their cloud journeys. #J-18808-Ljbffr

A leading technology company is seeking a Senior Principal Emulation Design Engineer in San Jose. This role focuses on developing verification environments and requires strong experience with system-level designs and communication standards. Ideal candidates will possess a relevant degree and extensive experience in design. The position offers a competitive salary range from $154,000 to $286,000 along with numerous benefits. #J-18808-Ljbffr

A leading semiconductor company in California is looking for a Senior Silicon Design Verification Engineer to innovate in the verification of high-speed Crypto and Network-on-Chip designs. You will lead a team, develop verification strategies, and collaborate with cross-functional engineering teams. The ideal candidate has a strong leadership background, is proficient in UVM and System Verilog, and has a passion for fostering a collaborative environment. The role requires a relevant degree and strong communication skills. Competitive benefits are included. #J-18808-Ljbffr

A leading electronic design automation company in San Jose is seeking a Sr Principal Design Engineer to lead high-performance memory IP architecture design. The position requires expertise in IC micro-architecture and a minimum of 8 years of experience in electrical engineering or related fields. A strong communication skill set is essential. The offered annual salary range is competitive, with comprehensive benefits including 401(k), paid vacation, and health plans. #J-18808-Ljbffr

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. HPC/ML GPU Performance Architect: AMD is looking for an outstanding technical contributor & lead to help optimize performance of AMD based next-generation GPU accelerators for HPC and Machine Learning. As a passionate and dedicated Server GPU Performance Architect in the MI SOC Architecture Team, you will optimize SOC performance by identifying opportunities across all parts of system architecture, spanning the application and related frameworks, driver, GPU core, memory & I/O subsystems. You will collect and analyze performance profiling data and traces to isolate performance bottlenecks, and share the insights to help drive features into the next generation of server GPUs and software stack components. The ideal candidate is expected to be well informed on latest trends in GPU accelerated HPC and ML, and be able to quickly ascertain, in a data-driven manner, how next generation server GPUs and platforms should be engineered to support those needs. Key Responsibilities: • Establishes and maintains AMD's technological leadership position • Considered technical leader across project and departmental boundaries and has a proven track record for sustained innovation. • Is responsible for projects or processes of significant strategic or commercial importance and for project/program results • Deals with problems requiring cutting edge approaches and champions innovation across the organization • Makes technical decisions that have a significant impact on product families, go to market strategies and customer satisfaction • Has business and technical time horizon of generally 6 to 36 months. • Accountability on project execution with significant influence on project/product time-tomarket schedules. • Provides consultative direction with senior management • Coaches and mentors experienced staff • Represents AMD to the outside technical community, partners and vendors • Work closely with other team members to understand design architecture and to propose solutions to improve/enhance performance with given SoC/IP and markets. • Architectural modeling, performance triage, deeper analysis, identifying bottlenecks working with architects and proposing solutions for performance improvement. • Developing tools and methodology for performance modeling, workloads analysis. • Proposing, communicating and implementing solutions to issues. • Lead technical teams, participate and present in executive reviews on product planning and execution. • Participate in collaborative development and workload performance optimization with AMD's partners/customers. Position Requirements: • Exceptional foundation in systems architecture, cutting across CPU or GPU, memory, storage and I/O subsystems • Power user of performance profiling tools • Experience with hardware performance counter monitoring tools • Knowledge of OS internals and kernel parameter tuning experience • Exposure to GPU accelerator performance benchmarks and codes are a plus (HPL, HPCG, STREAM, MLPerf, HACC, QMCPACK, LAMMPS, etc.) • Excellent communication skills (verbal, written, and presentation) • > 7 years relevant industry experience Education Requirements: Master's degree required, PhD preferred, emphasis in Electrical or Computer Engineering, Computer Architecture, or Computer Science with SoC/IP performance studies. AMD is a government contractor and subcontractor. As required by Executive Order, our US employees are required to be fully vaccinated against COVID-19 regardless of the employee's work location or work arrangement (e.g., telework, remote work, etc.), subject to such exceptions as required by law. If selected, you will be required to be vaccinated against COVID-19 and submit documentation of proof of vaccination by January 4, 2022 . AMD will provide additional information regarding what information or documentation will be needed and how you can request an exception from this requirement if you have a need for a religious and/or medical accommodation. Requisition Number: 124246 Country: United States State: Texas City: Austin Job Function: Design AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Senior Fellow will lead efforts in developing and optimizing adaptive and embedded hardware architectures. This role involves working on advanced elements such as pipelining, application mapping, customer commitments, technology evaluation, strategic pathfinding, government contracts, integration strategies, and FPGA prototyping algorithms. The position requires close collaboration with foundry teams, software teams, product planning teams, customers, and implementation groups to ensure successful project execution and alignment with strategic goals. RESPONSIBILITIES: * Design and optimize hardware architectures with a focus on adaptability and usability. * Develop pipelining strategies to enhance performance and efficiency. * Map applications effectively onto hardware platforms to establish capabilities against requirements. * Evaluate emerging technologies and conduct pathfinding to identify future opportunities. * Manage customer commitments and ensure alignment with project timelines and deliverables. * Collaborate with government entities to secure contracts and manage deliverables towards strategic research and development. * Develop integration strategies to seamlessly incorporate new technologies into existing systems. * Innovate and refine FPGA P&R algorithms to improve design and implementation processes. * Optimize product capabilities along with organization capabilities, schedule, cost, power, performance, and ease of use. * Coordinate with software teams to ensure hardware-software integration and functionality. * Engage with product planning teams to align hardware development with market needs. * Interface with customers to understand requirements and deliver tailored solutions. * Lead implementation groups to ensure successful deployment and operation of hardware systems. PREFERRED EXPERIENCE: * Extensive experience in hardware architecture design and development, particularly in adaptive and embedded systems. * Proven track record in managing complex projects and delivering innovative solutions. * Strong understanding of FPGA technology and implementation algorithms. * Excellent collaboration skills with the ability to work across multiple teams and disciplines. * Experience in government contract management and compliance. * Ability to evaluate and integrate new technologies into existing frameworks. * Strong communication skills to effectively engage with customers and stakeholders. #LI-IL1 #LI-HYBRID This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE PERSON: This role is ideal for a strategic thinker who thrives in solving large-scale technical challenges without losing sight of execution realities. You are: * A visionary and a builder - someone who can define and improve DV frameworks that will last through generations of silicon. * A mentor and a unifier - guiding diverse teams across geographies and backgrounds, aligning them to a shared DV mission. * A strong communicator who brings clarity and confidence when navigating ambiguity or resolving conflicting technical perspectives. * Comfortable influencing without authority and leading through technical credibility * Motivated by impact - not just doing DV but transforming how it's done at scale. THE ROLE: At AMD, we believe in "We before Me" - and this role exemplifies that value. Success here means making those around you better through leadership, knowledge sharing, and collaboration. * We are building high-performance computing technologies that are powering the future - from gaming and AI to hyperscale data centers and beyond. To help us continue this trajectory of excellence and innovation, we're looking for a Design Verification Architect AI/ML focus to drive the strategic vision of DV for our next-generation CPU cores. * This is a technical leadership position focused on methodology design, infrastructure planning, and team enablement. You will set the standard for quality, coverage, and scalability across a wide array of processor verification efforts. * If you have multiple successful tape-outs, a vision for world-class DV strategy, and the ability to orchestrate technical teams toward measurable impact, this role is your opportunity to shape the core of AMD's processor roadmap. KEY RESPONSIBILITIES: * Define and own the overall DV architecture for high-performance CPU cores, ensuring scalability across variants and generations. * Collaborate closely with design, microarchitecture, emulation, and verification leads/architects to build aligned verification strategies. * Lead the evaluation and enhancement of AMD's DV infrastructure and methodologies, to drive RTL quality and project intercept. * Provide technical mentorship and strategic direction to DV leads and engineers across global AMD sites. * Anticipate architectural and verification risks early and drive systemic solutions before they impact delivery. * Influence cross-functional decision-making through a blend of technical insight and collaborative communication. * Champion long-term DV innovation by staying current on AI/ML techniques, formal verification, and emulation strategies - and knowing when to integrate them into project flow. PREFERRED EXPERIENCE: * Expertise in Design Verification with an emphasis on CPU architecture and core-level verification, or strong AI/ML deployment experience * Strong grasp of DV methodologies: coverage-driven verification, formal, and infrastructure strategy. * Solid understanding of computer architecture fundamentals: pipelines, caching, coherency, load/store, execution units, etc. * Strong documentation, planning, and cross-functional coordination skills. * Familiarity with x86 or ARM CPU cores, or AI/ML deployments ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Santa Clara #LI-DC1 #HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ Power Management Architect The Role: Drive the definition, tradeoff studies, protyping, implementation and verification of the Power Management Architecture features and algorithms for Radeon gaming and datacenter GPUs. Collaborate closely with a wide array of engineering disciplines to create leadership products that delight our customers. The Person: This is an experienced engineer who brings a deep understanding of SoC and Platform architecture, Power Management concepts and algorithms, and a passion to drive perf/watt and perf/$ optimizations for worldclass GPUs. Previous experience in the areas of voltage margin optimization, reliability and yield management, statistical analysis of silicon manufacturing/test data will be a bonus. Key Responsibilities: Drive Power Management advances and multi-generational roadmap in the area of voltage optimization, with an eye on silicon reliability and yeild, to maximize power and cost constrained performance for Radeon graphics platforms Take ownership for developing and driving PM features from concept through product launch for a family of SoC devices with varying configurations and target market segments Work cross functionally with Software, Firmware, SOC, IP, Platform, Technology, Product teams through every stage of product development, evangelize for power efficiency, lead broad forums and drive product definition alignment Work with product teams to understand the Perf/Power/Cost requirements Drive power management feature definition per SoC program Develop system level models, analyze return-on-investment and evaluate trade-offs Document specifications Guide power management feature implementation, verification, emulation and post-silicon validation in an engineering resource efficient and scalable manner Coach and mentor other engineers as a technical leader Preferred Experience: Proven experience with GPU or CPU power architecture, PPA tradeoffs, power management algorithms, embedded microcontroller firmware, hardware test and verification environments Solid background in electrical circuits, VLSI and circuit design fundamentals Familiarity with ASIC/SoC Design cycles and methodologies including RTL, Verification, Emulation, Physical Design and post-si validation Background in prototyping and proof of concept of new complex architectures and algorithms in hardware/software/firmware using physical and/or emulation platforms will be a plus Programming skills in C/C++, scripting with Perl or Python Previous experience in the areas of voltage margin optimization, reliability and yield management, statistical analysis of silicon manufacturing/test data will be a major differentiator Ability to work cross functionally with HW/SW and Pre/Post Silicon teams, lead by influence and strong communication skills Academic Credentials: Bachelor's Degree in Electrical Engineering, Computer Engineering, or another relevant field. Masters or Ph.D. preferred Location: Santa Clara, CA - Austin, TX - Markham, Ontario #LI-SW2 Requisition Number: 150682 Country: United States State: California City: Santa Clara Job Function: Product Engineering Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for a GPU Machine Learning Architect to join GPU architecture team developing Deep Learning Architecture and GPU kernels for architecture exploration, development and performance verification THE PERSON: The successful person will be an experienced GPU-compute or graphics hardware developer and programmer with an eye towards hardware/software-aware performance implementations and optimizations. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Good teamwork and interpersonal skills required. Ability to work independently and within complementary teams. Demonstrate flexibility, strong motivation and a proven track record of meeting results-oriented deadlines. KEY RESPONSIBILITIES: * They will play a key role in all phases of GPU architecture development including architecture feature development and analysis, performance projection, and performance analysis across different platforms. * The ideal candidate will be responsible for writing high performance GPU kernels for Machine Learning applications to run on AMD's next generation GPU.\ * They will be porting and optimizing algorithms for new GPU architecture, perform code reviews, authoring detailed documentation related to their work. PREFERRED EXPERIENCE: * Strong programming skills in C/C++, HIP, and CUDA * Extensive experience with machine learning * Experience with GPU ML runtimes and compilers * Experience using version control software such as Git * Strong understanding of GPU architecture * Knowledge of Parallel-Computing, GPUs, and 3D graphics * Familiarity with deep neural network machine learning technologies and modern machine learning programming frameworks ACADEMIC CREDENTIALS: * PhD in computer architecture/Electrical Engineering preferred. This role is not eligible for Visa sponsorship. #LI-BM1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This role offers a rare opportunity for a senior technical leader to shape the future of memory interface technology at scale. As a key architect within the AMD Circuit Technology Design Group, you will influence the definition, architecture, and delivery of next-generation Memory PHY solutions in advanced CMOS technologies. The focus is on long-term impact: setting technical direction, guiding critical design decisions, and enabling teams to deliver differentiated mixed-signal IP across future SoCs. This position is well suited for technologists who value deep technical ownership, architectural influence, and the ability to leave a lasting technical legacy-without requiring people-management as a primary responsibility. THE PERSON: You are a highly respected engineer or architect known for solving difficult problems and raising the technical bar around you. You bring perspective earned from experience, approach challenges with curiosity and pragmatism, and engage others through thoughtful collaboration rather than authority. You are comfortable operating with ambiguity, influencing across organizations, and contributing at both strategic and hands-on technical levels. KEY RESPONSIBILITIES: * Serve as a senior technical authority and architect for Memory PHY technology, shaping long-range roadmaps and architectural direction. * Define and evolve architectures and specifications for advanced Memory PHYs, including DDR, LPDDR, GDDR, and HBM. * Drive innovation in high-speed I/O circuit design, system-level analysis, power integrity, and signal integrity. * Partner with cross-functional teams across Circuit Design, Layout, Logic Design, Physical Design, Firmware, Design Verification, and Post-Silicon organizations worldwide. * Influence design quality and execution through design reviews, technical mentorship, and principled tradeoff decisions. * Support post-silicon bring-up, validation, characterization, optimization, and product readiness. * Communicate complex technical concepts clearly to senior technical peers, leadership, and stakeholders. * Mentor and advise engineers and architects, contributing to a strong and inclusive technical community. PREFERRED EXPERIENCE: * Sustained technical impact on production Memory PHYs or high-speed I/O IP at advanced technology nodes. * Experience owning or shaping architecture across multiple successful tape-outs. * Deep expertise in high-speed analog and mixed-signal design, memory protocols, and system-level considerations. * Strong understanding of advanced CMOS technologies and modern design methodologies. * Track record of making sound technical decisions in complex, high-risk design spaces. * Ability to influence without formal authority and collaborate effectively across organizational boundaries. ACADEMIC CREDENTIALS: * Advanced degree in Electrical Engineering or related field preferred, or equivalent professional experience. * Typically, 15+ years of experience in high-speed analog, mixed-signal, or memory PHY design. LOCATION: Flexible - Bay Area, CA; Boston, MA; Austin, TX; or Toronto, Canada. This role is not eligible for visa sponsorship. #LI-ML4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves working with design architecture, design DFT/DFX, design block owners and physical design teams with ATE manufacturing environment, silicon debug, product quality and test cost perspectives. The DFT architect is expected to apply past technical knowledge, learn new cutting-edge technologies and collaborate with teams to arrive at best manufacturable solution. The DFT architect will ensure that DFT implementation is completed by architecture design specifications. This is the role of overseeing early architecture design definition to successful silicon high-volume production. THE PERSON: We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization. KEY RESPONSIBILITIES: * Promote ATE & production test environment, test cost and test quality enhancements in future AMD products through DFT architecture definitions and specifications * Manage DFT activities across architecture, design implementation, verification, and test implementation for new products. * The role is in AMD global quality and operation organization driving best manufacturing test solution through early product definition and pre & post silicon activities * Work closely with design teams and make sure DFT structures are correctly implemented. * Drive internal DFT teams to correctly implement and create test solutions * Drive firmware driven test solutions * Plan for diagnosability and yield improvement PREFERRED EXPERIENCE: * Significant DFT engineering experience through DFT pre and post silicon cycles * Experience in creating and implementing complex chip-level DFT architecture * Experience in DFT implementation including Scan and Scan Compression at IP and SoC level * Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression. * Strong MBIST knowledge * Experience in PHY, high-speed IO, digital communication and functional test development * Knowledge of Tessent Streaming Scan Network SSN and hand-on experience is a big plus * Good understanding of Verilog, synthesis, physical implementation and STA * Good understanding of verification methodology * Knowledge of FPGA logic, synthesis and design flow is a plus * Knowledge of embedded design and firmware methodology is a plus * Experience with post-silicon debug and bench equipment (e.g., oscilloscope and logic analyser) * Good communication skills and works well in a group environment that spans across continents ACADEMIC CREDENTIALS: * MS or Ph.D. in Electrical/Electronic/Computer Engineering LOCATION: San Jose, California, United States This role is not eligible for visa sponsorship. #LI-AJ1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE We are seeking an SoC Architect specializing in Boot, Firmware, and Software/Hardware Interfacing. In this role, you will define and drive firmware architecture for next-generation SoCs, ensuring robust boot flows and compliance with functional safety standards. You will collaborate closely with other SoC architects to integrate firmware seamlessly with processor subsystems, interconnects, and system-level components. THE PERSON You are passionate about SoC architecture and firmware design, with deep expertise in boot flows for ARM and x86 platforms. You thrive in cross-functional environments, balancing performance, power, and reliability trade-offs. You have strong analytical skills, excellent communication, and the ability to influence architecture decisions across teams. KEY RESPONSIBILITIES * Define and develop firmware architecture for SoC boot flows, reset sequences, and system initialization. * Collaborate with SoC architects to ensure cohesive integration of firmware with hardware components. * Specify requirements and create detailed documentation for boot and firmware interfaces. * Drive implementation of functional safety-compliant firmware and software. * Partner with design, verification, and software teams to ensure functional correctness and system-level validation. * Analyze trade-offs for performance, power, reliability, and safety in firmware design. * Influence strategies for security, safety, and lifecycle management across firmware domains. PREFERRED EXPERIENCE * Experience in ARM and x86 SoC boot flows, including secure boot and power-on initialization. * Expertise in firmware development for SoCs, including low-level drivers and hardware abstraction layers. * Experience with functional safety compliance (ISO 26262 or equivalent) for firmware and software. * Familiarity with SoC architecture, processor subsystems, interconnect protocols (e.g., AXI), and memory systems. * Knowledge of low-power design techniques, reset flows, and power management. * Proficiency in modeling and automation using C, Python or similar languages. * Strong understanding of security and reliability strategies for embedded firmware. ACADEMIC & EXPERIENCE REQUIREMENTS * BS, MS, or PhD in Computer/Electrical Engineering or related field. * 8+ years of experience in SoC architecture and firmware development. * Proven track record in delivering architecture for SoCs with robust boot and firmware solutions. LOCATION: Austin, Texas Preferred. #LI-RW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: SerDes Technology group is seeking a talented, motivated and self-driven SerDes Micro Architect with expertise in high-speed SerDes RTL design. You have had significant success driving architecture and product requirements, integrating complex IPs into SOC. You have deep knowledge of digital design methodology and are meticulous about Power, Performance and Area. In this role, you will work with a world-class team to drive the definition of next generation high-speed SerDes IPs. THE PERSON: If you have a keen interest in high-speed SerDes and digital RTL design, excel in teamwork and possess strong communication skills, your profile aligns well with our requirements. We are seeking someone who is innovative, detail-oriented and possesses excellent problem-solving skills to join our design team. KEY RESPONSIBILITIES: * Define micro-architecture requirements for SerDes IPs, drive technical specifications to meet those requirements, and provide technical direction to execution teams * Design and development of digital logic blocks in leading edge technology nodes * Work with cross-functional teams to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements * Work closely with design teams for area and floorplan refinement, verification test plan reviews, timing targets, emulation plans, pre-Si bug resolution and performance/power verification sign offs * Support post-Si teams for product performance, power and functional issues debug/resolution PREFERRED EXPERIENCE: * Excellent communication, management, and presentation skills * Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies * Experience in driving the definition of high-speed SerDes IPs, with strong knowledge on the application in PCIe and Ethernet * Experience in system architecture, CPU & IP Integration, power and clock management design * Experience in RTL design, verification, synthesis and STA in high performance design * Good understanding of adaptation and calibration algorithms * Good understanding of link equalization, clock and data recovery * Good understanding of digital signal processing * Good knowledge of SystemVerilog and UVM ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in related discipline LOCATION: San Jose, CA #LI-SC3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are excited to welcome highly talented engineers and application engineers to join our Cadence North America Field Applications Team. Working at Cadence means working alongside the industry's brightest people and innovating for the most advanced companies in the world. Through Cadence's Electronic Design Automation (EDA) products, we've worked with a wide range of customers, from helping build the world's most powerful supercomputer to innovating in the field of artificial intelligence and machine learning. As an expert Digital Implementation and Signoff Field Applications Engineering (AE) , you will work side-by-side with our leading edge customers. With your expertise, you'll help them deploy Cadence's market-leading technologies in Synthesis, P&R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts into reality. The greater your powers, the more business opportunities you'll help bring to the table. You will also work directly with the Cadence R&D group to drive the customer requirements and influence the direction of Cadence next-generation products and technologies. At Cadence, customers are at the heart of everything we do. Talented leaders like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in nanometer design, unlock unique expertise in digital design implementation, and level up your communication, customer, and sales skills. Key Responsibilities + Lead a team of Application Engineers providing technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff + Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules + Collaborate with team to conduct technical presentations and product demonstrations + Drive technical evaluations/benchmarks to success + Work closely with R&D to enhance the tools and methodologies to meet and exceed customer's requirements + Drive adoption and proliferation of Cadence tools and technologies + Provide guidance to the team to amend & augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows + Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements Job Requirements Minimum + 15+ years of industry Physical Design experience + BS degree Computer Science/Engineering, Electrical, Engineering, or related field + Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required + Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure + Experience with advanced nodes 10nm and below + Experience in scripting languages such as Tcl/Perl/Python is a must + Strong customer-facing communication and problem-solving skills + Strong personal drive for continuous learning and expanding professional skill sets + Strong verbal, written, and customer communication skills Preferred + MS degree Computer Science/Engineering, Electrical, Engineering, or related field + Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking + Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired + Experience with advanced nodes 5nm and below The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are excited to welcome highly talented engineers and application engineers to join our Cadence North America Field Applications Team. Working at Cadence means working alongside the industry's brightest people and innovating for the most advanced companies in the world. Through Cadence's Electronic Design Automation (EDA) products, we've worked with a wide range of customers, from helping build the world's most powerful supercomputer to innovating in the field of artificial intelligence and machine learning. As an expert Digital Implementation and Signoff Field Applications Engineering (AE) , you will work side-by-side with our leading edge customers. With your expertise, you'll help them deploy Cadence's market-leading technologies in Synthesis, P&R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts into reality. The greater your powers, the more business opportunities you'll help bring to the table. You will also work directly with the Cadence R&D group to drive the customer requirements and influence the direction of Cadence next-generation products and technologies. At Cadence, customers are at the heart of everything we do. Talented leaders like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in nanometer design, unlock unique expertise in digital design implementation, and level up your communication, customer, and sales skills. Key Responsibilities Lead a team of Application Engineers providing technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules Collaborate with team to conduct technical presentations and product demonstrations Drive technical evaluations/benchmarks to success Work closely with R&D to enhance the tools and methodologies to meet and exceed customer's requirements Drive adoption and proliferation of Cadence tools and technologies Provide guidance to the team to amend & augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements Job Requirements Minimum 15+ years of industry Physical Design experience BS degree Computer Science/Engineering, Electrical, Engineering, or related field Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure Experience with advanced nodes 10nm and below Experience in scripting languages such as Tcl/Perl/Python is a must Strong customer-facing communication and problem-solving skills Strong personal drive for continuous learning and expanding professional skill sets Strong verbal, written, and customer communication skills Preferred MS degree Computer Science/Engineering, Electrical, Engineering, or related field Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired Experience with advanced nodes 5nm and below The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. + Digital signal processing expert + Create ultra high-speed micro-architectures for serial data transmission and reception at 200Gb/s, 400Gb/s and above + Model impairments (e.g. linearity, noise, crosstalk) in associated with electronic and optical components and interact with analog and optical designers + Interact with Cadence customers to specify new IP products + Represent Cadence at standards bodies including PCI-SIG, 802.3 and OIF PhD or MS in Electrical Engineering desired by not required The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Digital signal processing expert Create ultra high-speed micro-architectures for serial data transmission and reception at 200Gb/s, 400Gb/s and above Model impairments (e.g. linearity, noise, crosstalk) in associated with electronic and optical components and interact with analog and optical designers Interact with Cadence customers to specify new IP products Represent Cadence at standards bodies including PCI-SIG, 802.3 and OIF PhD or MS in Electrical Engineering desired by not required The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.