Application Engineer jobs at Cadence Design Systems

- 176 jobs

Application Engineer Architect
Cadence Design Systems, Inc. 4.7
Application engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are excited to welcome highly talented engineers and application engineers to join our Cadence North America Field Applications Team. Working at Cadence means working alongside the industry's brightest people and innovating for the most advanced companies in the world. Through Cadence's Electronic Design Automation (EDA) products, we've worked with a wide range of customers, from helping build the world's most powerful supercomputer to innovating in the field of artificial intelligence and machine learning. As an expert Digital Implementation and Signoff Field Applications Engineering (AE) , you will work side-by-side with our leading edge customers. With your expertise, you'll help them deploy Cadence's market-leading technologies in Synthesis, P&R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts into reality. The greater your powers, the more business opportunities you'll help bring to the table. You will also work directly with the Cadence R&D group to drive the customer requirements and influence the direction of Cadence next-generation products and technologies. At Cadence, customers are at the heart of everything we do. Talented leaders like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in nanometer design, unlock unique expertise in digital design implementation, and level up your communication, customer, and sales skills. Key Responsibilities + Lead a team of Application Engineers providing technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff + Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules + Collaborate with team to conduct technical presentations and product demonstrations + Drive technical evaluations/benchmarks to success + Work closely with R&D to enhance the tools and methodologies to meet and exceed customer's requirements + Drive adoption and proliferation of Cadence tools and technologies + Provide guidance to the team to amend & augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows + Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements Job Requirements Minimum + 15+ years of industry Physical Design experience + BS degree Computer Science/Engineering, Electrical, Engineering, or related field + Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required + Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure + Experience with advanced nodes 10nm and below + Experience in scripting languages such as Tcl/Perl/Python is a must + Strong customer-facing communication and problem-solving skills + Strong personal drive for continuous learning and expanding professional skill sets + Strong verbal, written, and customer communication skills Preferred + MS degree Computer Science/Engineering, Electrical, Engineering, or related field + Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking + Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired + Experience with advanced nodes 5nm and below The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
$157.5k-292.5k yearly 13d ago
Application Engineer Architect
Cadence Design Systems 4.7
Application engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are excited to welcome highly talented engineers and application engineers to join our Cadence North America Field Applications Team. Working at Cadence means working alongside the industry's brightest people and innovating for the most advanced companies in the world. Through Cadence's Electronic Design Automation (EDA) products, we've worked with a wide range of customers, from helping build the world's most powerful supercomputer to innovating in the field of artificial intelligence and machine learning. As an expert Digital Implementation and Signoff Field Applications Engineering (AE) , you will work side-by-side with our leading edge customers. With your expertise, you'll help them deploy Cadence's market-leading technologies in Synthesis, P&R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts into reality. The greater your powers, the more business opportunities you'll help bring to the table. You will also work directly with the Cadence R&D group to drive the customer requirements and influence the direction of Cadence next-generation products and technologies. At Cadence, customers are at the heart of everything we do. Talented leaders like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in nanometer design, unlock unique expertise in digital design implementation, and level up your communication, customer, and sales skills. Key Responsibilities Lead a team of Application Engineers providing technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules Collaborate with team to conduct technical presentations and product demonstrations Drive technical evaluations/benchmarks to success Work closely with R&D to enhance the tools and methodologies to meet and exceed customer's requirements Drive adoption and proliferation of Cadence tools and technologies Provide guidance to the team to amend & augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements Job Requirements Minimum 15+ years of industry Physical Design experience BS degree Computer Science/Engineering, Electrical, Engineering, or related field Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure Experience with advanced nodes 10nm and below Experience in scripting languages such as Tcl/Perl/Python is a must Strong customer-facing communication and problem-solving skills Strong personal drive for continuous learning and expanding professional skill sets Strong verbal, written, and customer communication skills Preferred MS degree Computer Science/Engineering, Electrical, Engineering, or related field Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired Experience with advanced nodes 5nm and below The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.
$157.5k-292.5k yearly Auto-Apply 14d ago
Staff Applications Engineer in Power uModule Group
Analog Devices 4.6
San Jose, CA jobs
Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at ************** and on LinkedIn and Twitter (X). Analog Devices is committed to investing in our people and their growth. Our hiring program features high-impact professional development, opportunities to drive meaningful projects that are directly tied to business goals, and unique executive exposure. We aim to develop new talent and provide practical, real-world experience. The ADI Power uModule Team is seeking a skilled Staff Applications Engineer to advance our uModule business. This role is ideal for a talented engineer ready to independently deliver complex solutions and contribute deep technical expertise to the team and customers. Key Responsibilities Execute development of innovative power module solutions, focusing on technical excellence in design and customer support. Lead technical investigations and define specifications within your product area, collaborating closely with immediate product and engineering teams. Drive evaluation, optimization, and testing to enhance converter and system performance for a diverse set of applications. Provide direct technical support to marketing, field teams, and customers, ensuring successful product adoption. Develop and refine simulation models, tools, and circuits within assigned product lines. Create technical documentation and deliver presentations for team and customer audiences. Mentor junior engineers within the immediate team. Minimum Qualifications MSEE in power electronics plus at least 4 years of relevant experience. Demonstrated technical leadership within a product or functional team. Strong expertise in designing, building, and testing switching-mode power supplies. Skilled with simulation and modeling tools. Excellent communication and teamwork skills; able to collaborate in multidisciplinary environments. Preferred Qualifications Experience in schematic design, PCB layout, simulation, prototyping, and lab evaluation. Familiarity with analog IC design and multiphase converters. Experience supporting customer engagements and delivering technical training. Knowledge of embedded programming and communication protocols (e.g., I2C/PMbus). For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. Job Req Type: ExperiencedRequired Travel: Yes, 10% of the time Shift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $144,038 to $216,056. Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.
$144k-216.1k yearly Auto-Apply 6d ago
Senior Engineer, Field Applications
Analog Devices 4.6
San Jose, CA jobs
Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at ************** and on LinkedIn and Twitter (X). Employer: Analog Devices, Inc. Job Title: Senior Engineer, Field Applications Job Requisition: R258790 Job Location: San Jose, California Job Type: Full Time Rate of Pay: $156,853.00 - $188,370.00 per year Duties: Focus primarily on power products, support customer needs to yield optimal solutions at system level. Team up with Sales to provide technical field applications support to Strategic and Key Consumer and Automotive customers with system knowledge. Drive technology discussions and design ins for specific product areas with a focus on maximizing share, forming deep customer relationships, and driving exemplary customer satisfaction. Direct interface with customer providing technical guidance for power products, support recommended solutions, Design and Simulation works, schematic reviews, PCB layout and validation reports, on-site troubleshooting, debug board and system level issues, and help QA teams with field issues. Work with Product Lines in defining and developing new products to address future customer needs. Collect customer's technical requirements and macro trend of the application. Develop and maintain strong relationships with key Product Lines' Management, Marketing, and Application. Requirements: Must have a Master's degree in Electrical Engineering, Electronic Engineering, Computer Science, Computer Engineering, or closely related technical field (willing to accept foreign education equivalent) and two (2) years of experience as a Power Conversion Design Engineer or related occupation performing analog or power design and verification. Must also possess the following (quantitative experience requirements not applicable to this section): Demonstrated Expertise (DE) in power conversion topologies: Buck and Boost and Flyback and BAT-charger and LDO and Inverter design/evaluation/characterization; DE in Loop Stability and System Dynamics Design/Analysis for power systems; DE in CAD and Simulation Tools: LTSpice and Simplis and Allegro and Visio, and Matlab; DE in application of communication Bus: I2C and PMBUS and SPI; DE in general system level knowledge and hardware design, especially in high efficiency and very low power consumer-products, power solution optimization based on customer requirements, and power tree design at the board/system level; DE in customer interface and technical presentation; and DE in test equipment use, PCB rework, soldering skills, and test setups. Contact: Eligible for employee referral program. Apply online at https://**************/en/about-adi/careers.html and Reference Position Number: R258790 . For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. Job Req Type: ExperiencedRequired Travel: NoShift Type: 1st Shift/Days Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.
$156.9k-188.4k yearly Auto-Apply 7d ago
Application Engineer Architect
Cadence 4.7
Application engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are excited to welcome highly talented engineers and application engineers to join our Cadence North America Field Applications Team. Working at Cadence means working alongside the industry's brightest people and innovating for the most advanced companies in the world. Through Cadence's Electronic Design Automation (EDA) products, we've worked with a wide range of customers, from helping build the world's most powerful supercomputer to innovating in the field of artificial intelligence and machine learning. As an expert Digital Implementation and Signoff Field Applications Engineering (AE) , you will work side-by-side with our leading edge customers. With your expertise, you'll help them deploy Cadence's market-leading technologies in Synthesis, P&R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts into reality. The greater your powers, the more business opportunities you'll help bring to the table. You will also work directly with the Cadence R&D group to drive the customer requirements and influence the direction of Cadence next-generation products and technologies. At Cadence, customers are at the heart of everything we do. Talented leaders like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in nanometer design, unlock unique expertise in digital design implementation, and level up your communication, customer, and sales skills. Key Responsibilities * Lead a team of Application Engineers providing technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff * Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules * Collaborate with team to conduct technical presentations and product demonstrations * Drive technical evaluations/benchmarks to success * Work closely with R&D to enhance the tools and methodologies to meet and exceed customer's requirements * Drive adoption and proliferation of Cadence tools and technologies * Provide guidance to the team to amend & augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows * Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements Job Requirements Minimum * 15+ years of industry Physical Design experience * BS degree Computer Science/Engineering, Electrical, Engineering, or related field * Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required * Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure * Experience with advanced nodes 10nm and below * Experience in scripting languages such as Tcl/Perl/Python is a must * Strong customer-facing communication and problem-solving skills * Strong personal drive for continuous learning and expanding professional skill sets * Strong verbal, written, and customer communication skills Preferred * MS degree Computer Science/Engineering, Electrical, Engineering, or related field * Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking * Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired * Experience with advanced nodes 5nm and below The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.
$157.5k-292.5k yearly Auto-Apply 12d ago
Field Applications Engineer - Rotational Program
Analog Devices 4.6
San Jose, CA jobs
Come join Analog Devices (ADI) - a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare. ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future. About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at ************** and on LinkedIn and Twitter (X). Our rotation programs are a great way for you to understand different business/technology groups, practice relevant skills, and meet key connections for your future at ADI. Within the Graduate Rotational Development Program, you will be placed in an 18 month program that offers real-world experience, providing an excellent foundation for career growth and advancement. During the program, you will go through a structured, progressive curriculum including four rotations where you will receive professional development opportunities and mentorship before integration into the sales team. In addition, some skills you will develop include, but are not limited to: Analog / Mixed-Signal circuit and system design Assisting in the design and evaluation of customer systems - hardware and software Understanding and disseminating Customers' system needs versus wants Developing and maintaining relationships with customers and ADI's product line management, marketing, and engineering Educating customers about ADI's products, services, and system solutions through technical presentations and demonstrations Sales Integration Overview: After completing the Graduate Rotational Development Program, you will enter Analog Devices' sales organization as a Field Applications Engineer (FAE) in the greater (Denver, CO; Livonia, MI; San Diego, CA; Tampa, FL; or Milwaukee, WI) marketplace. As a FAE, you will work collaboratively with our sales team to engage our customers, understanding and solving their most challenging application-level problems that span a broad range of technologies in many end markets, including digital healthcare, aerospace and defense, industrial, etc. What you need to be successful in this role: Experience with lab equipment such as oscilloscopes, along with soldering and debugging skills Solid analytical and problem-solving skills Excellent communication and presentation skills Ability to work in teams and collaborate effectively with people in different functions Strong time management skills that enable on-time project delivery Ability to build lasting, influential relationships, internal and external Ability to work effectively in a fast-paced and changing environment Ability to take initiative and drive for results Ability to influence decisions through a sense of urgency and competitive drive Requirements: Bachelor's degree in Electrical Engineering or Computer Engineering Basic understanding of schematics, layouts and electronic components Knowledge and understanding of analog, mixed-signal, or digital circuitry (e.g., sensors, op-amps, DC/DC power, data converters, processors, etc.) Ability to travel 10% of the time Flexibility and desire to relocate to the Field upon completion of the development program. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. Job Req Type: Graduate JobRequired Travel: Yes, 25% of the time The expected wage range for a new hire into this position is $86,400 to $118,800. Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.
$86.4k-118.8k yearly Auto-Apply 58d ago
STA Principal Application Engineer
Cadence Design Systems, Inc. 4.7
Application engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities; Perform Static timing analysis, glitch, noise analysis using Tempus Signoff tool. Executing and delivering on various aspects of Timing analysis flows, ECO flows, CAD tools and methodologies. · Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. · Work efficiently with R&D and customer to enable various timing analysis & ECO flows including newer advanced technologies. · Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. · Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route, Clock Tree, RC Extraction and UPF/CPF concepts. · Execute and lead Tempus timing signoff campaigns at existing and new customers. · Automation of flows using scripting languages (Perl, Tcl, python). · Deliver technical trainings and seminars within Cadence and customer sites. Requirements; 8+ years of experience in Static timing analysis, Individual should be able to lead and execute technical campaigns at various internal and external customers. Perform several timing & correlation benchmarks with Cadence Tempus -Signoff tool. Execute and deliver on timing analysis & ECO flows and ensure integrity of delivered solutions. Individual should be able to efficiently work with Cadence R&D to enable various tool feature and close tool bug fixes. Work on various aspects of physical design including timing analysis, place and route, extraction, spice etc. The annual salary range for California is $123,200 to $228,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
$123.2k-228.8k yearly 60d+ ago
Principal Application Engineer
Cadence Design Systems, Inc. 4.7
Application engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. As an expert Digital Implementation and Signoff Field Applications Engineering (AE) , you will work side-by-side with our leading edge customers. With your expertise, you'll help them deploy Cadence's market-leading technologies in Synthesis, P&R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts into reality. The greater your powers, the more business opportunities you'll help bring to the table. You will also work directly with the Cadence R&D group to drive the customer requirements and influence the direction of Cadence next-generation products and technologies. At Cadence, customers are at the heart of everything we do. Talented leaders like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in nanometer design, unlock unique expertise in digital design implementation, and level up your communication, customer, and sales skills. Key Responsibilities + Be part of team of Application Engineers providing technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff + Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules + Collaborate with team to conduct technical presentations and product demonstrations + Drive technical evaluations/benchmarks to success + Work closely with R&D to enhance the tools and methodologies to meet and exceed customer's requirements + Drive adoption and proliferation of Cadence tools and technologies + Provide guidance to the team to amend & augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows + Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements Job Requirements Minimum + 10+ years of industry Physical Design experience + BS degree Computer Science/Engineering, Electrical, Engineering, or related field + Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required + Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure + Experience with advanced nodes 10nm and below + Experience in scripting languages such as Tcl/Perl/Python is a must + Strong customer-facing communication and problem-solving skills + Strong personal drive for continuous learning and expanding professional skill sets + Strong verbal, written, and customer communication skills Preferred + MS degree Computer Science/Engineering, Electrical, Engineering, or related field + Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking + Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired + Experience with advanced nodes 5nm and below The annual salary range for California is $123,200 to $228,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
$123.2k-228.8k yearly 60d+ ago
STA Principal Application Engineer
Cadence 4.7
Application engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities; Perform Static timing analysis, glitch, noise analysis using Tempus Signoff tool. Executing and delivering on various aspects of Timing analysis flows, ECO flows, CAD tools and methodologies. * Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. * Work efficiently with R&D and customer to enable various timing analysis & ECO flows including newer advanced technologies. * Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. * Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route, Clock Tree, RC Extraction and UPF/CPF concepts. * Execute and lead Tempus timing signoff campaigns at existing and new customers. * Automation of flows using scripting languages (Perl, Tcl, python). * Deliver technical trainings and seminars within Cadence and customer sites. Requirements; 8+ years of experience in Static timing analysis, Individual should be able to lead and execute technical campaigns at various internal and external customers. Perform several timing & correlation benchmarks with Cadence Tempus -Signoff tool. Execute and deliver on timing analysis & ECO flows and ensure integrity of delivered solutions. Individual should be able to efficiently work with Cadence R&D to enable various tool feature and close tool bug fixes. Work on various aspects of physical design including timing analysis, place and route, extraction, spice etc. The annual salary range for California is $123,200 to $228,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.
$123.2k-228.8k yearly Auto-Apply 60d+ ago
STA Principal Application Engineer
Cadence Design Systems 4.7
Application engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities; Perform Static timing analysis, glitch, noise analysis using Tempus Signoff tool. Executing and delivering on various aspects of Timing analysis flows, ECO flows, CAD tools and methodologies. · Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. · Work efficiently with R&D and customer to enable various timing analysis & ECO flows including newer advanced technologies. · Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. · Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route, Clock Tree, RC Extraction and UPF/CPF concepts. · Execute and lead Tempus timing signoff campaigns at existing and new customers. · Automation of flows using scripting languages (Perl, Tcl, python). · Deliver technical trainings and seminars within Cadence and customer sites. Requirements; 8+ years of experience in Static timing analysis, Individual should be able to lead and execute technical campaigns at various internal and external customers. Perform several timing & correlation benchmarks with Cadence Tempus -Signoff tool. Execute and deliver on timing analysis & ECO flows and ensure integrity of delivered solutions. Individual should be able to efficiently work with Cadence R&D to enable various tool feature and close tool bug fixes. Work on various aspects of physical design including timing analysis, place and route, extraction, spice etc. The annual salary range for California is $123,200 to $228,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.
$123.2k-228.8k yearly Auto-Apply 60d+ ago
Field Application Engineer, Server Datacenter - Supermicro
Advanced Micro Devices, Inc. 4.9
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD's Partner Support Field Applications Engineering Organization is responsible for supporting our OEM and ODM partners as they define and develop new platforms based on AMD technology. We are looking for our next team member to support new product introduction and debug efforts with our global datacenter customers, focusing on solutions involving GPUs, CPUs, and associated diagnostic and development tools. THE PERSON: Does this sound like you? We'd love to talk! * Excellent problem-solving, time-management, prioritization, and organizational skills, able to lead complex problems, involving multi-disciplined, multi-functional teams and many priorities at once * A standout colleague with excellent collaborative skills, and ability to work independently or as part of a team * Outstanding oral and written communication skills and demonstrated success in building strong technical relationships (internal: Sales, Marketing, Engineering and external: OEM) * Attention to detail combined with outstanding planning and organizational skills KEY RESPONSIBILITIES: Main focus: At-scale debug activities with customers are a primary focus for this role. The scope of these activities will span the entire hardware and software stack, including deployments of GPUs and CPUs in datacenter environments. Responsibilities will include: * Reproducing complicated customer issues onsite at AMD. * Working with internal engineering teams to debug & root cause issues. * Developing, setting Up & analyzing experiments to collect data for guiding debug activities. * Setting up complicated test harnesses in Software & Hardware to collect low level debug logs. * Developing scaffolding software to assist in debug activities both Internally & Externally with customers. * Package workloads & customer test cases for internal debug teams to reproduce issues. * Drive internal debug activity by playing the role of issue coordinator when needed. * Customer presentations, being the trusted advisors to AMD's key OEM partner. PREFERRED EXPERIENCE: Proven experience with Server and/or GPU architecture, either integrating, debugging, and/or validating various system components. Server software environments include Operating systems (Windows, Linux), compilers, benchmarks, and targeted applications that may be used to validate server platforms. developing and debugging low level server-based applications, or validating HW components - CPU, GPU, Boards, Storage, etc. Additional Preferred Qualifications: * Experience with large-scale rollouts of datacenter equipment. * Networking knowledge -- TCP/IP, RDMA, RoCE, NICs, Switches, etc. * Familiarity with AI Models and PCIe Architecture * Proficient in server software ecosystem (ie: OS/Hypervisors, Compilers, Libraries, debug tools, development tools and validation workloads). * Knowledgeable in platform firmware features (BIOS, BMC, SMU). * Hands-on experience and strong expertise in server hardware ecosystem at the node, rack and datacenter level. ACADEMIC CREDENTIALS: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a similar field with proven relevant industry professional experience LOCATION: Bay Area, CA This role is not eligible for visa sponsorship. #LI-RF1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$117k-156k yearly est. 5d ago
Principal Applications Engineer (ASIC/SoC/IP Engineer) - 12953
Synopsys, Inc. 4.4
Sunnyvale, CA jobs
Category Engineering Hire Type Employee Job ID 12953 Base Salary Range $183000-$275000 Remote Eligible No Date Posted 16/10/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced ASIC/SoC/Chiplet Architect, Manager or Design Engineer with a strong background in IC Digital, Mixed Signal, or Analog Design. You excel at customer-facing roles, communicate complex solutions with ease, and thrive in fast-paced, competitive environments. Organized and self-motivated, you build strong relationships and approach challenges with creativity. You hold a relevant Bachelor's (15+ years) or Master's (11+ years) degree, and experience with protocols like SerDes, UCIe, PCIe, DDR, USB, MIPI, or Ethernet is a plus. What You'll Be Doing: * Presenting Synopsys solutions to senior managers and technical stakeholders. * Understanding customer needs and proposing tailored solutions. * Positioning Synopsys in competitive technical situations. * Liaising between technical, marketing, and sales teams. * Driving technical solution strategy and design. * Supporting sales and business unit negotiations. The Impact You Will Have: * Lead customer engagements and ensure alignment with requirements. * Collaborate across teams to deliver winning solutions. * Boost adoption of Synopsys products and platforms. * Provide technical insight for customer chip designs. * Drive customer and business success. * Ensure complex SoC project delivery across regions. What You'll Need: * Expertise in IC design (Digital, Mixed Signal, or Analog). * Experience in customer-facing or sales support roles. * Excellent communication skills. * Strong organizational and project management skills. * Understanding of major semiconductor IP product lines and protocols. Who You Are: A creative problem solver, strategic thinker, and effective collaborator who is passionate about technology and customer success. The Team You'll Be A Part Of: A collaborative group focused on delivering innovative chip design solutions using Synopsys IP, working closely with Sales, R&D, and Marketing. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
$183k-275k yearly 12d ago
IP Applications Engineer
Synopsys, Inc. 4.4
Sunnyvale, CA jobs
Category Engineering Hire Type Employee Job ID 12949 Base Salary Range $157000-$235000 Remote Eligible No Date Posted 09/11/2025 We Are: At Synopsys, we drive innovation in chip design, verification, and IP integration. Our technology powers the Era of Pervasive Intelligence, enabling advances from self-driving cars to learning machines. Join us as we shape the future through continuous technological breakthroughs. You Are: You're a skilled Applications Engineer with 5+ years in ASIC design, simulation, and verification. You excel in IP integration, silicon bring-up, and thrive in fast-paced environments. Your communication and organizational skills help you guide customers and solve complex technical challenges. You're eager to learn new technologies and collaborate for customer success. What You'll Be Doing: * Integrating PCIe/SERDES Interface IP into ASIC SoC systems for customers. * Providing expert support on SoC flows and IP integration. * Resolving technical issues and leading integration reviews. * Supporting silicon bring-up and system validation. * Keeping current with industry standards and applications. * Traveling up to 20% for customer engagements. The Impact You Will Have: * Accelerating customer time-to-market with Synopsys IP integration. * Driving adoption of cutting-edge technologies. * Boosting customer satisfaction through technical expertise. * Supporting industry-leading innovation in silicon chips and software. * Advancing Synopsys' IP portfolio. * Enabling deployment across diverse markets. What You'll Need: * 5+ years' ASIC/SoC design or customer-facing experience. * Strong simulation, verification, and RTL synthesis skills. * Proficiency in IP design and integration flows. * Experience with silicon bring-up preferred. * Knowledge of PCIe, USB, MIPI, HBM DDR, LPDDR protocols. Who You Are: Creative, analytical, and organized. A confident communicator, quick learner, and collaborative problem solver who thrives in team settings. The Team You'll Be A Part Of: Join a collaborative group focused on integrating Synopsys Interface IP into ASIC SoC systems, driving innovation and customer success. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
$157k-235k yearly 12d ago
SerDes Applications Design Engineer
Advanced Micro Devices, Inc. 4.9
San Jose, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The candidate will join a highly visible team of physical interface experts concentrated on SERDES interfaces across AMD products. The team works across a large swath of AMD teams and is instrumental in the delivery of leading-edge, high-speed interface capabilities. THE PERSON: The ideal candidate is self-motivated to work independently as well as collaboratively with engineers across a variety of AMD design, verification, and validation teams. KEY RESPONSIBILITIES: * Excellent working knowledge of RTL-based design flows * Strong knowledge of firmware and hardware interaction * FPGA design and prototyping for various MAC or PCS functionalities * Working knowledge of the entire FPGA or ASIC design process and tool flow * Work with internal and external teams to develop transceivers solutions for various applications * Hands-on experience with various lab equipment for silicon bring-up and validation PREFERRED EXPERIENCE: * Familiar with industry standards such as Ethernet and PCIe is a plus * Strong analytical and problem-solving skills with pronounced attention to details ACADEMIC CREDENTIALS: * BS or MS in Electrical or Computer Engineering preferred LOCATION: San Jose, CA #LI-DP1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$124k-178k yearly est. 45d ago
Application Engineer
Cadence 4.7
Application engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our elite application engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the 2025 World's Best Workplaces for the tenth time! As an integral member of the North America Verification Field Applications Engineering (AE) Team, you will work directly with industry leading semiconductor and system companies to deploy Cadence's market leading emulation and FPGA prototyping platforms, Palladium and Protium. In this customer facing role you will provide the front line technical support in the pre and post-sales process and will work with team members to come up with innovative solutions to address our customers' most challenging problems in emulation and prototyping. As part of the team, you will develop customer specific emulation and prototyping requirements, including advanced acceleration component development, methodology support, and operation and maintenance of Cadence's emulation and prototyping tools and services. You will support technical evaluations and benchmark development for Cadence's market leading tools such as Palladium acceleration and emulation platform and Protium prototyping platform. You will create and conduct technical presentations and product demonstrations for customers. Key Responsibilities: Establish technical credibility and rapport with the customer Work closely with an experienced team to become the go-to expert for technical inquiries and support for emulation and prototyping Become part of a team that provides in-depth technical assistance in collaboration with R&D to help support advanced acceleration/emulation/prototyping flows to secure design wins Champion the customer needs and work with R&D and marketing to develop competitive and creative technical solutions Learn the competitive landscape and continuously work on differentiating Cadence's solutions Write technical product literature such as application notes and technical articles Requirements: Minimum: M.Sc. or B.Sc. degree in Computer Science, Engineering, or related field Good understanding and knowledge of Object Oriented Programming and experience in one such programming language such as C++, Java, Python or Systemverilog Knowledge of Linux/Unix platforms and scripting languages such as Perl, TCL, Python Strong verbal and written communication skills in English Self-motivated and strong teamwork skills Strong problem solving skills Preferred: Lab or internship experience leveraging hands on experience with lab bring up, debug, chipscope and instrument usage FPGA prototyping knowledge including compilation, debug and performance optimization on FPGA prototyping platforms Experience with hardware accelerators and emulators Education or experience in Verilog Systemverilog Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing The annual salary range for California is $74,200 to $137,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.
$74.2k-137.8k yearly Auto-Apply 12d ago
Application Engineer
Cadence Design Systems 4.7
Application engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Join our elite application engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the 2025 World's Best Workplaces™ for the tenth time!As an integral member of the North America Verification Field Applications Engineering (AE) Team, you will work directly with industry leading semiconductor and system companies to deploy Cadence's market leading emulation and FPGA prototyping platforms, Palladium and Protium. In this customer facing role you will provide the front line technical support in the pre and post-sales process and will work with team members to come up with innovative solutions to address our customers' most challenging problems in emulation and prototyping.As part of the team, you will develop customer specific emulation and prototyping requirements, including advanced acceleration component development, methodology support, and operation and maintenance of Cadence's emulation and prototyping tools and services. You will support technical evaluations and benchmark development for Cadence's market leading tools such as Palladium acceleration and emulation platform and Protium prototyping platform. You will create and conduct technical presentations and product demonstrations for customers.Key Responsibilities:Establish technical credibility and rapport with the customer Work closely with an experienced team to become the go-to expert for technical inquiries and support for emulation and prototyping Become part of a team that provides in-depth technical assistance in collaboration with R&D to help support advanced acceleration/emulation/prototyping flows to secure design wins Champion the customer needs and work with R&D and marketing to develop competitive and creative technical solutions Learn the competitive landscape and continuously work on differentiating Cadence's solutions Write technical product literature such as application notes and technical articles Requirements:Minimum:M.Sc. or B.Sc. degree in Computer Science, Engineering, or related field Good understanding and knowledge of Object Oriented Programming and experience in one such programming language such as C++, Java, Python or SystemverilogKnowledge of Linux/Unix platforms and scripting languages such as Perl, TCL, PythonStrong verbal and written communication skills in EnglishSelf-motivated and strong teamwork skills Strong problem solving skills Preferred:Lab or internship experience leveraging hands on experience with lab bring up, debug, chipscope and instrument usage FPGA prototyping knowledge including compilation, debug and performance optimization on FPGA prototyping platforms Experience with hardware accelerators and emulators Education or experience in VerilogSystemverilogKnowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing The annual salary range for California is $74,200 to $137,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.
$74.2k-137.8k yearly Auto-Apply 13d ago
Allegro Package Design Tools Application Engineer, Architect
Cadence 4.7
Application engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Application Engineer Architect for Allegro Package Design Tools - San Jose, CA Cadence offers amazing opportunities for professional growth, regardless of where you are in your career. Our ideal candidate will be energetic, innovative, and enthusiastic about helping customers solve their most challenging design problems. As an Application Engineer you will have the exciting opportunity to work closely with our customers supporting technical campaigns by delivering product demonstrations, knowledge transfer, training, and onsite support. This will involve working with state-of-the-art complex IC packaging of electronics using highly integrated IC package co-design and multi-die chiplet methodologies. Responsibilities include: * Working closely with our customers who are in the Advanced Packaging space * Helping customers to adopt and proliferate our packaging solutions * Consulting with customers to understand their flow requirements and creating solutions that best meet their needs * Conducting technical presentations, technical training, and product demonstrations, including development of customized presentations * Supporting technical evaluations and benchmarks * Collaborating with Sales Management to identify and prioritize opportunities, and to assist in developing winning sales strategies * Working with Cadence Engineering and Marketing to communicate requirements and drive resolution of issues Required Experience/Skills: * BS in Electrical, Mechanical or Computer Engineering * Minimum 8 years of practical experience with Cadence IC packaging tools is required * Must possess expertise in 2.5D/3D-IC packaging technologies * CAD experience in setting up Cadence tools is desirable * Solid verbal and written communication skills * Exceptional problem-solving skills * Ability to work independently and productively in a fast paced and dynamic environment * Interest in learning new technologies * Open to continued personal development to meet the evolving demands of the EDA industry Additional Information: * San Jose office location strongly preferred The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.
$157.5k-292.5k yearly Auto-Apply 58d ago
Physical Design Application Engineer
Synopsys, Inc. 4.4
Sunnyvale, CA jobs
Category Engineering Hire Type Employee Job ID 12583 Base Salary Range $157000-$235000 Remote Eligible No Date Posted 21/08/2025 This position requires access to or use of information, which is subject to export restrictions, including the International Traffic in Arms Regulations (ITAR). All applicants for this position must be "U.S. Persons" within the meaning of the ITAR. "U.S. Persons" include U.S. Citizens, U.S. Lawful Permanent Residents (i.e. 'Green Card Holders'), Political Asylees, Refugees or other protected individuals as defined by 8 U.S.C. 1324b(a)(3). This role is required to work onsite in our Sunnyvale CA location. We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced engineer with a deep understanding of the RTL to GDSII flow. You thrive on solving complex technical issues and enjoy working closely with customers to enhance their experience with cutting-edge technology. With your strong background in synthesis, physical design, and static timing analysis, you excel in diagnosing and resolving technical challenges. You are an excellent communicator, capable of conveying technical concepts clearly and effectively to both technical and non-technical stakeholders. Your scripting skills in Perl, Tcl, and Python, along with your knowledge of CAD automation methods, make you a valuable asset to any team. You are motivated to work collaboratively with internal teams and customers to drive product adoption and satisfaction. What You'll Be Doing: * Providing technical and engineering insight to support and improve the usability, applicability, and adoption of Synopsys products. * Diagnosing, troubleshooting, and resolving complex technical issues on customer installations. * Deploying and training customers on new implementations and capabilities. * Reviewing and acting upon product feedback and solutions performance from customers and other application partners. * Working directly with R&D to develop and implement the technical roadmap, specifications, and validation for improvements and enhancements. * Partnering with customer technical managers and Sales to identify business challenges and develop effective technical solutions for new accounts. The Impact You Will Have: * Enhancing customer satisfaction by ensuring seamless product deployment and support. * Driving product adoption and utilization through effective technical training and support. * Contributing to the technical roadmap and product improvements based on customer feedback. * Supporting the sales team in acquiring new accounts by providing technical expertise. * Improving product performance and reliability through collaborative efforts with R&D. * Strengthening customer relationships by addressing and resolving technical challenges promptly. What You'll Need: * 7+ years of RTL to GDSII full flow experience or knowledge. * In depth experience debugging complex engineering issues related to STA, DRC/DRV and PPA optimization * Exceptional interest and knowledge of Advanced Node & Design methodologies. * Proven aptitude and motivation to work with internal and customer groups. * Excellent verbal and written presentation/communication skills. * Hands-on experience in synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis. * Knowledge of ASIC implementation domains outside of RTL2GDS including RTL coding, Verification, formal checking is a plus. * Good scripting skills (Python, Tcl, Perl); working knowledge of CAD automation methods. Who You Are: * A collaborative team player who thrives in a dynamic environment. * An excellent communicator with the ability to convey complex technical concepts effectively. * A proactive problem-solver with a keen eye for detail. * Customer-focused, with a passion for delivering exceptional service and support. * A continuous learner, always seeking to expand your technical knowledge and skills. The Team You'll Be A Part Of: You will be part of a highly skilled and dedicated team of engineers focused on providing exceptional technical support and solutions to our customers. Our team collaborates closely with R&D, Sales, and Customer Success to drive product innovation, adoption, and satisfaction. We value continuous learning, open communication, and a customer-centric approach in everything we do. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
$157k-235k yearly 12d ago
Physical Design Applications Engineer
Synopsys, Inc. 4.4
Sunnyvale, CA jobs
Category Engineering Hire Type Employee Job ID 13867 Base Salary Range $109000-$163000 Remote Eligible No Date Posted 20/12/2025 At Synopsys, we drive the innovations that shape the way the world connects and computes. Our technology powers cutting-edge silicon in applications from mobile and AI to autonomous systems and advanced computing. Join us to help customers achieve breakthrough performance using our leading EDA tool suite. We are seeking a Physical Design Engineer with strong technical skills in digital implementation and optimization. In this role you will work with engineering teams and customers to deliver solutions that drive timing closure, power and area optimization, and robust RTL-to-GDS flows using Synopsys tools. You Are You are an ASIC/physical design engineer with 2-4 years of hands-on experience in digital implementation flows. You understand full RTL-to-GDS design flows and are comfortable applying state-of-the-art methodologies to achieve timing closure and quality signoff. You have solid scripting skills to automate flows and customize solutions, and you communicate clearly with internal teams and customers to solve complex design challenges. What You'll Be Doing * Execute RTL-to-GDSII digital implementation flows, including logic synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off quality closure. * Work with customers and internal teams to troubleshoot and optimize implementation challenges, propose solutions, and deliver highly-tuned PPA results. * Utilize Synopsys tools such as Fusion Compiler, PrimeTime, and DSO.ai/FusionAI in digital implementation and static timing analysis. * Develop and enhance automation scripts and flows using TCL, Python, Perl, or other scripting languages. * Perform static timing analysis (STA), debug timing violations, and implement ECOs to improve performance and timing closure. * Drive DRC/LVS/Signoff quality closures at advanced technology nodes. * Collaborate with customers, product teams, and research groups to share best practices and feedback to improve tool flows. What You'll Need * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. * 2-4 years of hands-on experience in digital physical design or backend implementation. * Experience with full RTL-to-GDS flows, including place & route methodologies, STA, timing closure, and signoff strategies. * Proficiency with Synopsys tools such as Fusion Compiler, PrimeTime, and familiarity with AI-assisted optimization tools (e.g., DSO.ai/FusionAI) is highly desirable. * Solid scripting skills in TCL, Python, Perl, or equivalent for flow automation. * Strong analytical ability to dissect complex timing, PPA, and design challenges. * Familiarity with unix/linux environments and engineering workflows. * Excellent communication skills and ability to work in collaborative team and customer-facing environments. Who You Are * A proactive self-starter who takes ownership of technical solutions and delivery. * Comfortable interfacing with customers and internal teams to understand requirements and deliver effective outcomes. * Able to adapt to evolving methodologies and rapidly learn emerging tool capabilities in EDA. * Detail-oriented and organized, capable of balancing multiple priorities in a fast-paced environment. The Team You'll Be Part Of Join a dynamic Applications Engineering team dedicated to customer success and powerful EDA solutions. You'll work closely with fellow engineers, researchers, and tool developers to enable high-performance physical design solutions and push the boundaries of what's possible in semiconductor design. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
$109k-163k yearly 1d ago
Senior Physical Design Applications Engineer Returnship
Cadence Design Systems 4.7
Application engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Are you looking to re-enter the workforce as a Physical Design Application Engineer after taking a career break for caregiving? Who is eligible to apply: Please ONLY consider applying if you are a Physical Designer and (IMPORTANT) who has been out of the workforce for caregiving for a period of at least two years and have a minimum of three years of Physical Design work experience. This role is not open to new college grads or interns. Please check our career site for those roles. Cadence is offering an opportunity to qualified candidates who meet our eligibility criteria to participate in a 16-week paid returnship program. You will be entered in a tailored program designed to jump start your skills through training, hands on projects and customer interaction. You will have an opportunity to update your resume, build connections and participate in fun events as you re-enter the workforce. In this program, you will work with best in class EDA tools, collaborate with R&D and the Sales team in a dynamic, innovative environment. Learn processes that are in the forefront of technology, how a company like Cadence works as well as experience how teams solve problems. We are seeking individuals with experience in Digital Synthesis, Place and Route and Signoff Analysis. Where is this returnship located: San Jose, CA What opportunity is offered: Candidates will find opportunities to be in the Application Engineering field spanning across Digital Synthesis, Place and Route and Signoff Analysis. How long is this returnship: 16 weeks Company Description: At Cadence, our core values are more than just words, they are the way we work, laugh, debate, care, question, and innovate together. We are One Cadence-One Team. Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation (EDA) company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Our team's shared passion for solving the world's toughest technical challenges and drive to do meaningful work makes us proud to be part of Cadence. Our unique culture has been recognized on FORTUNE Magazine's 100 Best Companies to Work For list and garnered accolades from the Great Place To Work Institute around the globe. #LI-MA1 The annual salary range for California is $59,500 to $110,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.
$59.5k-110.5k yearly Auto-Apply 60d+ ago