Design Architect jobs at Cadence Design Systems

**Please Note:** **1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)** **2. If you already have a Candidate Account, please Sign-In before you apply.** **:** We are seeking a highly skilled and experienced Chip Architect to lead the definition and documentation of next-generation ARM-based Systems-on-Chip (SoCs). This role is central to bridging the gap between system requirements and silicon implementation, with a strong focus on mixed-signal integration for sensing and touch interfaces within stringent low-power and bandwidth constraints. The ideal candidate must be a hands-on leader capable of driving detailed technical specifications, conducting rigorous power and performance analyses, and serving as the primary architectural liaison across diverse engineering teams. Strong hands-on RTL and scripting knowledge is a must. **Key Responsibilities** + Bandwidth & Power Analysis: Lead comprehensive power and bandwidth analysis for architectural trade-offs. Develop models to predict system performance and power consumption (uW/MHz) and make data-driven decisions to optimize the SoC PPA (Power, Performance, Area). + Detailed Chip Specification: Create and maintain detailed chip specification documentation, including detailed architecture descriptions, relevant block diagrams, timing diagrams, and expected waveforms to guide implementation and verification teams. Working knowledge of AXI, AMBA, Serial interfaces and memory. + ARM-based SoC Architecture: Define and drive the top-level architecture for complex SoCs utilizing various ARM processor cores (Cortex-M, Cortex-A, etc.) and associated system IP. Cross-Functional Interface: Serve as the mandatory interface point and technical lead across multiple disciplines: o Firmware: Ensure the architecture is easily programmable and meets real-time constraints. o Design (Digital/Analog): Provide clear specifications and support during implementation. o Systems: Translate high-level use cases into concrete architectural requirements. o Analog: Define clear interfaces and integration strategies for mixed-signal blocks. o (ADCs, DACs, sensor interfaces). o Mixed-Signal Integration: Architect the seamless integration of mixed- signal components tailored for advanced sensing and touch applications. o Low-Power Leadership: Champion ultra-low-power design methodologies and architectural choices to achieve aggressive battery life targets for portable devices. **Qualifications** o Education: Bachelor's and 12+ years of related experience, or Master's degree in Electrical Engineering, Computer Engineering, or a related field and 10+ years of related experience Experience: System engineering, or a related field, with a proven track record of successful SoC tape-outs. o Technical Expertise: Deep expertise in ARM architectures and system IP (interconnects, memory systems). o Proven experience conducting rigorous power (static/dynamic) and bandwidth analysis for complex systems. o Strong understanding of mixed-signal integration challenges and design principles for sensing/touch applications. o Documentation Skills: Excellent technical writing skills with meticulous attention to detail in creating specifications, diagrams, and documentation. o Soft Skills: Exceptional communication, leadership, and negotiation skills. Must be highly effective at driving consensus and clarity across disparate engineering disciplines. o Work Environment & Location o On-site Requirement: This is a full-time, hands-on role that requires the employee to be present at the office location. There is no remote work option available. o Preferred Location: San Jose, CA. o Secondary Location: Irvine, CA (Candidates willing to relocate or work from our Irvine office may be considered). Other Desired Experience Touch Sensors Mixed Signal SOC architecture FPGA knowledge is a plus Low power Architecture as applied to DSP Technical Customer engagement **Additional Job Description:** **Compensation and Benefits** The annual base salary range for this position is $141,300 - $226,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. **Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.** **If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.** Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library (******************************* and check out our Connected by Broadcom (************************************************************************************************************************************************* series. Follow us on Linked In Broadcom Inc (****************************************** .

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : We are seeking a highly skilled and experienced Chip Architect to lead the definition and documentation of next-generation ARM-based Systems-on-Chip (SoCs). This role is central to bridging the gap between system requirements and silicon implementation, with a strong focus on mixed-signal integration for sensing and touch interfaces within stringent low-power and bandwidth constraints. The ideal candidate must be a hands-on leader capable of driving detailed technical specifications, conducting rigorous power and performance analyses, and serving as the primary architectural liaison across diverse engineering teams. Strong hands-on RTL and scripting knowledge is a must. Key Responsibilities * Bandwidth & Power Analysis: Lead comprehensive power and bandwidth analysis for architectural trade-offs. Develop models to predict system performance and power consumption (uW/MHz) and make data-driven decisions to optimize the SoC PPA (Power, Performance, Area). * Detailed Chip Specification: Create and maintain detailed chip specification documentation, including detailed architecture descriptions, relevant block diagrams, timing diagrams, and expected waveforms to guide implementation and verification teams. Working knowledge of AXI, AMBA, Serial interfaces and memory. * ARM-based SoC Architecture: Define and drive the top-level architecture for complex SoCs utilizing various ARM processor cores (Cortex-M, Cortex-A, etc.) and associated system IP. Cross-Functional Interface: Serve as the mandatory interface point and technical lead across multiple disciplines: o Firmware: Ensure the architecture is easily programmable and meets real-time constraints. o Design (Digital/Analog): Provide clear specifications and support during implementation. o Systems: Translate high-level use cases into concrete architectural requirements. o Analog: Define clear interfaces and integration strategies for mixed-signal blocks. o (ADCs, DACs, sensor interfaces). o Mixed-Signal Integration: Architect the seamless integration of mixed- signal components tailored for advanced sensing and touch applications. o Low-Power Leadership: Champion ultra-low-power design methodologies and architectural choices to achieve aggressive battery life targets for portable devices. Qualifications o Education: Bachelor's and 12+ years of related experience, or Master's degree in Electrical Engineering, Computer Engineering, or a related field and 10+ years of related experience Experience: System engineering, or a related field, with a proven track record of successful SoC tape-outs. o Technical Expertise: Deep expertise in ARM architectures and system IP (interconnects, memory systems). o Proven experience conducting rigorous power (static/dynamic) and bandwidth analysis for complex systems. o Strong understanding of mixed-signal integration challenges and design principles for sensing/touch applications. o Documentation Skills: Excellent technical writing skills with meticulous attention to detail in creating specifications, diagrams, and documentation. o Soft Skills: Exceptional communication, leadership, and negotiation skills. Must be highly effective at driving consensus and clarity across disparate engineering disciplines. o Work Environment & Location o On-site Requirement: This is a full-time, hands-on role that requires the employee to be present at the office location. There is no remote work option available. o Preferred Location: San Jose, CA. o Secondary Location: Irvine, CA (Candidates willing to relocate or work from our Irvine office may be considered). Other Desired Experience Touch Sensors Mixed Signal SOC architecture FPGA knowledge is a plus Low power Architecture as applied to DSP Technical Customer engagement Additional Job Description: Compensation and Benefits The annual base salary range for this position is $141,300 - $226,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : We are seeking a highly skilled and experienced Chip Architect to lead the definition and documentation of next-generation ARM-based Systems-on-Chip (SoCs). This role is central to bridging the gap between system requirements and silicon implementation, with a strong focus on mixed-signal integration for sensing and touch interfaces within stringent low-power and bandwidth constraints. The ideal candidate must be a hands-on leader capable of driving detailed technical specifications, conducting rigorous power and performance analyses, and serving as the primary architectural liaison across diverse engineering teams. Strong hands-on RTL and scripting knowledge is a must. Key Responsibilities Bandwidth & Power Analysis: Lead comprehensive power and bandwidth analysis for architectural trade-offs. Develop models to predict system performance and power consumption (uW/MHz) and make data-driven decisions to optimize the SoC PPA (Power, Performance, Area). Detailed Chip Specification: Create and maintain detailed chip specification documentation, including detailed architecture descriptions, relevant block diagrams, timing diagrams, and expected waveforms to guide implementation and verification teams. Working knowledge of AXI, AMBA, Serial interfaces and memory. ARM-based SoC Architecture: Define and drive the top-level architecture for complex SoCs utilizing various ARM processor cores (Cortex-M, Cortex-A, etc.) and associated system IP. Cross-Functional Interface: Serve as the mandatory interface point and technical lead across multiple disciplines: o Firmware: Ensure the architecture is easily programmable and meets real-time constraints. o Design (Digital/Analog): Provide clear specifications and support during implementation. o Systems: Translate high-level use cases into concrete architectural requirements. o Analog: Define clear interfaces and integration strategies for mixed-signal blocks. o (ADCs, DACs, sensor interfaces). o Mixed-Signal Integration: Architect the seamless integration of mixed- signal components tailored for advanced sensing and touch applications. o Low-Power Leadership: Champion ultra-low-power design methodologies and architectural choices to achieve aggressive battery life targets for portable devices. Qualifications o Education: Bachelor's and 12+ years of related experience, or Master's degree in Electrical Engineering, Computer Engineering, or a related field and 10+ years of related experience Experience: System engineering, or a related field, with a proven track record of successful SoC tape-outs. o Technical Expertise: Deep expertise in ARM architectures and system IP (interconnects, memory systems). o Proven experience conducting rigorous power (static/dynamic) and bandwidth analysis for complex systems. o Strong understanding of mixed-signal integration challenges and design principles for sensing/touch applications. o Documentation Skills: Excellent technical writing skills with meticulous attention to detail in creating specifications, diagrams, and documentation. o Soft Skills: Exceptional communication, leadership, and negotiation skills. Must be highly effective at driving consensus and clarity across disparate engineering disciplines. o Work Environment & Location o On-site Requirement: This is a full-time, hands-on role that requires the employee to be present at the office location. There is no remote work option available. o Preferred Location: San Jose, CA. o Secondary Location: Irvine, CA (Candidates willing to relocate or work from our Irvine office may be considered). Other Desired Experience Touch Sensors Mixed Signal SOC architecture FPGA knowledge is a plus Low power Architecture as applied to DSP Technical Customer engagement Additional Job Description: Compensation and Benefits The annual base salary range for this position is $141,300 - $226,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : We are seeking a highly skilled and experienced Chip Architect to lead the definition and documentation of next-generation ARM-based Systems-on-Chip (SoCs). This role is central to bridging the gap between system requirements and silicon implementation, with a strong focus on mixed-signal integration for sensing and touch interfaces within stringent low-power and bandwidth constraints. The ideal candidate must be a hands-on leader capable of driving detailed technical specifications, conducting rigorous power and performance analyses, and serving as the primary architectural liaison across diverse engineering teams. Strong hands-on RTL and scripting knowledge is a must. Key Responsibilities * Bandwidth & Power Analysis: Lead comprehensive power and bandwidth analysis for architectural trade-offs. Develop models to predict system performance and power consumption (uW/MHz) and make data-driven decisions to optimize the SoC PPA (Power, Performance, Area). * Detailed Chip Specification: Create and maintain detailed chip specification documentation, including detailed architecture descriptions, relevant block diagrams, timing diagrams, and expected waveforms to guide implementation and verification teams. Working knowledge of AXI, AMBA, Serial interfaces and memory. * ARM-based SoC Architecture: Define and drive the top-level architecture for complex SoCs utilizing various ARM processor cores (Cortex-M, Cortex-A, etc.) and associated system IP. Cross-Functional Interface: Serve as the mandatory interface point and technical lead across multiple disciplines: o Firmware: Ensure the architecture is easily programmable and meets real-time constraints. o Design (Digital/Analog): Provide clear specifications and support during implementation. o Systems: Translate high-level use cases into concrete architectural requirements. o Analog: Define clear interfaces and integration strategies for mixed-signal blocks. o (ADCs, DACs, sensor interfaces). o Mixed-Signal Integration: Architect the seamless integration of mixed- signal components tailored for advanced sensing and touch applications. o Low-Power Leadership: Champion ultra-low-power design methodologies and architectural choices to achieve aggressive battery life targets for portable devices. Qualifications o Education: Bachelor's and 12+ years of related experience, or Master's degree in Electrical Engineering, Computer Engineering, or a related field and 10+ years of related experience Experience: System engineering, or a related field, with a proven track record of successful SoC tape-outs. o Technical Expertise: Deep expertise in ARM architectures and system IP (interconnects, memory systems). o Proven experience conducting rigorous power (static/dynamic) and bandwidth analysis for complex systems. o Strong understanding of mixed-signal integration challenges and design principles for sensing/touch applications. o Documentation Skills: Excellent technical writing skills with meticulous attention to detail in creating specifications, diagrams, and documentation. o Soft Skills: Exceptional communication, leadership, and negotiation skills. Must be highly effective at driving consensus and clarity across disparate engineering disciplines. o Work Environment & Location o On-site Requirement: This is a full-time, hands-on role that requires the employee to be present at the office location. There is no remote work option available. o Preferred Location: San Jose, CA. o Secondary Location: Irvine, CA (Candidates willing to relocate or work from our Irvine office may be considered). Other Desired Experience Touch Sensors Mixed Signal SOC architecture FPGA knowledge is a plus Low power Architecture as applied to DSP Technical Customer engagement Additional Job Description: Compensation and Benefits The annual base salary range for this position is $141,300 - $226,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Are you a problem solver looking for a hands-on internship position with a market-leading company that will help develop your career and reward you intellectually and professionally? Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at ************** and on LinkedIn and Twitter (X). At ADI, you will learn from the brightest minds who are here to help you grow and succeed. During your internship, you will make an impact through work on meaningful projects alongside a team of experts. Collaborating with colleagues in an environment of respect and responsibility, you will create connections that will become a part of your professional network. ADI's culture values aligned goals, work-life balance, continuous and life-long learning opportunities, and shared rewards. The internship program features various lunch-and-learn topics and social events with other interns and full-time employees. At ADI, our goal is to develop our interns so they are the first to be considered for full-time roles. Apply now for the opportunity to grow your career and help innovate ahead of what's possible. The Architectural Design Team seeking a motivated, experienced Design Intern to provide support to our Facilities located at ADI's Rio Robles office. The candidate will have the opportunity to support a small-sized architectural design team that includes both individual contributors and managers. The team culture is highly collaborative and promotes open communication, allowing for a positive and inclusive work environment. Being a part of this team offers unique opportunities to work on diverse projects and contribute to the design process, ultimately helping to improve facilities on site. Responsibilities include, but not limited to: Assist in the creation of architectural drawings and documentation Conduct on-site verification and measurement Prepare and present design proposals Ensure compliance with building codes and regulations Maintain the material library Minimum qualifications Basic CAD drafting skills Proficiency in MS Office, Word, Excel and Outlook Basic proficiency in 3D Modeling software (Sketchup) Ability to communicate both verbally and in writing. Preferred qualifications Currently enrolled in an architecture or interior design program Previous internship in an architectural or interiors design firm preferred Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. Job Req Type: Internship/CooperativeRequired Travel: NoThe expected wage range for a new hire into this position is $25 to $46. Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE PERSON: This role is ideal for a strategic thinker who thrives in solving large-scale technical challenges without losing sight of execution realities. You are: * A visionary and a builder - someone who can define and improve DV frameworks that will last through generations of silicon. * A mentor and a unifier - guiding diverse teams across geographies and backgrounds, aligning them to a shared DV mission. * A strong communicator who brings clarity and confidence when navigating ambiguity or resolving conflicting technical perspectives. * Comfortable influencing without authority and leading through technical credibility * Motivated by impact - not just doing DV but transforming how it's done at scale. THE ROLE: At AMD, we believe in "We before Me" - and this role exemplifies that value. Success here means making those around you better through leadership, knowledge sharing, and collaboration. * We are building high-performance computing technologies that are powering the future - from gaming and AI to hyperscale data centers and beyond. To help us continue this trajectory of excellence and innovation, we're looking for a CPU Design Verification Architect to drive the strategic vision of DV for our next-generation CPU cores. * This is a technical leadership position focused on methodology design, infrastructure planning, and team enablement. You will set the standard for quality, coverage, and scalability across a wide array of processor verification efforts. * If you have multiple successful tape-outs, a vision for world-class DV strategy, and the ability to orchestrate technical teams toward measurable impact, this role is your opportunity to shape the core of AMD's processor roadmap. KEY RESPONSIBILITIES: * Define and own the overall DV architecture for high-performance CPU cores, ensuring scalability across variants and generations. * Collaborate closely with design, microarchitecture, emulation, and verification leads/architects to build aligned verification strategies. * Lead the evaluation and enhancement of AMD's DV infrastructure and methodologies, to drive RTL quality and project intercept. * Provide technical mentorship and strategic direction to DV leads and engineers across global AMD sites. * Anticipate architectural and verification risks early and drive systemic solutions before they impact delivery. * Influence cross-functional decision-making through a blend of technical insight and collaborative communication. * Champion long-term DV innovation by staying current on AI/ML techniques, formal verification, and emulation strategies - and knowing when to integrate them into project flow. PREFERRED EXPERIENCE: * Expertise in Design Verification with an emphasis on CPU architecture and core-level verification. * Proven tape-out experience across multiple CPU or processor projects. * Strong grasp of DV methodologies: coverage-driven verification, formal, and infrastructure strategy. * Solid understanding of computer architecture fundamentals: pipelines, caching, coherency, load/store, execution units, etc. * Strong documentation, planning, and cross-functional coordination skills. * Familiarity with x86 or ARM CPU cores. NICE TO HAVE: * Experience with formal verification or ML/AI-enhanced DV tools. * Track record of leading cross-site DV architecture initiatives in high-performance compute environments. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Santa Clara #LI-DC1 #HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Category Engineering Hire Type Employee Job ID 13350 Base Salary Range $209000-$313000 Remote Eligible No Date Posted 17/11/2025 We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced IC physical design expert, with strong leadership in digital implementation and signoff for complex, high-speed mixed-signal subsystems. You thrive in collaborative environments, can manage both local and remote teams, and have a proven track record of driving projects to tapeout. You're hands-on, detail-oriented, and passionate about optimizing performance, power, and area. Your communication skills and technical insight make you a go-to resource for cross-functional teams. What You'll Be Doing: * Technically lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff. * Guide signoff quality timing constraints development and qualification for critical Subsystem designs with hundreds of clocks. * Drive PNR flow and methodology for timing critical muti-million deep sub-micro designs flat/hierarchical digital implementation. * Handson expertise in all aspects of flat, hierarchical PNR implementation tasks like synthesis, floorplanning, design partitioning, DFT, low power/UPF based implementation, timing constraints, clock tree synthesis, routing and optimization, extraction, timing signoff, signal integrity, physical verification, Power & IR drop signoff to debug and resolve critical implementation bottlenecks. * Requires close interaction and collaborative teamwork with multiple functional groups front end, analog, PM/PEMs. * Drive RTL, design partitioning, timing constraints related feedback to Frond-end team for data path optimization, clock & reset architecture improvements for enabling high speed timing closure, PPA improvements. The Impact You Will Have: * Deliver signoff-quality, high-performance silicon solutions. * Mentor and develop engineering teams. * Drive process improvements and technical innovation. * Enhance Synopsys' leadership in high-speed IP. * Facilitate successful cross-team collaboration. * Enable next-generation chip architectures. What You'll Need: * MS in Electrical Engineering; 10+ years in physical design, static timing analysis. * Must have hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs. * Must have experience in leading and managing local, remote implementation teams. * Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects. * Strong scripting and software skills. Who You Are: * Inclusive leader and effective communicator. * Innovative, collaborative, and quality-driven. * Thrives in dynamic environments. The Team You'll Be A Part Of: Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process. #LI-NK4 At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a "team first" organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for. Responsibilities & Skills Lattice is looking for experts in the field of Synthesis, Place and Route to work on their next-gen FPGA Software compiler. The candidate will drive the research, design and development of different aspects of Lattice Tools flow, with the focus on improving Fmax, Area, Runtime and new features development. The candidate will also participate in defining next-gen FPGA devices, work on customer support and align with Marketing and Field expectations. Responsibilities: * Develop new algorithms for Synthesis, Place and Route * Architect software tool flow to achieve quality robustness and efficiency * Optimize existing tools to achieve better Fmax, Area, Runtime and Memory usage * Collaborate with cross functional teams to define next gen devices and technology * Work with Sales, Marketing and Field Applications team to support innovation and customer adoption of our products * Assist in management of customer escalations and support tickets Required Skills * MS/PhD in Electrical Engineering or Computer Science or Computer Engineering * 15+ years of industry experience in developing EDA tools * Strong background and experience in data structures and algorithms * Experience of logic design and EDA software is a must * Proficient with C++ * Knowledge in Verilog/VHDL is a plus * Experience of FPGA tool development is a plus * Experience of multi-processing development is a plus * Strong written and verbal communication skills, and collaboration skill * Must be able to work independently and also in a team environment * Strong analytical and problem solving skills * Ability to work in a fast paced environment, prioritize appropriately and manage competing priorities Benefits: The base pay for this role is between $247,000 to $309,000 per year. In addition to base salary, we offer an incentive plan, bonus, and new hire equity for a competitive total compensation package. Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit ******************** You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : The Platform Architect position in Broadcom's DCSG division is primarily responsible for driving the Standard and AI Server architecture using DCSG's industry leading RAID and PCIe switch products. This will specifically involve working with a team of board, hardware and firmware architects and developers to ensure our solutions are robust and meet the needs of the changing AI and standard servers. The role will require involvement in near term production solutions as well as strategic long-term research and investigations of new architecture involving DCSG's storage controller and Switch products. Architecture in the DCSG division takes very hands on approach, with the expectation of close work with our development teams, including Board, FW and IC. Skills Preferred * 12 years or more experience in hardware development, with a focus on Standard and AI server architecture for at least 5 years. * Skills in leading debugging complex issues related to hardware and software interaction and system level performance issues * In depth understanding of system level power, cooling aspects for boards, rack based servers * Strong communications skills, both verbal and written, which enable communication both up and down the chain of command. Ability to present complex problems and solutions in an understandable fashion to executive management, while also being able to have very low level technical discussions with architecture peers and development teams. Ability to clearly document solutions at an architectural level also required. * Bachelor's in Electrical or Computer Science Engineering, Master's preferred Responsibilities * Engagement with key customers in order understand System architecture issues and or future directions utilizing our Switch and Storage products * Perform technical investigations and/or debug within our current production solutions in order to optimize performance, evaluate future product features, or resolve current product issues. * Present on architectural related topics to executive management in a clear and concise manner * Participate and contribute in industry standard workgroups to enable future product definition and goals * Support of development organizations in order to aid in resolution of complex issues or optimization of code for performance or efficiency Additional Job Description: Compensation and Benefits The annual base salary range for this position is $127,100 - $203,400. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

**Please Note:** **1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)** **2. If you already have a Candidate Account, please Sign-In before you apply.** **:** The vKS Application Engineering team is responsible for enabling enterprise success with vSphere Kubernetes Service (vKS) as part of VMware Cloud Foundation (VCF). Our mission is to accelerate adoption of vKS as the enterprise-grade Kubernetes platform for modern applications in private cloud. As a vKS Application Engineer, you will be on the front lines with enterprise customers, driving the successful adoption of vSphere Kubernetes Service (vKS) on VMware Cloud Foundation (VCF). This is a hands-on, customer-facing role focused on designing and validating solutions, running proof-of-concepts, and guiding customers through their modernization journey. **Key Accountabilities** + Act as a trusted advisor for enterprise customers, guiding them through the design, validation, and deployment of vKS solutions on VCF. + Collaborate closely with field account teams to align solution architecture with customer priorities and drive successful engagement outcomes. + Lead technical discovery sessions, workshops, and proof-of-concepts to validate vKS architectures and demonstrate business value. + Partner with sales to jointly develop customer proposals that address modernization goals, workload placement, and operational transformation. + Provide prescriptive guidance on Kubernetes adoption, DevOps/CI-CD integration, and enterprise requirements such as scalability, security, and disaster recovery. + Build and share reference architectures, deployment patterns, and technical assets to accelerate customer adoption of vKS. + Deliver clear, compelling technical presentations to diverse audiences, from architects to executive decision makers. + Stay current on industry trends, competitor offerings, and evolving enterprise requirements to position vKS effectively. + Collaborate with product management and engineering to provide field feedback that influences roadmap direction. **Required Skills & Experience** + Experience in application engineering or technical sales for enterprise IT, cloud, or application platforms. + Strong expertise in Kubernetes, containers, and VMware Cloud Foundation (vSphere, vSAN, NSX as foundation). + 8-10+ years in technology-related roles, with depth in enterprise IT architecture, application modernization, or cloud-native platforms. + Demonstrated success working directly with enterprise customers to deliver technical solutions and drive platform adoption. + Excellent communication, storytelling, and presentation skills with the ability to engage both technical and business leaders. + Strong collaboration skills, able to work hand-in-hand with sales teams to advance customer opportunities. + Proven ability to identify challenges, design solutions, and articulate value in business terms. + Enthusiastic self-starter with curiosity, drive, and the ability to thrive in dynamic environments. + Ability to travel up to 50% of the time **Qualifications** + Bachelor's Degree or Master's Degree plus 12+/10+ in Computer Science, Engineering, Mathematics, or related field; or equivalent experience. + Deep knowledge of VMware Cloud Foundation and Kubernetes platforms. + Certifications in cloud-native or public cloud technologies (AWS, Azure, GCP, Red Hat OpenShift, etc.) are highly desirable. **Additional Job Description:** **Compensation and Benefits** The annual base salary range for this position is $118,800 - $171,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. **Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.** **If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.** Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library (******************************* and check out our Connected by Broadcom (************************************************************************************************************************************************* series. Follow us on Linked In Broadcom Inc (****************************************** .

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. Principal SoC Architect, Discrete GPU SoCs - 113062 The Role: AMD is looking for an outstanding technical contributor to help optimize performance of next-generation Discrete GPU SoCs. As a passionate and dedicated Performance Architect in the SOC Architecture Team, you will optimize SOC performance by identifying opportunities across all parts of system architecture, spanning the application and related frameworks, driver, GPU core, memory & I/O subsystems. You will use performance models for micro architecture trade-offs, collect and analyze performance profiling data and traces to isolate performance bottlenecks, and share the insights to help drive features into the next generation of GPUs. The ideal candidate is expected to be well informed on latest trends in GPU and CPU Systems, and be able to quickly ascertain, in a data-driven manner, how next generation GPUs and platforms should be engineered to support those needs. Key Responsibilities: SoC level Performance analysis for multiple SoCs in Discrete GPU product line. Has technical time horizon of generally 6 to 18 months. Explore and evaluate architectural design choices in Fabrics, Caches, and IPs in the SoC. Work closely with other HW and SW architects to understand the architecture, the workloads and to propose solutions to improve/enhance performance with given SoC/IP and markets. Architectural modeling (as needed), performance triage, deeper analysis, identifying bottlenecks and solutions for performance improvement. Proposing, communicating, and implementing solutions to issues. Participate in new workload definition and/or workload optimizations. Deep engagement with Performance modelling team for new features development, developing performance analysis plan in Architecture phase, analyzing results and model correlation. Work closely with Design and Performance Verification teams to set Performance KPIs, Performance Verification test plan reviews and triaging Performance issues identified by them. Work closely with Post-Si teams for correlation of Pre-Silicon models and assumptions, and support them for Performance validation issues. Position Requirements Exceptional foundation in systems architecture, cutting across CPU or GPU, memory, storage and I/O subsystems Experience in using Performance Modeling and Simulation Tools for CPUs, GPUs or SoC components at different abstraction levels (Functional, TLM or Cycle Accurate) Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads Experience with Performance monitoring tools such as Hardware performance counters and Visualization tools Excellent communication skills (verbal, written, and presentation) Exposure to GPU performance benchmarks and workloads are a plus Proficiency in Unix, C++, and Scripting languages such as Python is a plus More than 8 years relevant industry experience ACADEMIC CREDENTIALS: Bachelor, Master or PhD Degree, emphasis in Electrical or Computer Engineering, Computer Architecture, or Computer Science with SoC/IP performance studies. Requisition Number: 113062 Country: United States State: California City: Santa Clara Job Function: Design AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Join our Data Center Platform Architecture Engineering team as a Lead Principal Power Architect, where you will influence the next generation of GPU platform power delivery. In this high-impact position, you will define end-to-end power architecture features with a focus on efficiency, scalability, and system-level performance. You will work closely with cross-functional partners across silicon, system, mechanical, and thermal engineering to bring innovative power architectures from concept to production. This team prioritizes continuous technical innovation, collaboration, and career development while delivering industry-leading technologies to market. THE PERSON: You are a strategic thinker with deep power electronics engineering expertise and a passion for solving complex architectural challenges. You excel in fast-paced, highly visible environments and bring a balanced mix of technical depth, analytical rigor, and cross-functional communication. You are proactive, detail-oriented, and skilled at driving clarity across ambiguous or complex technical problems. Your ability to model, prototype, debug, and influence system architecture makes you a key contributor to the platform's success. KEY RESPONSIBILITIES: * Architectural Definition & Modeling: Define and develop GPU end-to-end platform power delivery architecture features with emphasis on power efficiency. * Build advanced power and performance models to evaluate architectural and system-level trade-offs. * Technical Innovation: Drive innovation across architecture development, methodology enhancements, and cross-functional technical initiatives that advance platform capabilities. * Prototyping & Validation: Support the development of prototype proof-of-concepts. Analyze and resolve complex issues throughout the architectural and product development lifecycle. * System Debug: Lead debugging efforts during bring-up, validation, and production phases of SOC programs. * Cross-Functional Collaboration: Partner closely with System Architects, Silicon/ASIC Design, PCB Design, Mechanical Engineering, Thermal Engineering, and Validation teams to ensure alignment on power architecture goals and seamless integration. * Specification & Documentation: Develop clear system specifications, architecture documents, and implementation guidelines for engineering teams. PREFERRED EXPERIENCE: * Experience in GPU/CPU architecture with strong emphasis on power delivery and energy efficiency * Proficiency with high-power GPU/CPU architecture topologies (Buck, Boost, Buck-Boost, LLC, Full Bridge, Half-Bridge, etc.) * Strong understanding of modeling tools and methodologies (Simplis, Cadence, HSPICE) * Expertise in debug techniques and methodologies * Proficient with common lab equipment and hands-on board/platform-level debug, including delivery, sequencing, analysis, and optimization * Deep knowledge of system architecture, technical debug, and validation strategies * Experience with end-to-end power architecture definition in large-scale platforms * Familiarity with system-level co-design considerations (thermal management, mechanical constraints, signal integrity) * Strong analytical and problem-solving skills with exceptional attention to detail * Self-starter with the ability to independently drive initiatives to completion ACADEMIC CREDENTIALS: * Master's or Ph.D. in Electrical Engineering, with a focus on power electronics or power integrity (preferred) Location could also be in Austin, TX, Secaucus, NJ, Seattle or Bellevue, WA, or Longmont, CO This role is not eligible for visa sponsorship #LI-TL1 #HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. GPU ML Performance Architect The Role: AMD is looking for an individual to join GPU architecture team to work on next generation GPU architecture for machine learning acceleration. The job includes architecture modeling and developing Deep Learning GPU kernels for architecture exploration and performance projection. The Person: The successful person will be an experienced GPU architect or GPU-compute/graphics programmer with an eye towards hardware-aware performance optimizations. Key Responsibilities: The ideal candidate will be responsible for architecture modeling and writing high performance GPU kernels for Machine Learning applications to run on AMD's next generation GPU. They will be porting and optimizing algorithms for new GPU architecture Implement new architecture ideas then analyze performance impact Perform code reviews, authoring detailed documentation related to their work. They will play a key role in all phases of GPU architecture development including architecture feature analysis, performance projection, and performance analysis across different platforms. Preferred Experience: Strong programming skills in C/C++ Extensive experience with machine learning Experience on GPU programing Strong understanding of GPU architecture Good teamwork and interpersonal skills required Ability to work independently and within complementary teams Demonstrate flexibility, strong motivation and a proven track record of meeting results-oriented deadlines. Knowledge of Parallel-Computing, GPUs, and 3D graphics Familiarity with deep neural network machine learning technologies and modern machine learning programming frameworks Academic Credentials: Masters, PhD or 5 years industry experience in relevant field (CS, EE, CE) Location: Santa Clara, CA; Orlando, Florida #LI-PA1 Requisition Number: 112841 Country: United States State: California City: Santa Clara Job Function: Design AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ Power Management Architect The Role: Drive the definition, tradeoff studies, protyping, implementation and verification of the Power Management Architecture features and algorithms for Radeon gaming and datacenter GPUs. Collaborate closely with a wide array of engineering disciplines to create leadership products that delight our customers. The Person: This is an experienced engineer who brings a deep understanding of SoC and Platform architecture, Power Management concepts and algorithms, and a passion to drive perf/watt and perf/$ optimizations for worldclass GPUs. Previous experience in the areas of voltage margin optimization, reliability and yield management, statistical analysis of silicon manufacturing/test data will be a bonus. Key Responsibilities: Drive Power Management advances and multi-generational roadmap in the area of voltage optimization, with an eye on silicon reliability and yeild, to maximize power and cost constrained performance for Radeon graphics platforms Take ownership for developing and driving PM features from concept through product launch for a family of SoC devices with varying configurations and target market segments Work cross functionally with Software, Firmware, SOC, IP, Platform, Technology, Product teams through every stage of product development, evangelize for power efficiency, lead broad forums and drive product definition alignment Work with product teams to understand the Perf/Power/Cost requirements Drive power management feature definition per SoC program Develop system level models, analyze return-on-investment and evaluate trade-offs Document specifications Guide power management feature implementation, verification, emulation and post-silicon validation in an engineering resource efficient and scalable manner Coach and mentor other engineers as a technical leader Preferred Experience: Proven experience with GPU or CPU power architecture, PPA tradeoffs, power management algorithms, embedded microcontroller firmware, hardware test and verification environments Solid background in electrical circuits, VLSI and circuit design fundamentals Familiarity with ASIC/SoC Design cycles and methodologies including RTL, Verification, Emulation, Physical Design and post-si validation Background in prototyping and proof of concept of new complex architectures and algorithms in hardware/software/firmware using physical and/or emulation platforms will be a plus Programming skills in C/C++, scripting with Perl or Python Previous experience in the areas of voltage margin optimization, reliability and yield management, statistical analysis of silicon manufacturing/test data will be a major differentiator Ability to work cross functionally with HW/SW and Pre/Post Silicon teams, lead by influence and strong communication skills Academic Credentials: Bachelor's Degree in Electrical Engineering, Computer Engineering, or another relevant field. Masters or Ph.D. preferred Location: Santa Clara, CA - Austin, TX - Markham, Ontario #LI-SW2 Requisition Number: 150682 Country: United States State: California City: Santa Clara Job Function: Product Engineering Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for a GPU Machine Learning Architect to join GPU architecture team developing Deep Learning Architecture and GPU kernels for architecture exploration, development and performance verification THE PERSON: The successful person will be an experienced GPU-compute or graphics hardware developer and programmer with an eye towards hardware/software-aware performance implementations and optimizations. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Good teamwork and interpersonal skills required. Ability to work independently and within complementary teams. Demonstrate flexibility, strong motivation and a proven track record of meeting results-oriented deadlines. KEY RESPONSIBILITIES: * They will play a key role in all phases of GPU architecture development including architecture feature development and analysis, performance projection, and performance analysis across different platforms. * The ideal candidate will be responsible for writing high performance GPU kernels for Machine Learning applications to run on AMD's next generation GPU.\ * They will be porting and optimizing algorithms for new GPU architecture, perform code reviews, authoring detailed documentation related to their work. PREFERRED EXPERIENCE: * Strong programming skills in C/C++, HIP, and CUDA * Extensive experience with machine learning * Experience with GPU ML runtimes and compilers * Experience using version control software such as Git * Strong understanding of GPU architecture * Knowledge of Parallel-Computing, GPUs, and 3D graphics * Familiarity with deep neural network machine learning technologies and modern machine learning programming frameworks ACADEMIC CREDENTIALS: * PhD in computer architecture/Electrical Engineering preferred. This role is not eligible for Visa sponsorship. #LI-BM1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

We're in an unbelievably exciting area of tech and are fundamentally reshaping the data storage industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team in the industry. This type of work-work that changes the world-is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE: Portworx by Pure Storage is the leading global solution for unlocking the potential of Kubernetes by unlocking the power of data at enterprise scale. Portworx is a cloud native platform that enterprises depend on to reduce the cost and complexity of rapidly deploying containerized applications across multiple clouds and on-prem environments. By providing a single standard that works across the environment, we reduce the operating cost of kubernetes, unlock more use cases, respond and pivot to changes due to economic, regulatory and/or business impacts and make it easier to modernize applications, delight developers, and deliver innovation. Via Portworx, you can manage any database or stateful service on any infrastructure using any container scheduler. You get a single data management layer for all of your stateful services, no matter where they run. And we thrive in multi-cloud environments. We are looking for Kubernetes experts to help our team capture this massive and rapidly growing market opportunity. This architect role will serve as the vanguard of the “Kubernetes Everywhere” movement. There's no safe harbor here for those that can't, don't, or won't. There's also no room for those that put “I” ahead of “We”. We are customer first, we lead with integrity, and recognize that unlocking achievement requires engagement across the full spectrum of co-selling partners. We are builders, creators, and helping define the next generation of the world's best modern data platform at Pure. WHAT YOU'LL DO: The Pure Storage Cloud Architecture team is responsible for providing pre-sales deep technical and business expertise to customers who want to run stateful applications in containers and automate “Day 2” data management workflows. WHAT YOU BRING: 5+ years experience as a customer facing senior-level technical architect. Charismatic, confident, and likable self-starter with a track record of success on stage, in the spotlight, and with customers. Team oriented leader that is able to coach and drive desired behavior through influence rather than title. 5+ years of Linux Administration and/or Linux development experience with an industry recognized administration-level or higher certification. 3+ years of Kubernetes Administration experience and a KCNA (Kubernetes and Cloud Native Associate) or above certification. Certification-level fluency in OpenShift, Rancher, or other Kubernetes orchestration environment. Certification-level fluency in Cloud IaaS environments such as VMware, AWS, Azure, Google Cloud Platform and OpenStack. Certification-level fluency with DevOps concepts and hands-on experience with associated tools, such as; Ansible, Terraform, Docker, and CI/CD pipeline applications. Certification-level fluency in data engineering, big data, and database operations, delivery and operational services. Demonstrable understanding of data platform technologies as they relate to highly available business applications on-prem, hybrid, and in the cloud Demonstrable understanding of the enterprise application development lifecycle and container platforms' effect on it. Demonstrable ability to see and present ‘the big picture' e.g. thought leadership, offer solutions to improve upon it, and challenge the status quo when it is not in alignment with or in the best interest of desired customer outcomes. Demonstrable ability to distill complex problems into a simplified vision that drives customer interest in Pure technologies Strong bias for continuous improvement both personally and professionally. Ability to travel as needed regionally (up-to 60%) #LI-Remote #LI-JL4 Salary ranges are determined based on role, level and location. For positions open to candidates in multiple geographical locations, the base salary range is reflective of the labor market across the applicable locations. This role may be eligible for incentive pay and/or equity. There is no application deadline and we accept applications on an ongoing basis until the job is filled. The annual base salary range is: $151,900-$249,900 USD WHAT YOU CAN EXPECT FROM US: Pure Innovation: We celebrate those who think critically, like a challenge and aspire to be trailblazers. Pure Growth: We give you the space and support to grow along with us and to contribute to something meaningful. We have been Named Fortune's Best Large Workplaces in the Bay Area™, Fortune's Best Workplaces for Millennials™ and certified as a Great Place to Work ! Pure Team: We build each other up and set aside ego for the greater good. And because we understand the value of bringing your full and best self to work, we offer a variety of perks to manage a healthy balance, including flexible time off, wellness resources and company-sponsored team events. Check out purebenefits.com for more information. ACCOMMODATIONS AND ACCESSIBILITY: Candidates with disabilities may request accommodations for all aspects of our hiring process. For more on this, contact us at ********************** if you're invited to an interview. OUR COMMITMENT TO A STRONG AND INCLUSIVE TEAM: We're forging a future where everyone finds their rightful place and where every voice matters. Where uniqueness isn't just accepted but embraced. That's why we are committed to fostering the growth and development of every person, cultivating a sense of community through our Employee Resource Groups and advocating for inclusive leadership. Pure is proud to be an equal opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or any other characteristic legally protected by the laws of the jurisdiction in which you are being considered for hire. JOIN US AND BRING YOUR BEST. BRING YOUR BOLD. BRING YOUR FLASH.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : The vKS Application Engineering team is responsible for enabling enterprise success with vSphere Kubernetes Service (vKS) as part of VMware Cloud Foundation (VCF). Our mission is to accelerate adoption of vKS as the enterprise-grade Kubernetes platform for modern applications in private cloud. As a vKS Application Engineer, you will be on the front lines with enterprise customers, driving the successful adoption of vSphere Kubernetes Service (vKS) on VMware Cloud Foundation (VCF). This is a hands-on, customer-facing role focused on designing and validating solutions, running proof-of-concepts, and guiding customers through their modernization journey. Key Accountabilities Act as a trusted advisor for enterprise customers, guiding them through the design, validation, and deployment of vKS solutions on VCF. Collaborate closely with field account teams to align solution architecture with customer priorities and drive successful engagement outcomes. Lead technical discovery sessions, workshops, and proof-of-concepts to validate vKS architectures and demonstrate business value. Partner with sales to jointly develop customer proposals that address modernization goals, workload placement, and operational transformation. Provide prescriptive guidance on Kubernetes adoption, DevOps/CI-CD integration, and enterprise requirements such as scalability, security, and disaster recovery. Build and share reference architectures, deployment patterns, and technical assets to accelerate customer adoption of vKS. Deliver clear, compelling technical presentations to diverse audiences, from architects to executive decision makers. Stay current on industry trends, competitor offerings, and evolving enterprise requirements to position vKS effectively. Collaborate with product management and engineering to provide field feedback that influences roadmap direction. Required Skills & Experience Experience in application engineering or technical sales for enterprise IT, cloud, or application platforms. Strong expertise in Kubernetes, containers, and VMware Cloud Foundation (vSphere, vSAN, NSX as foundation). 8-10+ years in technology-related roles, with depth in enterprise IT architecture, application modernization, or cloud-native platforms. Demonstrated success working directly with enterprise customers to deliver technical solutions and drive platform adoption. Excellent communication, storytelling, and presentation skills with the ability to engage both technical and business leaders. Strong collaboration skills, able to work hand-in-hand with sales teams to advance customer opportunities. Proven ability to identify challenges, design solutions, and articulate value in business terms. Enthusiastic self-starter with curiosity, drive, and the ability to thrive in dynamic environments. Ability to travel up to 50% of the time Qualifications Bachelor's Degree or Master's Degree plus 12+/10+ in Computer Science, Engineering, Mathematics, or related field; or equivalent experience. Deep knowledge of VMware Cloud Foundation and Kubernetes platforms. Certifications in cloud-native or public cloud technologies (AWS, Azure, GCP, Red Hat OpenShift, etc.) are highly desirable. Additional Job Description: Compensation and Benefits The annual base salary range for this position is $118,800 - $171,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Cloud Architect will be responsible for providing technical support to Engineering and Corporate organizations at AMD. This position will be required to support AMD's global cloud infrastructure in a dynamic, fast-paced environment. Furthermore, this person will be collaborating globally on efforts for various IT activities related to the AMD Engineering AI/GPU - Compute Environment, in accordance with AMD Worldwide IT strategies and objectives. THE PERSON: You're a highly motivated team player with a strong development background, problem solving mentality, excellent communication skills, ability to prioritize tasks along with willingness to learn and adapt. Excellent teamwork skills and capable of working independently. KEY RESPONSIBILITIES: * Design, develop, deploy, monitor, maintain, and evolve cloud-native resources, tools, services, reusable modules (infrastructure-as-code-practices) and frameworks to secure and automate provisioning of cloud infrastructure that empowers our users across Azure, AWS, GCP. * Provide customers with standards and best practices on how to deploy and consume cloud-based services. * Proactively seek opportunities to improve operational efficiency of teams and usage of cloud services. * Contribute to a strong team-culture and an atmosphere of cross-functional teamwork. * Work with internal customers in managing incident tickets to achieve operational excellence. * Work with global teams to provide support and complete IT projects. * Create secure hybrid deployments of virtual machines, and PaaS solutions in Azure, AWS, GCP. * Work with Project teams to understand and accommodate application architecture and the App's specific requirements for Azure, AWS, and GCP. * Collaborate with other engineers and stakeholders to share knowledge and build expertise for IaaS, PaaS, and Saas deployment. * Collaborate with onshore and offshore resources. * Implementing and automating security controls, governance processes, and compliance validation by closely partnering with the Security Team to incorporate respective requirements and best practices to keep our Cloud Env safe and secure. * Applies experience in migrating on-premises applications and workloads to Azure, AWS, GCP using cloud technologies and providing support. * Drives identity (IAM), access, and configuration management for cloud native tools. * Responsible for the Recovery and Continuity process for cloud environments. PREFERRED EXPERIENCE: Cloud Systems Engineer general experience of various CSPs fundamentals with: * Terraform, YAML, Jenkins, GitHub actions. * Python, Golang, Shell, Java/J2EE, NodeJS, ReactJS, HTML5, PyTorch * Able to build and support a full CI/CD pipeline to support consistent code deployment. * Preferred understanding of AI framework * Managing GPU clusters optimizing GPU-based services/tools/software * Experience with Container technologies (GKE, EKS, ECS, Docker, Kubernetes) is desirable. * Understanding CHANGE Management/Release Process * Strong analytical and problem-solving skills. * Strong understanding of Agile/Scrum methodologies. * Strong written and verbal communication skills. Ability to effectively communicate technical issues and solutions to peers and external vendors. * Strong active listening and consensus-building skills and passionate about learning and sharing knowledge with others. * Infrastructure automation like Ansible, Terraform, or Cloud Formation, Deployment Mgr., and Resource Mgr. * Designing, developing, and implementing solutions that improve efficiency and reduce costs through Kubernetes/containers, virtualization, functions, and automation. * Experiences in building and managing complex cloud environments in Azure, AWS, GCP including security measures for encryption, authorization, and protocols. * Monitoring system performance, conducting capacity planning, identifying trends, and providing recommendations to improve service levels via automation. * Working closely with software development teams to troubleshoot and resolve issues. * Understand cloud networking (VPCs), Load balancers, WAFs and CDNs * Experience deploying, managing, administering, and migrating Infrastructure platforms in a Hybrid environment. * Strong understanding of different deployment resource types and when to deploy each type (IaaS, PaaS, SaaS). * Experience with Cloud native monitoring tools and also Nagios, ELK stack, Kibana/Prometheus. * Proactive and empathetic mindset - you love to roll up your sleeves to fix problems for our customers. * Ability to juggle multiple projects and priorities and re-prioritize as necessary to align with current business. * Strong organizational ability. ACADEMIC CREDENTIALS: * Bachelor's degree in Computer Science, Engineering, or a related field. LOCATION: San Jose, CA #LI-MF2 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: SerDes Technology group is seeking a talented, motivated and self-driven SerDes Micro Architect with expertise in high-speed SerDes RTL design. You have had significant success driving architecture and product requirements, integrating complex IPs into SOC. You have deep knowledge of digital design methodology and are meticulous about Power, Performance and Area. In this role, you will work with a world-class team to drive the definition of next generation high-speed SerDes IPs. THE PERSON: If you have a keen interest in high-speed SerDes and digital RTL design, excel in teamwork and possess strong communication skills, your profile aligns well with our requirements. We are seeking someone who is innovative, detail-oriented and possesses excellent problem-solving skills to join our design team. KEY RESPONSIBILITIES: * Define micro-architecture requirements for SerDes IPs, drive technical specifications to meet those requirements, and provide technical direction to execution teams * Design and development of digital logic blocks in leading edge technology nodes * Work with cross-functional teams to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements * Work closely with design teams for area and floorplan refinement, verification test plan reviews, timing targets, emulation plans, pre-Si bug resolution and performance/power verification sign offs * Support post-Si teams for product performance, power and functional issues debug/resolution PREFERRED EXPERIENCE: * Excellent communication, management, and presentation skills * Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies * Experience in driving the definition of high-speed SerDes IPs, with strong knowledge on the application in PCIe and Ethernet * Experience in system architecture, CPU & IP Integration, power and clock management design * Experience in RTL design, verification, synthesis and STA in high performance design * Good understanding of adaptation and calibration algorithms * Good understanding of link equalization, clock and data recovery * Good understanding of digital signal processing * Good knowledge of SystemVerilog and UVM ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in related discipline LOCATION: San Jose, CA #LI-SC3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.