Design Engineer jobs at Cadence Design Systems

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Application Engineer Architect for Allegro Package Design Tools - San Jose, CA Cadence offers amazing opportunities for professional growth, regardless of where you are in your career. Our ideal candidate will be energetic, innovative, and enthusiastic about helping customers solve their most challenging design problems. As an Application Engineer you will have the exciting opportunity to work closely with our customers supporting technical campaigns by delivering product demonstrations, knowledge transfer, training, and onsite support. This will involve working with state-of-the-art complex IC packaging of electronics using highly integrated IC package co-design and multi-die chiplet methodologies. Responsibilities include: + Working closely with our customers who are in the Advanced Packaging space + Helping customers to adopt and proliferate our packaging solutions + Consulting with customers to understand their flow requirements and creating solutions that best meet their needs + Conducting technical presentations, technical training, and product demonstrations, including development of customized presentations + Supporting technical evaluations and benchmarks + Collaborating with Sales Management to identify and prioritize opportunities, and to assist in developing winning sales strategies + Working with Cadence Engineering and Marketing to communicate requirements and drive resolution of issues Required Experience/Skills: + BS in Electrical, Mechanical or Computer Engineering + Minimum 8 years of practical experience with Cadence IC packaging tools is required + Must possess expertise in 2.5D/3D-IC packaging technologies + CAD experience in setting up Cadence tools is desirable + Solid verbal and written communication skills + Exceptional problem-solving skills + Ability to work independently and productively in a fast paced and dynamic environment + Interest in learning new technologies + Open to continued personal development to meet the evolving demands of the EDA industry Additional Information: + San Jose office location strongly preferred The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Join our leading-edge Design and RTL Methodology team as a Hardware Development Engineer, contributing directly to the development of our latest FPGA products. In this role, you will help ensure the highest quality of RTL design that our customers rely on. THE PERSON: You are an experienced, proactive RTL Design Engineer who thrives in a fast-paced environment. You quickly ramp up on new tools and methodologies, and you're comfortable working on a small, highly capable team where you can take on significant responsibility. KEY RESPONSIBILITITES: * We will guide you as you ramp up on our RTL design and static verification tools and methodology ecosystem. * Collaborate with the design team to drive continuous improvements in front-end design methodologies, ensuring top-quality RTL across areas such as Lint, CDC, formal equivalence, and low-power verification. * Enhance and develop flows that analyze RTL and Unified Power Format (UPF) Files, including updating or creating new UPF to enable robust verification of power-domain crossings for AMD's next-generation monolithic and stacked FPGA-SoC product families. * Leverage corporate AI systems to increase productivity and streamline workflows. PREFERRED EXPERIENCE: * Proven experience in logic design and static verification (SystemVerilog, Verilog, or VHDL), ideally with contributions to at least two ASIC products brought to market. * Strong background in RTL/logic design, including specifying multi-power-domain architectures using IEEE 1801 Unified Power Format (UPF). * Programming skills in Perl, Python, and TCL. ACADEMIC CREDENTIALS: * Bachelor's degree in Electrical or Computer Engineering; Master's degree preferred. LOCATION: San Jose or other HYBRID office locations. #LI-GW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a design engineer in our CAD and methodology team, you will be responsible for leading and optimizing the EDA environment for Project CAD team in the Adaptive & Embedded Computing Group (AECG). You will oversee the complete SCH-to-GDS flow, manage tool deployments, and drive methodology development across multiple semiconductor projects. This is an opportunity to shape the technical direction of critical IC design workflows and lead a team of skilled CAD engineers. You will advise on tools selection, and interface with various EDA tool vendors and foundries to run the EDA tools, PDKs and other files necessary for the Silicon Development Team to operate efficiently. You will be responsible for defining and creating a unified environment that sets the versions of the tools, PDK and design for every individual chip in development. Additionally, you will interact with the various Silicon development teams who will be requesting newer versions of the tools and raise trouble tickets with CAD vendors as needed. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: * Execute in CAD infrastructure team supporting multiple IC design projects * Establish and maintain standardized design flows and methodologies * Implement and support customized CAD flows for Fabric design groups * Enable the team to meet design and development targets by working closely with external tool vendors * Develop tools flows methodologies on digital back-end domains, sign-off flows for timing, power, EM/IR, DRC/LVS/DFM, etc. * Improve engineering efficiency while improving design quality in IP release process * Be single point contact for bugs and issues for custom and analog physical design team * Build flow in TCL, Python to ensure quality and faster executions * Understand different methodologies used across industry to adopt best practices * Leverage and deploy AMD AI systems to design teams PREFERRED EXPERIENCE: * Proficiency in TCL, Python, PERL, or other scripting languages * Experience with PDKs and technology enablement * Skilled in Spice and PVT simulation environments * Hands-on expertise with Virtuoso-based custom layout tools and flows * Familiarity with Calibre extraction flows and EM/IR analysis using Totem and Redhawk * Working knowledge of SiliconSmart, PrimeTime, and Physical aspect of VLSI designs * Strong written and verbal communication skills ACADEMIC CREDENTIALS: * Bachelor's degree in Computer or Electrical Engineering, or equivalent; Master's degree preferred LOCATION: * San Jose #LI-GW1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SoC Architect THE ROLE We are seeking a SoC Architect to join our adaptive SoC Architecture team. This role is pivotal in defining and driving architecture for next-generation Adaptive SoCs, with on Processor subsystems, Interconnect, AI, GPU, video processing pipelines, and memory systems. THE PERSON You are a seasoned SoC architect with deep expertise in heterogeneous compute systems. You thrive in collaborative environments and bring a system-level mindset to solving architectural challenges. You are passionate about performance, power, and scalability, and have a strong grasp of silicon design trade-offs. You communicate effectively across engineering disciplines and influence architectural decisions with clarity and technical rigor. KEY RESPONSIBILITIES * Drive architecture of key IPs including their PPA tradeoffs, Interconnect, and integration into SoC * Define and optimize SoC control bus protocols, reset flows, clocking strategies, and power domains. * Drive early-stage architectural analysis, modeling, and specification development. * Contribute to architectural innovation for Adaptive SoC Use-cases in AI, GPU, video, and IO domains. * Collaborate with planning, software and hardware cross-functional teams to develop architecture solution. * Collaborate with subsystem architects to ensure cohesive integration and system-level performance. PREFERRED EXPERIENCE * Proven experience in SoC architecture with Processor, Interconnects, and Memory subsystem. * Expertise in AI accelerators, GPU integration, video processing pipelines, and IO subsystems. * Expertise in SoC control bus design, reset architecture, clocking , and power management techniques. * Experience with modeling and automation using Python, SystemC, or equivalent. * Knowledge of advanced process technologies and associated design challenges. ACADEMIC & EXPERIENCE REQUIREMENTS * BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field. * Demonstrated success in delivering high-performance, low-power SoC solutions. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ SILICON DESIGN ENGINEER 2 THE ROLE: Join a team of silicon design engineers who utilize their skills in logical and physical circuit optimization to innovate and implement programmable logic interfaces. Our team owns the design and implementation from RTL to final layout database delivery, as well as supports silicon validation and characterization. You'll be part of a small and focused design team with a wide scope of responsibilities and technical opportunities using the latest in circuit design tools and methodologies. Your skills will be deployed in simulation, characterization, and model development for circuit performance and power at cell, critical path, and block-level designs. THE PERSON: We are looking for a self-motivated team worker, who possesses good verbal and written communication skills. The ideal candidate strives to tackle challenges in creative ways with solutions that can be applied in a wide range of applications. If you have a drive for high-quality, high-accountability design work, then you will be a great fit for our team! KEY RESPONSIBILITIES: Schematic capture Logical equivalency checks Test bench development Place and route constraint definition Physical design closure in APR tools Critical-path simulations for timing correlation with STA Electrical rule checks commensurate with each stage of the design Generating and characterizing models of circuit timing and power PREFERRED EXPERIENCE: Knowledge in VLSI design, design automation, IC design, and RTL design Knowledge of floor planning, synthesis, place & route, static timing analysis, and EM/IR analysis Knowledge of Cadence SPICE, Synopsys Primetime, and IC compiler preferred ACADEMIC CREDENTIALS: MS (preferred) or BS with additional experience in Electrical Engineering or Computer Engineering or related equivalent #LI-JY1 Requisition Number: 162224 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ TITLE: Design Engineer At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. THE ROLE: This position is within the AMD SERDES Technology team in San Jose, CA, looking for a talented and motivated team member with a focus on FPGA design and hands on silicon bring-up. You will use your knowledge of high-speed SerDes and design experience to develop various solutions for common high-speed SerDes interfaces and applications. RESPONSIBILITIES: FPGA design and IP solutions development Develop embedded firmware for validation and applications development Work with internal teams to create IP solution, debug features associated with physical layer functionalities Provide customer support and field debugging as required Preferred Skills & Experience: FPGA design and debug experience C/C++ for embedded system development Knowledge of physical layer specifications in IEEE 802.3 and / or PCIe Programming experience in Python or Perl scripting languages Hands-on experience with various lab equipment for silicon bring-up and validation Knowledge of 50G+ multi-level (i.e. PAM4) SERDES is preferred Excellent verbal and written communication skills ACADEMIC CREDENTIALS: B.S. or M.S. Electrical or Computer Engineering preferred Requisition Number: 179684 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ Job Requirements: Experience in Digital Design or Silicon characterization Should be knowledgeable about all the internal blocks of FPGA like DSP, BRAM, I/O etc Good understanding of device technology, custom circuit and digital designs and electrical analysis Strong scripting skills using Perl, Python, C-shell or similar scripting languages. Experience with Xilinx FPGA design / implementation tools is a plus Good analytical, communication, presentation and troubleshooting skills are required Education Requirements Minimum of a BS with 2+ year of experience or MS degree in Electrical Engineering, Computer Engineering or related equivalent #LI-JY1 Requisition Number: 167464 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: * RTL design for memory I/O * PHY Digital Architecture development from pathfinding, coding, verification to physical implementation * PHY link layer design, implementation & verification with Analog and System architect. * PHY Analog/Digital co-design * Digital design and RTL coding * Timing Synthesis & Drive Physical implementation * Collaborate with architects, hardware engineers, and firmware engineers to understand the new features * Estimate the time required to write the new feature tests and any required changes to the test environment * Build the unit tests * Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues PREFERRED EXPERIENCE: * Digital design engineering experience * Experienced with Verilog, System Verilog, C, and C++ * Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus * Knowledge of clocking architectures, synchronization, and CDC methodology * Experience with synthesis, Timing closure * SERDES, DDR, Memory Controller, or MAC Design experience is preferred * Proficient in debugging firmware and RTL code using simulation tools * Strong understanding of computer organization/architecture. * Mixed signal RTL, Low power design experience is a plus * Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Santa Clara, CA or Boxborough, MA This role is not eligible for Visa sponsorship #LI-SC3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the Graphics and Engineering group, you will help bring to life cutting-edge designs related to Artificial Intelligent/ High Performance Computing SOCs . As a member of the Physical design and SOC teams, you will work closely with the architecture, IP design, RTL design, CAD, silicon technology teams and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: * Physical design and signoff methodology development for advanced nodes and High performance * Automation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environment for an SOC * Full chip / sub-system/ Tile level timing analysis with bleeding edge STA methodologies * Full chip / sub system level Clock tree synthesis and advanced clock tree construction and analysis. * Block and top level Formal verification, Physical Verification and chip finishing methodologies. * Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion, IRdrop and logic equivalence * Statistical and Static Timing Analysis, Variation aware analysis, stdcell Library characterization enhancements * Developing and Integrating ML and LLM applications for Physical Design and Analysis flows * Performing data analysis and identifying design trends * Customizing and implementing solutions for new challenges * Collaborating with multi-site engineering teams to reach project goals * Hands-on in reference flows, excellent debugging skills. * Maintain and update technology collaterals PREFERRED EXPERIENCE: * Experience in ASIC Physical Design and/or CAD development * Hands-on experience with Place and Route, Timing Analysis, and Physical Verification tools from Synopsys, Cadence, like ICC2, Fusion Compiler, DSO.AI, Innovus, Cerebrus, Primetime, Primeshield, PT-PX, Formality, Conformal, RedHawk, etc. * Experience in 5nm and below technologies * Script development, scripting (TCL, Perl, Python, Pandas), ML/AI techniques * Knowledge and Experience in ML and LLM * Experience with data analytics applications, database management ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering This role is not eligible for Visa Sponsorship. #LI-PA1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a PCB Layout Physical Design Engineer - CAD in our Networking Technology & Solutions Group (NTSG), you will be responsible for ensuring that AMD's next-generation products deliver industry-leading reliability, performance, and efficiency. THE PERSON: In this role, you will closely collaborate with Silicon IP team, ASIC packaging team, PCB team, System Architect and external partners/suppliers to meet the most demanding SerDes requirements while ensuring the manufacturability. KEY RESPONSBILITIES: * PCB physical design for high-speed and high-power boards from initial concept to mass production * Optimize component placement, high-speed signal routing, critical power plane * Create design constraints based on the requirements of Hardware Design engineers, Signal/Power-Integrity engineers, Mechanical/Thermal engineers * Ensure that complex system layouts meet electrical and mechanical/thermal specifications * Adapt designs to fit component availability or manufacturing limitations * Resolve any issue related to PCB physical design and ensure a smooth transition from design to production * Generate comprehensive manufacturing and assembly packages such as Gerber, ODB * Building strong relationships with both engineers and manufacturers to reduce the risk of redesigning * Collaborate with cross-functional teams to drive product development while keeping projects on schedule and within scope. * Stay at the forefront of PCB physical design innovations and technologies to ensure AMD leadership in the industry PREFERRED QUALIFICATIONS: * Strong experience on PCB physical design for high-speed/high-power systems * Strong background in electronic fundamentals * Strong expertise in PCB design software such as Cadence Allegro * Deep knowledge on different types of layers such as copper, silkscreen, solder mask, and different types of component models such as symbol, footprint * Basic knowledge of mechanical, thermal, signal integrity, power integrity * Familiarity with PCB manufacturing processes and standards * Hands-on experience of balancing the technical requirements from hardware engineers and the practical constraints set by manufacturers * Excellent problem-solving and cross-functional collaboration skills ACADEMIC CREDENTIALS: Bachelor or Master degree of Electrical Engineering, Computer Engineering, or related field LOCATION: Santa Clara, CA #LI-BW1 #LI-NTSG-HW Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Graphics Memory Controller (GMC) is an IP that delivers into AMD's Discrete GPU (Navi) and Instinct (HBM) based SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for an experienced, conscientious logic design engineer in the Dram Controller IP at AMD's Santa Clara Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. THE PERSON: The ideal candidate for this role is an experienced and detail-oriented logic design engineer with a strong background in RTL development and a commitment to advancing graphics technologies. With over five years of experience in digital design, they bring expertise in high-speed memory interfaces such as HBM and GDDR and have a proven ability to deliver high-performance designs that meet timing, power, and area requirements. They are proficient in Verilog and familiar with industry-standard CAD tools from Synopsys, Cadence, and Mentor Graphics, with strong skills in simulation, synthesis, and timing analysis. This individual works effectively in dynamic, collaborative environments, communicates clearly across teams, and demonstrates strong analytical and problem-solving abilities. Their initiative and attention to detail make them a valuable contributor to AMD's Santa Clara Design Center, where they will support the development of next-generation discrete GPUs and data center solutions. KEY RESPONSIBILITIES: * Participate in the development of Architecture and Micro-architecture specifications for the Logic components. * Perform logic design, Register Transfer Level (RTL) coding for new features within existing blocks and design new blocks supporting HBM and GDDR DRAM Technologies * Deliver Designs that meet functional and performance requirements, * Deliver Design that meets physical/structural design constraints (timing, area, power) * Work with Verification Engineers to effectively communicate and resolve issues from test plan through feature bring up to coverage closure PREFERRED EXPERIENCE: * Logic design implementation using hardware description language (RTL) * Experience working on DRAM or similar high-speed interfaces is a big plus * Usage/execution of logic simulation, synthesis and familiarity with logic development flows * Strong RTL analysis skills including Verilog, Timing Analysis * Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics * Strong communication, Time Management, and Presentation Skills * Must be a self-starter, and be able to independently and efficiently drive tasks to completion * Excellent analytical and problem-solving skills along with attention to details * Aware of latest Power -aware design methodologies ACADEMIC CREDENTIALS: * Bachelor's or master's degree in computer engineering, Electrical Engineering, or a related field. #LI-DP1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ The System Validation team plays a key role in validation of complex SOCs in pre-silicon and post silicon. Our most recent project Versal ACAP, a fully software-programmable, heterogeneous compute platform that combines Scalar Engines, Adaptable Engines, and Intelligent Engines to achieve dramatic performance improvements with dual core ARM processing system and Programmable logic is known for Industry's first Heterogeneous architecture. We are looking for a passionate engineer to work with us on our latest SOC - Versal. We are looking for an aspiring Systems Design Engineer with a strong background in software to join the System-level Test team in San Jose. As a System Validation Engineering Intern, you will be involved in the silicon life cycle from testing of emulated next-generation RTL through to silicon verification and characterization. You will have a view of the full system but also will become an expert in certain IP down to the register-level. We are looking for someone who can span the range of able to develop device drivers in software to debug on hardware. As an intern on our team, you will gain real engineering experience in working with complex SOC and validation software and make a difference to the quality of our products. Responsibilities Assist in bringing up system level validation tool on new silicon Run regressions and experiments to help root cause issues Enhance existing test software for system-level validation and verification of existing and new FPGA features. Design, develop, implement, test, and verify systems based on FPGAs with embedded Micro Blaze or ARM processors Help to develop novel methods for system-level modeling and verification Help automate design, test, and build processes Qualificiations Must be a student enrolled in a bachelor's or master's degree program in Electrical / Computer Engineering with an emphasis on embedded system development and/or computer architecture Computer Architecture class(es) required Programming languages: C, Python, Verilog To support our group, we are looking for a intern that can commit to a full time (40 hr per week), 4-12-month internship starting in January 2023. You must be able to work onsite at are San Jose, CA Office. Located at 2100 Logic Dr, San Jose, CA 95124 Shorter internships will NOT be considered. Requisition Number: 185604 Country: United States State: California City: San Jose Job Function: Student/ Intern/ Temp Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The candidate will join a highly visible team of physical interface experts concentrated on SERDES interfaces across AMD products. The team works across a large swath of AMD teams and is instrumental in the delivery of leading-edge, high-speed interface capabilities. THE PERSON: The ideal candidate is self-motivated to work independently as well as collaboratively with engineers across a variety of AMD design, verification, and validation teams. KEY RESPONSIBILITIES: * Excellent working knowledge of RTL-based design flows * Strong knowledge of firmware and hardware interaction * FPGA design and prototyping for various MAC or PCS functionalities * Working knowledge of the entire FPGA or ASIC design process and tool flow * Work with internal and external teams to develop transceivers solutions for various applications * Hands-on experience with various lab equipment for silicon bring-up and validation PREFERRED EXPERIENCE: * Familiar with industry standards such as Ethernet and PCIe is a plus * Strong analytical and problem-solving skills with pronounced attention to details ACADEMIC CREDENTIALS: * BS or MS in Electrical or Computer Engineering preferred LOCATION: San Jose, CA #LI-DP1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The candidate will join a highly visible team of physical interface experts concentrated on SerDes interfaces across AMD products. The team works across a large swath of AMD teams and is instrumental in the delivery of leading-edge high-speed interface capabilities. THE PERSON: The ideal candidate is self-motivated to work independently as well as collaboratively with engineers across a variety of AMD design, verification, and validation teams. KEY RESPONSIBILITIES: * SerDes applications and system design for the next generation high-speed transceiver * Collaborate with analog/mixed-signal design teams to define specifications for TX/RX front-end circuits, PLLs, CDRs, and data converters * Define SerDes system-level and block level validation plan * Drive innovation in SerDes architectures to support emerging standards and custom protocols for hyperscale and AI workloads * Perform end-to-end channel analysis across backplane, midplane, and cable assemblies within rack-level systems * Define PCB stack-up, routing topology, and via structures optimized for high-speed SerDes channels, including differential pair impedance control, return path continuity, and crosstalk mitigation * Define IBIS-AMI models validation and hardware correlation methodology PREFERRED EXPERIENCE: * Knowledge and experience in high-speed I/O design and electrical compliance testing in Ethernet and PCIe * Experience with SI tools, HSPICE, HFSS, ADS or similar * Hands-on experience with high-speed oscilloscopes, BERTs, VNA and spectrum analyzer for SI/PI analysis ACADEMIC CREDENTIALS: * BS or MS in Electrical or Computer Engineering preferred LOCATION: San Jose, CA #LI-TB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a Product Development engineer, you will collaborate with various Product Development Groups to help with driving the execution of AMD's Value-Added Services (VAS) for FPGA and Adaptive SoC products. This role bridges technical innovation with customer engagement, enabling tailored solutions that drive design wins and revenue growth. This individual serves as a critical technical point of contact to the business, sales, technical field, customers, and product engineering teams. We have competitive benefit packages and an award-winning culture. Join us! THE PERSON: A successful candidate possesses deep technical expertise, cross-functional collaboration skills, and a strategic mindset to deliver differentiated services across manufacturing, logistics, and engineering domains. Additionally, the candidate can make technical decisions independently, has accountability for accuracy, reliability and completeness of assignment results critical to the project's success. This role allows the opportunity to influence technical decisions that have a significant impact on multiple products or the product line. KEY RESPONSIBILITIES: * Collaborate to Customize AMD Products: Work closely with cross-functional teams to tailor device features-such as performance, power, and test screening-based on customer needs. * Collaborate to Deliver Custom Technical Solutions: Leverage customer-specific offerings including customized test screening, eFUSE programming, secure provisioning, and device-level traceability. * Partner with Customers: Engage directly with customers to understand their technical requirements and co-develop solutions that align with their system goals. * Coordinate Service Delivery: Team up with engineering, manufacturing, and logistics to deliver value-added services like custom labeling and marking, and package enhancements. * Contribute to Innovation and Growth: Support the team in identifying and executing new service opportunities that strengthen AMD's competitive edge and drive business growth. * Support die / wafer delivery efforts: Work with internal teams on bare die, chiplet, and SiP programs, ensuring technical readiness and smooth integration with customers. PREFERRED EXPERIENCE: * Proven experience in semiconductor product engineering, technical sales, or solutions architecture. * Deep understanding of FPGA, Adaptive SoC architectures, and manufacturing test methodologies. * Strong customer engagement and communication skills; ability to translate technical capabilities into business value. * Proven ability to work cross-functionally to drive initiatives and manage complex customization workflows. ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in electrical engineering, computer engineering, or related fields. LOCATION: San Jose, CA This role is not eligible for visa sponsorship. #LI-AJ1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Transforming the Future with Convergence of Simulation and Data FEA Design Engineer . The employee is part of the Design Engineering Team and shall serve as a stress analysis and mechanical design subject matter expert supporting a variety of projects. The employee will work unsupervised approximately 75%+ of the time. Product line is primarily high pressure, high temperature pneumatic and fluid lines for aerospace applications. Markets served include domestic and foreign commercial, military, and space. Essential Duties and Responsibilities: * There are two primary job functions: Detailed component design and FEA based stress analysis. * Component design consists of conceptual sketches (physical or CAD) which are fed to the drafting team. Significant application of concepts such as design to specification, design for manufacturing, design for inspection, and design for cost. * Stress analysis has a heavy emphasis on structural dynamics, fatigue, and nonlinear solutions. FEA tasks range from simple geometry creation and meshing all the way to final analysis report. * Works with a diverse cross-functional team of engineers designing and analyzing metallic parts that are produced using a variety of manufacturing methods. Common methods: forming and welding of sheet metal, machining, additive manufacturing, and casting. * Regular interaction with internal teams of: Project Engineers, Drafters, Manufacturing Engineers, Quality Engineers, Test Lab Personnel, Contracts, and Sales. * Tasks involve a full range of product life cycle including new product development, legacy product support, research and development, and failure analysis. * Often necessary to create (i.e. programming) custom design and task automation tools in Excel (VBA), MATLAB, Python, and the API of applicable calculation software. * Internal flow calculations and external insulation calculations are common using in-house tools. * Travel required is engineers for customer design reviews, and potential onsite customer support during initial quotation or design phases. Qualifications * BS Degree in Mechanical, Aerospace, Astronautical or similar Engineering field. (MS Degree preferred). * 5+ years of experience in an engineering design environment. * 6+ years of experience with finite element analysis stress software (HyperWorks, Femap/NASTRAN, or ANSYS Mechanical). * 4+ years of experience specifically with HyperWorks / Hypermesh, Optistruct . * Demonstrated expertise in data analysis and reduction. * Experience with linear and nonlinear static FEA solutions is required. * Experience with modal, harmonic response, and random response is required. * Experience with contact analysis is preferred. * Experience with topology optimization is required. * Experience with simulation of metal forming methods is preferred. * Experience designing for metallic additive manufacturing is required. * Experience with SolidWorks, CATIA, or similar drafting software is preferred. * Experience with Stainless Steel, Titanium, Inconel, and other superalloys is preferred. * Experience applying GD&T per ASME Y14.5:2018 (and/or 2009) to complex components and assemblies is required. * Experience in the MRB review and disposition of nonconforming hardware is required. How You Will Be Successful: * Envision the Future * Communicate Honestly and Broadly * Seek Technology and Business "First" * Embrace Diversity and Take Risks What We Offer: * Competitive Salary * Comprehensive Benefit Package * 401(k) with matching contributions * Paid Time Off * Employee Discounts * Free training on all Altair products Why Work with Us: Altair is a global technology company providing software and cloud solutions in the area of data analytics, product development, and high-performance computing (HPC). Altair enables organizations in nearly every industry to compete more effectively in a connected world, while creating a more sustainable future. With more than 3,000 engineers, scientists, and creative thinkers in 25 countries, we help solve our customer's toughest challenges and deliver unparalleled service, helping the innovators innovate, drive better decisions, and turn today's problems into tomorrow's opportunities. Our vision is to transform customer decision making with data analytics, simulation, and high-performance computing. For more than 30 years, we have been helping our customers integrate electronics and controls with mechanical design to expand product value, develop AI, simulation and data-driven digital twins to drive better decisions, and deliver advanced HPC and cloud solutions to support unlimited idea exploration. To learn more, please visit altair.com Ready to go? #ONLYFORWARD At our core we are explorers; adventures; pioneers. We are the brains behind some of the world's most revolutionary innovations and are not only comfortable in new and unchartered waters, we dive headfirst. We are the original trailblazers that make the impossible possible, discovering new solutions to our customer's toughest challenges. Altair is an equal opportunity employer. Our backgrounds are diverse, and every member of our global team is critical to our success. Altair's history demonstrations a belief that empowering each individual authentic voice reinforces a culture that thrives because of the uniqueness among our team.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Application Engineer Architect for Allegro Package Design Tools - San Jose, CA Cadence offers amazing opportunities for professional growth, regardless of where you are in your career. Our ideal candidate will be energetic, innovative, and enthusiastic about helping customers solve their most challenging design problems. As an Application Engineer you will have the exciting opportunity to work closely with our customers supporting technical campaigns by delivering product demonstrations, knowledge transfer, training, and onsite support. This will involve working with state-of-the-art complex IC packaging of electronics using highly integrated IC package co-design and multi-die chiplet methodologies. Responsibilities include: Working closely with our customers who are in the Advanced Packaging space Helping customers to adopt and proliferate our packaging solutions Consulting with customers to understand their flow requirements and creating solutions that best meet their needs Conducting technical presentations, technical training, and product demonstrations, including development of customized presentations Supporting technical evaluations and benchmarks Collaborating with Sales Management to identify and prioritize opportunities, and to assist in developing winning sales strategies Working with Cadence Engineering and Marketing to communicate requirements and drive resolution of issues Required Experience/Skills: BS in Electrical, Mechanical or Computer Engineering Minimum 8 years of practical experience with Cadence IC packaging tools is required Must possess expertise in 2.5D/3D-IC packaging technologies CAD experience in setting up Cadence tools is desirable Solid verbal and written communication skills Exceptional problem-solving skills Ability to work independently and productively in a fast paced and dynamic environment Interest in learning new technologies Open to continued personal development to meet the evolving demands of the EDA industry Additional Information: San Jose office location strongly preferred The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.

Category Engineering Hire Type Employee Job ID 12583 Base Salary Range $157000-$235000 Remote Eligible No Date Posted 21/08/2025 This position requires access to or use of information, which is subject to export restrictions, including the International Traffic in Arms Regulations (ITAR). All applicants for this position must be "U.S. Persons" within the meaning of the ITAR. "U.S. Persons" include U.S. Citizens, U.S. Lawful Permanent Residents (i.e. 'Green Card Holders'), Political Asylees, Refugees or other protected individuals as defined by 8 U.S.C. 1324b(a)(3). This role is required to work onsite in our Sunnyvale CA location. We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced engineer with a deep understanding of the RTL to GDSII flow. You thrive on solving complex technical issues and enjoy working closely with customers to enhance their experience with cutting-edge technology. With your strong background in synthesis, physical design, and static timing analysis, you excel in diagnosing and resolving technical challenges. You are an excellent communicator, capable of conveying technical concepts clearly and effectively to both technical and non-technical stakeholders. Your scripting skills in Perl, Tcl, and Python, along with your knowledge of CAD automation methods, make you a valuable asset to any team. You are motivated to work collaboratively with internal teams and customers to drive product adoption and satisfaction. What You'll Be Doing: * Providing technical and engineering insight to support and improve the usability, applicability, and adoption of Synopsys products. * Diagnosing, troubleshooting, and resolving complex technical issues on customer installations. * Deploying and training customers on new implementations and capabilities. * Reviewing and acting upon product feedback and solutions performance from customers and other application partners. * Working directly with R&D to develop and implement the technical roadmap, specifications, and validation for improvements and enhancements. * Partnering with customer technical managers and Sales to identify business challenges and develop effective technical solutions for new accounts. The Impact You Will Have: * Enhancing customer satisfaction by ensuring seamless product deployment and support. * Driving product adoption and utilization through effective technical training and support. * Contributing to the technical roadmap and product improvements based on customer feedback. * Supporting the sales team in acquiring new accounts by providing technical expertise. * Improving product performance and reliability through collaborative efforts with R&D. * Strengthening customer relationships by addressing and resolving technical challenges promptly. What You'll Need: * 7+ years of RTL to GDSII full flow experience or knowledge. * In depth experience debugging complex engineering issues related to STA, DRC/DRV and PPA optimization * Exceptional interest and knowledge of Advanced Node & Design methodologies. * Proven aptitude and motivation to work with internal and customer groups. * Excellent verbal and written presentation/communication skills. * Hands-on experience in synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis. * Knowledge of ASIC implementation domains outside of RTL2GDS including RTL coding, Verification, formal checking is a plus. * Good scripting skills (Python, Tcl, Perl); working knowledge of CAD automation methods. Who You Are: * A collaborative team player who thrives in a dynamic environment. * An excellent communicator with the ability to convey complex technical concepts effectively. * A proactive problem-solver with a keen eye for detail. * Customer-focused, with a passion for delivering exceptional service and support. * A continuous learner, always seeking to expand your technical knowledge and skills. The Team You'll Be A Part Of: You will be part of a highly skilled and dedicated team of engineers focused on providing exceptional technical support and solutions to our customers. Our team collaborates closely with R&D, Sales, and Customer Success to drive product innovation, adoption, and satisfaction. We value continuous learning, open communication, and a customer-centric approach in everything we do. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Are you looking to re-enter the workforce as a Physical Design Application Engineer after taking a career break for caregiving? Who is eligible to apply: Please ONLY consider applying if you are a Physical Designer and (IMPORTANT) who has been out of the workforce for caregiving for a period of at least two years and have a minimum of three years of Physical Design work experience. This role is not open to new college grads or interns. Please check our career site for those roles. Cadence is offering an opportunity to qualified candidates who meet our eligibility criteria to participate in a 16-week paid returnship program. You will be entered in a tailored program designed to jump start your skills through training, hands on projects and customer interaction. You will have an opportunity to update your resume, build connections and participate in fun events as you re-enter the workforce. In this program, you will work with best in class EDA tools, collaborate with R&D and the Sales team in a dynamic, innovative environment. Learn processes that are in the forefront of technology, how a company like Cadence works as well as experience how teams solve problems. We are seeking individuals with experience in Digital Synthesis, Place and Route and Signoff Analysis. Where is this returnship located: San Jose, CA What opportunity is offered: Candidates will find opportunities to be in the Application Engineering field spanning across Digital Synthesis, Place and Route and Signoff Analysis. How long is this returnship: 16 weeks Company Description: At Cadence, our core values are more than just words, they are the way we work, laugh, debate, care, question, and innovate together. We are One Cadence-One Team. Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation (EDA) company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Our team's shared passion for solving the world's toughest technical challenges and drive to do meaningful work makes us proud to be part of Cadence. Our unique culture has been recognized on FORTUNE Magazine's 100 Best Companies to Work For list and garnered accolades from the Great Place To Work Institute around the globe. #LI-MA1 The annual salary range for California is $59,500 to $110,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.