Principal Design Engineer jobs at Cadence Design Systems

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. At Cadence, we hire and develop innovators and leaders who want to make an impact on the world of technology. We offer amazing opportunities to grow, no matter where you are in your career. The ideal candidate will be energetic, innovative and enthusiastic about how to help customers solve their toughest verification problems using Cadence technology. Join our elite application engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces year after year! As an integral member of the North America Verification Field Applications Engineering (AE) Team, you will work directly with industry leading semiconductor and system companies to deploy Cadence's market leading verification platforms including cutting edge technologies using AI assistants, Agentic AI and machine learning. In this customer facing role you will provide the front line technical support in the pre and post-sales process and will work with the account team to come up with innovative solutions to address our customers' most challenging problems in verification. You will own customer success! In this role, you will develop customer specific verification requirements, including advanced verification component development, methodology support, and operation and maintenance of Cadence's verification tools and services. You will support technical evaluations and benchmark development for Cadence's market leading tools such as Xcelium simulation platform and Verisium platform of AI and ML tools for enhanced verification. You will create and conduct technical presentations and product demonstrations for customers. At Cadence, customers are at the heart of everything we do. Talented engineers like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in verification tools, unlock unique expertise in verification methodologies, and level up your communication, customer, and sales skills. No matter where you are in your career, whether your next career step is to stay on the technical track, move up in management, or explore sales/marketing career opportunities, the skills and expertise you gain as an Application Engineer here at Cadence will put you miles ahead in your career advancement. Key Responsibilities: - Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support - In collaboration with R&D, provide in-depth technical assistance to help support advanced verification flows and AI/ML applications to secure design wins - Champion the customer needs and work closely with R&D and marketing to develop competitive and creative technical solutions - Understand the competitive landscape and continuously work on differentiating Cadence's solutions - Write technical product literature such as application notes and technical articles - Review new product proposals and device specifications - Assume technical leadership roles in small teams as needed Requirements: Minimum: BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field 5+ years experience with SystemVerilog, VHDL, Verilog Verification skills such as UVM testbench architecture, development and debug Strong RTL and Testbench debug skills Experience in writing scripts (Perl, Python or Tcl) Strong software, HDL design and verification skills Ability to quickly analyze verification environments and design complexity Strong verbal and written communication skills Strong teamwork skills Ability to interact effectively with both external customers and R&D teams Preferred: Experience with C/C++/SystemC Experience in deploying VIP in testbenches Knowledge of protocols like JTAG, UART, PCIe, AMBA, DDR Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing Digital design experience The annual salary range for California is $143,500 to $266,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at ************** and on LinkedIn and Twitter (X). Principal Power Module Design Engineer in ADI µModule Group: (San Jose, CA, USA) Analog Devices is committed to investing in our people and their growth. Our hiring program features high impact professional development, opportunities to drive meaningful projects that are directly tied to business goals, and unique executive exposure. Our duty is to develop the next generation of talent in our communities and provide them with a pathway to apply their academic skills in the real-world. At ADI, our hires will learn from the brightest minds who are dedicated to their growth, development, and success. From an industry perspective, incoming new career hires are surrounded by employees that represent the best of the best minds in their respective fields. Apply now for the opportunity to grow your career and help innovate ahead of what's possible! The ADI power module team is seeking a motivated, experienced power module principal design engineer to in our Broad Market and Industrial BU located at ADI's San Jose offices. The candidate will be working with the industry best power engineering team and working on the industry leading power module product research and development. Responsibilities include, but not limited to: New power module product developments including product definition, feasibility, design, simulation, test, lab evaluation/debugging, qualification and release. Develop new product and technology roadmap and plans. Collaborate with product marketing, applications teams and customers to understand application requirements and contribute to architectural decisions of new products. Participate in customer, vendor or factory visits. Develop innovative techniques for advanced products and technology applications. Identify project technical risks, define mitigating strategies, and establish milestones to ensure project success. Enhance product development flows and qualities through advanced tools and methodologies. Prepare and present design review documentation at peer review meetings. Work cross-functionally to drive project schedules and achieve performance targets. Mentor and guide junior engineers for technical growth. Deliver technical writing, presentations and training sessions. Required Education, experiences, and skills: MSEE or Ph.D. degree in Power Electronics. Minimum 5-year industry experience of switching power converter design and development. Strong foundation of analog circuit, power electronics and power management systems. Expertise in switching mode power converter (Buck, Boost, etc) design and optimization. Solid knowledge and development experience of transformer-based isolated power converters (Flyback, forward, half-bridge, full-bridge, etc.) Strong analytic skills. Proficient in power converter modeling, control architecture and loop design, static and dynamic performance optimizations. Familiar with circuit design/simulation/optimization tools (SPICE/LTspice, Simplis, MathCAD/Matlab, Ansys/Maxwell, etc) and lab equipment for power applications. Strong hardware and circuit debugging skills. Magnetic design and simulation, thermal analysis knowledge and experiences. Familiar with digital power management, I2C and PMbus protocols. Familiar with firmware, DPS or FPGA programming (preferred). Analog IC design knowledge (preferred). Excellent technical writing and presentation skills Strong communication skills and ability to work effectively in a multidisciplinary team. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. Job Req Type: ExperiencedRequired Travel: Yes, 10% of the time Shift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $170,775 to $256,163. Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at ************** and on LinkedIn and Twitter (X). Staff Power Module Design Engineer in ADI µModule Group: (San Jose, CA, USA) Analog Devices is committed to investing in our people and their growth. Our hiring program features high impact professional development, opportunities to drive meaningful projects that are directly tied to business goals, and unique executive exposure. Our duty is to develop the next generation of talent in our communities and provide them with a pathway to apply their academic skills in the real-world. At ADI, our hires will learn from the brightest minds who are dedicated to their growth, development, and success. From an industry perspective, incoming new career hires are surrounded by employees that represent the best of the best minds in their respective fields. Apply now for the opportunity to grow your career and help innovate ahead of what's possible! The ADI power module team is seeking a motivated, experienced power module staff design engineer to in our Broad Market and Industrial BU located at ADI's San Jose offices. The candidate will be working with the industry best power engineering team and working on the industry leading power module product research and development. Responsibilities include, but not limited to: Lead new power module product development, including product definition, feasibility, design, simulation, test, lab evaluation, qualification and release. Collaborate with product marketing, applications teams and customers to understand applications and contribute to architectural decisions of new products. Develop innovative techniques for advanced products and technology applications. Identify project technical risks, define mitigating strategies, and establish milestones to ensure project success. Enhance product development flows and qualities through advanced tools and methodologies. Prepare and present design review documentation at peer review meetings. Work cross-functionally to drive project schedules and achieve performance targets. Perform lab evaluation or debug. Mentor and develop junior engineers for technical growth. Deliver technical writing, presentations and training sessions. Required Education, experiences, and skills: MSEE or Ph.D. degree in Power Electronics. Minimum 3-year industry experience of switching power converter design and development. Strong foundation of analog circuit, power electronics and power management systems. Strong DC/DC power converter (Buck, Boost, etc.) design and optimization experiences and skills. Solid knowledge and experience of transformer-based power converters (Flyback, forward, half-bridge, full bridge, etc.) Strong analytic skills. Good knowledge and skills of power converter modeling, control architecture and loop design, static and dynamic performance optimizations. Familiar with circuit design/simulation/optimization tools (SPICE/LTspice, Simplis, MathCAD/Matlab, Ansys/Maxwell, etc) and lab equipment for power applications. Strong hardware and circuit debugging skills. Firmware, DPS or FPGA programming and I2C/PMbus experience (preferred). Analog IC design knowledge (preferred). Magnetic design and simulation, thermal analysis knowledge and experiences. Good technical writing and presentation skills Strong communication skills and ability to work effectively in a multidisciplinary team. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. Job Req Type: ExperiencedRequired Travel: Yes, 10% of the time Shift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $144,038 to $216,056. Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for a ASIC Design Engineer, GPU/ML Shader Core who are motivated to challenge the status quo. If you are excited about building the next generation GPU/MI shader core, our team is on the lookout for you! You will be part of a fast-paced team working on the Graphics shader design, a team of engineers of varied disciplines who are responsible for micro-architecting, designing, and delivering GPU and ML/AI shader IP for various products. Since we are the heart of GPU engine, we strive to challenge ourselves in exceeding area, power, and performance targets. No idea is too small; we welcome every initiative that makes our product better. THE PERSON: You are an "out of the box" thinker, motivated to absorb dynamic changes and thirsty to keep innovating. You will work on the sub-block inside programmable engine aka shader core of the GPU. The shader core plays a key role in running applications program, feeding, and consuming the data to/from GPU shader resources and computing mathematical operations. Collaborate with software, architect, micro-architect and logic design team members to define and tackle "how to efficiently own an application program with the least number of instructions and data transfer while consuming the least amount of power". Strong interpersonal skills and an excellent teammate. KEY RESPONSIBILITIES: * Collaborate with block architect, ASIC designers and verification engineers to define and document block micro-architecture and analyze architectural trade-offs based on features, performance requirements and system limitations * Responsible for owning full design cycle from defining micro-architecture, implementing RTL, and deliver fully verified and PD timing clean design. * Consult DV engineers in describing features, outlining test plans, and closing on coverage * Assist DV engineers to debug functional, performance or power test failures * Work with Physical Design team to close on timing, area and power requirements PREFERRED EXPERIENCE: * Experience in micro-architecture and RTL development (Verilog), focused on GPU/CPU/ML/AI pipelines, arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. * Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. * Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required. ACADEMIC CREDENTIALS: * Undergraduate degree required. Bachelors or Masters degree in Computer Engineering/Electrical Engineering preferred. LOCATION: * Santa Clara CA - San Diego CA - Folsom CA This role is not eligible for Visa sponsorship. #LI-BM1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. ASIC Physical Design Engineer THE ROLE: The position will involve working with a very experienced physical design team of AMD graphics core and is responsible for delivering the physical design of blocks to meet challenging goals for frequency, power and other design requirements for AMD next generation graphics processors in a fast-paced environment on cutting edge technology. THE PERSON: Physical design Engineer with strong analytical thinking and problem-solving skills with excellent attention to detail. The candidates should have excellent communication skills, very good team player and ability to drive, lead and mentor team of engineers for project execution. KEY RESPONSIBILITIES: Physical design of complex GPU multi-millions gate design and achieve required performance, area and power targets Work with RTL design to analyze potential bottlenecks for frequency, resolve LOL and timing issue upfront in the project cycle to achieve frequency targets Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Innovus, genus PREFERRED EXPERIENCE: 10+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in leading team of Engineers for design closure Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Experience in RTL design and LOL reduction is preferred Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. Proficient in perl, python, tcl etc ACADEMIC CREDENTIALS: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Orlando FL, Santa Clara CA, Folsom CA, Austin TX, Boston, #LI-PH1 Requisition Number: 176681 Country: United States State: California City: Santa Clara Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. The Role: This is a great opportunity to be part of the next generation GPU chip development team at AMD Santa Clara for ASIC Physical Design engineer. You will join us as Sr. Staff Engineer / Principal Member of Technical Staff. KEY RESPONSIBILITIES: Senior level lead engineer driving PPA improvements in both pre-silicon and post-silicon design phase Drive cross-functional teams (technology, CAD tools, platform characterization , binning practices and design methodology) and optimize margining practices across boundaries to deliver best in class performance/watt Improve low voltage margining methodology and design practices to improve Vmin and performance/watt for low power GFXIP Drive design practices to improve boost frequency for GFXIP Drive silicon correlation and deliver systematic improvements to improve silicon to STA on high performance Graphics IP PREFERRED EXPERIENCE: Over 18 years' experience with BSEE/BSCS or 15+ years of MSEE or MSCE in ASIC Physical Design from RTL to GDSII Excellent analytical and problem-solving skills along with attention to details Strong RTL analysis skills including Verilog, Timing Analysis and library understanding Strong knowledge in design margining methodology, low voltage design, silicon - STA correlation Hands on experience in taping out 5nm, 7nm, 14nm and/or 16nm SOC Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics Strong communication, Time Management, and Presentation Skills Must be a self-starter, and be able to independently and efficiently drive tasks to completion Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player ACADEMIC CREDENTIALS: Bachelor's or Master's Degree in Electrical Engineering, Computer Science, or equivalent is preferred. #LI-PH1 Requisition Number: 181183 Country: United States State: California City: Santa Clara Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD is looking for an engineering leader passionate about driving the best Power, Performance, Area (PPA) of AMD's SoC coherent Interconnects Data Fabrics IPs for next generation AMD AI devices. The ideal candidate will have proven experience in developing scalable complex digital IP microarchitectures to deliver industry leading performance/area and performance/power. In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team, and physical design team to drive the RTL design and microarchitecture of modular network on chip IPs for AMD Data Center silicon SoCs. The candidate will drive new methodologies to build scalable, modular network on chips. You will be a member of a core team of incredibly talented industry specialists and will work with the latest and rapidly evolving hardware technologies for AMD Data Center SoCs. THE PERSON: The ideal candidate has passion for modern, complex microarchitecture, and efficient digital design. Should have demonstrated experience in developing complex highly scalable, modular microarchitectures for SOC with focus on coherent and non-coherent switch fabric IP and must possess leadership and technical skills to influence and drive SOC methodologies to enable delivery of multiple highly complex, high quality, SoCs in shorter time. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: * Technical Microarchitecture lead on AMD Data Fabric RTL design team focused on driving the best scalability, modularity, power, performance, and area * Explore and dive initiatives to achieve best switch fabric scalability, modularity, and reuse across multiple advanced Data Center AI acclerator SOCs * Develop technical relationship with broader AMD design community and peers * Stay informed on latest trends on innovations on switch fabric hardware architecture and implementation. * Close architecture, and micro-architecture requirements, drive technical specifications for Data Fabric IP to meet those requirements, and drive RTL execution * Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop RTL and microarchitecture solutions to achieve requirements * Knowledge sharing and other contributions to AMD Data Fabric architecture and design * Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs * Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: * Experience with highly scalable, configurable switch fabrics (coherent and non-coherent) * Experience with modern heterogenous systems including CPU, GPU, and AI accelerators. * Experience with SOC and IP creation automation for different microarchitectures * Proven track record of defining and delivering complex IP and SOC microarchitectures. * Expert level ability in optimizing and performing tradeoff analysis across multiple domains including PPA, design, microarchitecture, and architecture, verification, and schedule. * Expert of RTL design, Verilog and SystemVerilog * Deep knowledge of front-end tools * experience with synthesis, static timing, DFT * Exposure to physical design and verification methods * Experience with scripting languages such as Perl, Python, Unix shells and Makefiles, and leveraging AI tools to improve improductivity. * Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-systems, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security * Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads * Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture and logic design * Excellent communication, management, and presentation skills. * Adept at collaboration among top-thinkers and senior architects and designers with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering preferred LOCATION: Santa Clara, Ca #LI-MR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate's responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred. THE PERSON: High energy candidates with strong written and verbal communication skills, and structured, well-organized work habits will be successful. Team and goal oriented are essential. KEY RESPONSIBILITIES: * Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff * Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency. * Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA checks. * collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows. * Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts) PREFERRED EXPERIENCE: * Worked with EDA tools that enable RTL quality checks * Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. * Experience with analyzing the timing reports and identifying both the design and constraints related issues. * Ability to multitask, grasp new flows/tools/ideas. * Experience in improving the methodologies. * Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. * Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT) * Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters * Strong analytical and problem-solving skills ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA This role is not eligible for visa sponsorship. #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ Staff ASIC Design Engineer - AI Engineer- 152880 THE ROLE: AMD-Xilinx is seeking a capable and motivated RTL/ASIC design engineer to be part of front-end design team of next generation AI Engine/ML processors. THE PERSON: You will take part in design and implementation of high-performance, low-power processor and accelerator IP for AI/ML applications. KEY RESPONISIBILITES: In this role you will: Define and specify micro-architecture of processor building blocks based on architecture requirements RTL design and debug of complex blocks in Verilog / System Verilog Analyze performance and make implementation choices to optimize timing Analyze and optimize design for power efficiency and power integrity Work with verification and physical design teams to achieve high quality design and successful tape out Solve customer problems through innovative enhancements to product architecture/ micro-architecture Design and implement underlying clocking infrastructures to ensure implementation tool requirements are met and are optimized for compile time and memory Collaborate with cross-functional teams to solve novel problems across multiple functional areas in development of clocking features and/or algorithms PREFERRED EXPERIECE: Strong experience in the following ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes Digital design and experience with RTL design in Verilog/System Verilog Circuit timing/STA, and practical experience with Prime Time or equivalent tools Low power digital design and analysis Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation Experience in following is highly desired Understanding of FPGA architecture and implementation flow TCL, Perl, Python scripting Version control systems such as Perforce, ICManage or Git Strong verbal and written communication skills Ability to organize and present complex technical information Fluent in working with Linux environment Needs to be manually updated. ACADEMIC CREDENTIALS BSEE or equivalent and 8 years of relevant work experience, or MSEE or equivalent with 6 years of experience LOCATION:San Jose, CA #LI-DA1 Requisition Number: 152880 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE We are seeking a SoC Architect to join our adaptive SoC Architecture team. This role is pivotal in defining and driving architecture for next-generation Adaptive SoCs, with on Processor subsystems, Interconnect, AI, GPU, video processing pipelines, and memory systems. THE PERSON You are a seasoned SoC architect with deep expertise in heterogeneous compute systems. You thrive in collaborative environments and bring a system-level mindset to solving architectural challenges. You are passionate about performance, power, and scalability, and have a strong grasp of silicon design trade-offs. You communicate effectively across engineering disciplines and influence architectural decisions with clarity and technical rigor. KEY RESPONSIBILITIES * Drive architecture of key IPs including their PPA tradeoffs, Interconnect, and integration into SoC * Define and optimize SoC control bus protocols, reset flows, clocking strategies, and power domains. * Drive early-stage architectural analysis, modeling, and specification development. * Contribute to architectural innovation for Adaptive SoC Use-cases in AI, GPU, video, and IO domains. * Collaborate with planning, software and hardware cross-functional teams to develop architecture solution. * Collaborate with subsystem architects to ensure cohesive integration and system-level performance. PREFERRED EXPERIENCE * Proven experience in SoC architecture with Processor, Interconnects, and Memory subsystem. * Expertise in AI accelerators, GPU integration, video processing pipelines, and IO subsystems. * Expertise in SoC control bus design, reset architecture, clocking , and power management techniques. * Experience with modeling and automation using Python, SystemC, or equivalent. * Knowledge of advanced process technologies and associated design challenges. ACADEMIC & EXPERIENCE REQUIREMENTS * BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field. * Demonstrated success in delivering high-performance, low-power SoC solutions. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for a self-motivated senior design engineer to be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. As a key contributor, you will focus on RTL design and validation of high-speed interfaces such as chip-to-chip interconnect, both on system and on package, and highly configurable mufti-protocol PHYs. Continuous technical innovation to increase productivity, to heighten quality of results, and to foster career development is integral to the role. THE PERSON: You have a passion for digital design. You are a team player. You have strong analytical and problem-solving skills. You are willing to learn and ready to take ownership of problems. KEY RESPONSIBILITIES: * Perform RTL design of the digital components. * Develop and validate timing constraints involving multiple clock domains while working with physical design to harden IP * Help lead and mentor other engineers to achieve project goals and organizational growth. * Work with a functional (design) verification team to meet coverage and quality standards. * Analyze/fix Lint and CDC/RDC errors of the components. * Guarantee quality/timely deliverables meeting project's schedule. * Help to improve and automate design process. * Support post-silicon product bring-up/debug. PREFERRED EXPERIENCE: * Strong experience in designing digital components for high performance, low power SOC/FPGA. * Design of digital circuits and components using Verilog/System Verilog * Creating and maintenance of timing constraints for complex multi-clock designs * Debugging in digital and mixed-signal simulation environment. * Power-optimization of digital designs. * Multi-clock domain designs. * Experience/Knowledge of High speed SerDes/Physical layer is a plus * Logic synthesis, timing closure, logical equivalence checking and ECOs. * Scripting languages such as Perl, Tcl, or Python. * Collaboration with verification team. * Excellent verbal and interpersonal communication skills. * Excellent technical communications. Ability to produce technical documentation. * Exhibit strong ownership of tasks and responsibilities. ACADEMIC CREDENTIALS: * Bachelors or Masters degree in Electrical Engineering with relevant industry experience LOCATION: San Jose, California #LI-TB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: A senior technical contributor that drives end-to-end delivery of SerDes solution directly contributing to and coordinating implementation and optimization across multiple teams. The position will involve interfacing with software and hardware engineering teams and AMD partners to plan, develop and optimize use cases. This is an exciting opportunity to work on the cutting edge of SerDes Technology. THE PERSON: You are a subject matter expert and strong technical contributor with SerDes/PHY experience. You excel as part of a team where communication and team skills are highly valued. KEY RESPONSIBILITIES: As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: * Write microarchitecture and/or design specifications * Design, implement, and debug complex logic designs * Integrate complex IPs into the SOC * Work with other specialists that are members of the SOC Design - Verification, Emulation, STA, and Physical Design teams * Support all front end integration activities (Lint, CDC, Synthesis, and ECO) * Implement design automation via Python or other languages * Collaborate with software and systems teams to ensure a high quality system PREFERRED EXPERIENCE: * Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies * Writing specifications and converting them to design * Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs is highly desirable * Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, and logic equivalence checks. * Experience in low-power design techniques such as clock- and power-gating is a plus * Ability to communicate effectively across all internal groups * Familiarity with scripting languages like Perl or Python or Tcl is a plus * Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) is a plus * Familiarity with security concepts is a plus * Familiarity with software and operating concepts is a plus * Excellent communication and collaboration skills ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in related discipline preferred LOCATION: San Jose, CA, or anywhere in the US #LI-TB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD Serdes Technology Group develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS process. We are currently seeking an analog/mixed-signal design engineer to join our world-class team. THE PERSON: The candidate will be responsible for the design of high-speed ADC-based receivers, DAC-based transmitters, or silicon photonics transceivers. KEY RESPONSIBILITIES: * Define circuit architectures optimized for high bandwidth electrical and optical links * Perform link level simulation in Matlab and/or SPICE to prove the architecture * Perform design and modeling of on-die RF passive components (e.g., inductors and capacitors) and/or optical structures * Design circuit components (e.g., DAC, SAR-ADC, S/H, Analog Front-End, PLL, reference generation, clock distribution) required to implement the architecture in advanced FinFET process PREFERRED EXPERIENCE: * Strong background in analog and mixed-signal circuit design * Strong teamwork and communication skills * History of coming up with innovative circuit design/architecture is a plus ACADEMIC CREDENTIALS: * BS or MS or PhD in Electrical Engineering or Computer Engineering or related equivalent. LOCATION: San Jose, CA #LI-TB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Graphic Memory Controller(GMC) is an IP that delivers into all SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for a design verification engineer in the Dram Controller IP at AMD's Santa Clara, CA Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. This is a highly visible position in a growing team. Leadership opportunity is available. We are seeking a highly skilled Formal Verification Expert to join our talented team as a Staff Engineer and technical lead. This role is crucial to ensuring IP quality through rigorous formal verification processes. THE PERSON: The successful candidate will play a key role in developing verification strategies, leading formal verification team, and collaborating across departments to ensure the highest quality standards. KEY RESPONSIBILITIES: * Lead formal verification team to ensure IP quality and project execution. * Develop and implement comprehensive formal verification plans, including constraint/assertion property development, model development, inconclusive issue resolve and sign off, etc.. * Collaborate with IP architects, hardware designer, verification engineers, and other stakeholders to design efficient formal verification strategies. * Mentor and guide junior engineers in formal verification techniques and best practices. * Communicate results and progress effectively to cross-functional teams, providing insights and actionable recommendations. * Drive continuous improvement in formal verification processes and contribute to the advancement of the organization's verification capabilities. PREFERRED EXPERIENCE: * Proven experience in formal verification and simulation, model checking, and theorem proving applied to complex IP or systems. * Proficiency in formal verification tools such as VC-Formal or JasperGoal * Strong understanding of hardware description languages (e.g., VHDL, Verilog) and/or programming languages (e.g., System verilog, C, C++, Python). ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Santa Clara, CA This role is not eligible for visa sponsorship #LI-SL3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are seeking a seasoned Lead Design Verification Engineer with expertise in verifying networking chip. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead verification teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: We are seeking an experienced and hands-on Lead Design Verification Engineer to drive the verification strategy, methodology, and execution for our next-generation high-performance networking chip. The ideal candidate will have deep expertise in SoC/ASIC verification, strong knowledge of networking protocols and architectures, and a proven ability to lead verification teams in a fast-paced environment. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: * Ownership of verification strategy for one or more major IP blocks or subsystems within a complex networking ASIC. * Architect and implement testbenches using UVM/SystemVerilog, ensuring maximum coverage and quality. * Develop and maintain test plans, coverage models, and scoreboards to ensure comprehensive verification of all design features. * Lead and mentor a team of DV engineers - drive reviews, define milestones, and ensure high-quality deliverables. * Collaborate closely with design, architecture, and software teams to define verification requirements and debug issues across the full chip. * Develop and maintain automation and regression infrastructure, including CI/CD integration. * Drive coverage closure and signoff for IP and SoC-level verification. * Contribute to methodology improvements, verification IP reuse, and best practices across the DV organization. * Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements * Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: * Proven line management experience, including hiring, mentoring, and performance management of DV engineers. * Demonstrated ability to build and lead high-performing verification teams, setting goals and driving execution across projects. * Experience with chip-level verification for networking ASICs, switches, or routers. * Familiarity with traffic generators, packet-level verification, and network protocol stacks. * Knowledge of SystemC, C testbenches, or hardware/software co-verification. * Exposure to emulation or FPGA prototyping environments (e.g., Palladium, Veloce). * Prior experience leading cross-site or multi-IP verification efforts. * Strong communication, collaboration, and leadership skills with the ability to influence technical direction across disciplines. ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in related discipline preferred LOCATION: Santa Clara, CA This role is not eligible for VISA sponsorship #LI-BW1 #LI-hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD/Xilinx programmable devices. THE PERSON: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: * Collaborate with architects, hardware and firmware engineers to understand the new features to be verified * Take ownership of block level verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes * Review functional and code coverage metrics to meet the coverage requirements * Develop and improve existing verification flows and environments PREFERRED EXPERIENCE: * Strong understanding of computer architecture and logic design * Knowledge of Verilog, system Verilog and UVM is a must * Familiarity with common security protocols and algorithms, including hashing, digital signatures, and encryption standards like AES and SHA. * Strong understanding of computer architecture and logic design * Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification * Working knowledge of C/C++ and Assembly programming languages * Exposure to scripting (python preferred) for post-processing and automation * Experience with gate level simulation, power and reset verification ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are seeking a highly motivated and experienced Senior Silicon Design Engineer to join our AECG SIT team. This role involves leading and contributing to the design, integration, and characterization of advanced silicon testchips for FPGA products across cutting-edge process nodes. THE PERSON: You are an expert in IC design and manufacturing including analog/digital IP integration, chip design, silicon process or packaging technologies. A good understanding of foundry technology PDK, device physics, reliability and silicon chip manufacturing is essential. The candidate must also demonstrate effective communication, good interpersonal skills, along with a strong interest in emerging technologies and innovation. KEY RESPONSIBILITIES: * Facilitate the design and seamless integration of custom digital and analog blocks. * Support functional, timing and EMIR verification of IP blocks in custom design flow. * Collaborate cross-functionally with layout designers, IC design teams, foundry partners, CAD engineers, and test teams to ensure seamless integration and execution. * Develop end-to-end test solutions, including board-level and system-level design, for advanced test vehicle initiatives. * Assist with the bring-up and debugging of testchip silicon in lab environments. PREFERRED EXPERIENCE: * Strong foundation in circuit design and semiconductor device physics and reliability. * Hands-on experience in designing and validating circuits across advanced technology nodes such as FinFET and Gate-All-Around. * Working knowledge of digital P&R design and verification. * Working knowledge of 2.5D and 3D stacked silicon and advanced package assembly technologies. * Experience with usage of major EDA tools for device model, layout, circuit simulation, parasitic extraction, and physical verification. * Working knowledge of PCB/package design and signal/power integrity (SI/PI) analysis. * Proficiency in C/C++ and Python for programming and scripting tasks. Exposure to AI-based coding tools (e.g., GitHub Copilot) is a plus. * Hands-on experience with silicon bring-up and lab bench test equipment. ACADEMIC CREDENTIALS: Preferably holds an advanced degree (PhD or MS) in electrical & electronics engineering or physical sciences; alternatively, a bachelor's degree with 5+ years of relevant industry experience is acceptable. LOCATION: San Jose, California #LI-DR1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is an opportunity to join a dynamic and growing team of engineers developing high-speed PMA layer IP for industry-standard protocols. The successful candidate will be a highly self-motivated and results-oriented member of a small team of engineers that can learn and improve existing digital flows. The candidate will primarily be responsible for front-end coding, scripting and developing flows at all phases of the digital design and functional verification. It is further expected that the candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with the digital, analog and application teams. Candidate should be willing to work full time in the San Jose office. A Cadence satellite office (if senior with extensive SerDes exp.) will be considered. Position Requirements This team is focused on DSP and/or High Speed Serdes. The ideal candidate will have at least 10 plus years of actual work experience in SerDes as well as a thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status. This includes but is not limited to: Digital microarchitecture definition and documentation RTL logic design, debug and functional verification Strong background in DSP and algorithms is a plus. Familiar with the PMA/PMD/PCS layers of the Ethernet protocol is a plus. Understanding of digital architecture trade-offs for power, performance, and area Understanding of proper handling of multiple asynchronous clock domains and their crossings Understanding of Lint checks and proper resolution of errors Understanding synthesis timing constraints, static timing analysis and constraint development Understanding of fundamental physical design flows and stages Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow. Exhibit excellent communication skills and be self-motivated and well organized. Experience with FPGA and/or emulation platform is a plus. Firmware development of embedded microcontroller systems is a plus. Substantial experience with Verilog is required, as are excellent logic and debug skills. Engineering expertise in mixed-signal IP development procedures and Ethernet connectivity protocol knowledge are also strongly preferred. #LI-MA1 The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. At Cadence, we hire and develop innovators and leaders who want to make an impact on the world of technology. We offer amazing opportunities to grow, no matter where you are in your career. The ideal candidate will be energetic, innovative and enthusiastic about how to help customers solve their toughest verification problems using Cadence technology. Join our elite application engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces year after year! As an integral member of the North America Verification Field Applications Engineering (AE) Team, you will work directly with industry leading semiconductor and system companies to deploy Cadence's market leading verification platforms including cutting edge technologies using AI assistants, Agentic AI and machine learning. In this customer facing role you will provide the front line technical support in the pre and post-sales process and will work with the account team to come up with innovative solutions to address our customers' most challenging problems in verification. You will own customer success! In this role, you will develop customer specific verification requirements, including advanced verification component development, methodology support, and operation and maintenance of Cadence's verification tools and services. You will support technical evaluations and benchmark development for Cadence's market leading tools such as Xcelium simulation platform and Verisium platform of AI and ML tools for enhanced verification. You will create and conduct technical presentations and product demonstrations for customers. At Cadence, customers are at the heart of everything we do. Talented engineers like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in verification tools, unlock unique expertise in verification methodologies, and level up your communication, customer, and sales skills. No matter where you are in your career, whether your next career step is to stay on the technical track, move up in management, or explore sales/marketing career opportunities, the skills and expertise you gain as an Application Engineer here at Cadence will put you miles ahead in your career advancement. Key Responsibilities: * Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support * In collaboration with R&D, provide in-depth technical assistance to help support advanced verification flows and AI/ML applications to secure design wins * Champion the customer needs and work closely with R&D and marketing to develop competitive and creative technical solutions * Understand the competitive landscape and continuously work on differentiating Cadence's solutions * Write technical product literature such as application notes and technical articles * Review new product proposals and device specifications * Assume technical leadership roles in small teams as needed Requirements: Minimum: BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field 5+ years experience with SystemVerilog, VHDL, Verilog Verification skills such as UVM testbench architecture, development and debug Strong RTL and Testbench debug skills Experience in writing scripts (Perl, Python or Tcl) Strong software, HDL design and verification skills Ability to quickly analyze verification environments and design complexity Strong verbal and written communication skills Strong teamwork skills Ability to interact effectively with both external customers and R&D teams Preferred: Experience with C/C++/SystemC Experience in deploying VIP in testbenches Knowledge of protocols like JTAG, UART, PCIe, AMBA, DDR Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing Digital design experience The annual salary range for California is $143,500 to $266,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.