Product Design Engineer jobs at Cadence Design Systems

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is the leader in hardware emulation-acceleration technologies and products. Our emulation-acceleration system platform is the most advanced industry-leading configurable scalable system, generation after generation, used in labs and datacenters. Looking for a hands-on Principal Thermal Mechanical Engineer who wants to expand their scope and grow their career. This position is located in our San Jose headquarter office, reports to the Mechanical Engineering Director, and works in a talented organization. This position requires to do thermal analysis, design, and testing; mechanical component and platform enclosure design, thermal and mechanical component specifications, board layout design, mechanical drawings, product documentation, supplier/manufacturer interface, quality inspection, and some hand-on works. Key responsibilities Perform component and system thermal analysis. Design thermal solutions for air-cooled and liquid-cooled products. Perform thermal testing and provide thermal assessment/recommendations. Specify thermal and mechanical components. Design mechanical components and platform enclosures. Perform circuit board layouts and placement of electronic components on circuit boards. Draft 2D drawings of circuit board layouts, mechanical components, and system assemblies Structure BOMs and generate ECRs to release products to PDM. Work with suppliers/manufacturers to address DFM feedback. Perform inspection of materials and resolve quality issues. Perform some hand-on works (prototype build, mechanical assembling, cable routing…) Qualifications BS or degree in mechanical engineering with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience Experienced in thermal and mechanical design of equipment designed to operate in data centers. Experienced with thermal analysis and thermal simulation tools (CFD) Experienced with air and liquid cooling design, and thermal testing. Experienced designing circuit board layouts, sheet metal parts and mechanical components Proficient in using mechanical CAD software. Experienced with Creo Elements/Direct is a plus. Familiar with BOM structuring and ECO processes. PTC Arena (PDM) experience is a plus. Experienced with GD&T is a plus. Experienced using hand tools and operating machining equipment is a plus. Good cross-functional communications. Strong work ethic. Great team-work attitude. The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at ************** and on LinkedIn and Twitter (X). Employer: Analog Devices, Inc. Job Title: Senior Engineer, Product Applications Job Requisition: R257895 Job Location: San Jose, California Job Type: Full Time Rate of Pay: $164,115.00 - $187,680.00 per year Duties: Create and present training and education material for other ADI Engineers and customers on product design, application, and service information. Define, develop and support new products or technologies, which may include hardware reference designs or software. Drive, define and approve customer facing collateral, documentation and application notes. Design, lay-out, build, and test application boards to validate products, and develop demonstration systems to show-off industry-leading features to potential and existing customers. Provide technical support to customers to secure design-ins and sales for their assigned portion of the product portfolio. Support customer visits to qualify new opportunities or features, resolve customer issues and define new product ideas. Mentor Jr. Level Engineers. Recommend actions to resolve quality or performance issues. Perform system architecture analysis. Perform hardware, software, and system testing, debugging, and troubleshooting. Report design, reliability and maintenance problems or bugs to product team. Design models and/or use system modeling or test tools to facilitate development. Partial telecommute benefit (2 days/week work from home). Experience and skills may be gained in a graduate program. Requirements: Must have a Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering or closely related technical field (willing to accept a foreign educational equivalent) and two (2) years of experience as an Applications Engineer or related occupation performing hardware, software, and system testing, debugging, and troubleshooting in the development of power, mixed signal, or electronic products as part of a cross-functional project team. Demonstrated understanding of analog circuitry, DC-DC converter topologies, and control theory. Demonstrated Expertise (“DE”) using ADCs, DACs, amplifiers, analog and digital filters, I2C, SPI, microcontrollers, circuit design, or PCB layout; collaborating with firmware/API/GUI development teams to guide software integration; or testing PCBs to validate products and demonstrate IC performance. DE designing, debugging evaluation kits, test boards, and reference designs, and automating bench testing of new ICs for device operation, including measurement collection and software authoring using oscilloscopes, power supplies, and DMMs. DE creating customer facing collateral, documentation and application notes and facilitating resolution of customer issues. DE either programming using C, C#, Visual Basic, Python, MATLAB, or LabView, or familiarity with circuit simulation tools such as SPICE. Proficient in development of training materials for other engineers and customers on product design, application, and service information. Contact: Eligible for employee referral program. Apply online at https://**************/en/about-adi/careers.html and Reference Position Number: R257895 . For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. Job Req Type: ExperiencedRequired Travel: NoShift Type: 1st Shift/Days Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at ************** and on LinkedIn and Twitter (X). Employer: Analog Devices, Inc. Job Title: Senior Engineer, Product Engineering (Mfg.) Job Requisition: R252068 Job Location: San Jose, California Job Type: Full Time Rate of Pay: $134,679.00 - $158,865.00/year Duties: Manage new product introduction and production support engineering for a specific product or group of products after transfer from design to in-house or outsourced production. Interface with design, process, test, reliability, and manufacturing engineering to solve product issues and production problems. Develop and sustain process improvements to reduce production costs and increase yields. Perform Yield Enhancement root cause analysis and Failure Analysis on a variety of analog and mixed signal integrated circuits. Define problems by identifying failure modes, quantity of material affected, percent fallout, etc. Perform data analysis, problem characterization, fault isolation, and physical failure analysis to determine the root cause of the problem. Support product reliability qualification testing and analysis, and package qualification testing and analysis. Conduct low yield failure analysis for process transfer and product transfer between fabrications. Partial telecommute benefit (2 days WFH). Requirements: Must have a Master's degree in Electrical Engineering, Materials Engineering, Physics or related field of study (or foreign education equivalent) and two (2) years of experience as a product engineer or related occupation performing solid circuit debugging and physical failure analysis. Must also possess the following: • Demonstrated Experience (DE) performing mixed integrated circuit (IC) and sensor modeling and simulation using Candance, Console, and Advanced Design System (ADS); • DE monitoring manufacturing process (Work in Process "WIP"), gathering test and process data for analysis to identify the failure models and potential root causes through shop floor control and yield management system such as ACE, or Excensio; • DE synthesizing ECAD, product datasheets and process design rules for new products and existing products; verifying schematics and layouts to determine electrical properties, and set up the test bench per customer document or failure analysis requirement; and • DE conducting physical non-destructive and destructive analysis using X-Ray, mechanical and chemical de-processing, mechanical cross-sectioning (such as Buehler, RIE, or Elite) on microelectronics or mixed IC, metallographic analysis, Scanning Electron Microscope "SEM", and element analysis (such as Energy Dispersive X-ray "EDX" or FIB). Experience and skills may be gained during a graduate program Contact: Eligible for employee referral program. Apply online at https://**************/en/about-adi/careers.html and Reference Position Number: R252068. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. Job Req Type: ExperiencedRequired Travel: NoShift Type: 1st Shift/Days Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. KEY RESPONSIBILITIES: * Develops characterization and silicon validation plans for high speed transceivers * Defines methodologies for characterization and silicon validation of high speed serial systems * Characterize high speed SERDES with automated flows * Data analysis and create characterization reports * Correlation of pre-silicon results with silicon measurements * Drives direct and cross-functional teams to expand capability, productivity and effectiveness to deliver improvements in cost, quality and manufacturability PREFERRED EXPERIENCE: * Experience in characterizing PLL, CDR, TX/RX analog front-end * PLL phase noise measurement, transmitter output jitter measurement, receiver jitter tolerance measurement * Hands on experience in laboratory environment, using lab equipment such as sampling oscilloscope, high performance BERT, logic analyzers, spectrum analyzers, BERT scopes, function/pulse generator * Experience in transceiver electrical compliance testing (PCIE, IEEE 802.3, OIF-CEI) * Experience in using automated methodologies to maximize use of equipment * Experience working with FPGA and/or SOC Architectures * Understanding of PCB schematic and layout * Strong analytical, problem-solving and debugging skills * Experience in protocol testing (PCIE, SATA, SGMII, 100GBASE-X) * Skills: Verilog, Python, Perl, TCL ACADEMIC CREDENTIALS: BSEE/MSEE with extensive experience in product characterization or validation field LOCATION: San Jose, CA This role is not eligible for visa sponsorship. #LI-TW2 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Developer Productivity Engineer THE ROLE: AMD is seeking a Developer Productivity Engineer with a Gradle focus to strengthen our build performance and release reliability for complex, multi-repo systems. You will standardize shared Gradle plugin conventions, optimize task graphs and caching, and orchestrate releases across Dev/QA/Stage/Prod with automated notes and SBOMs. You'll collaborate closely with Security on hotfix and CVE remediation workflows, operate GitHub Actions runners and/or Jenkins at scale, and manage artifacts in Artifactory/Nexus-all while advancing Release-as-Code and working with the latest hardware and software stacks. THE PERSON: You are passionate about modern CI/CD and large-scale build systems, with the leadership to drive sophisticated build and release issues to resolution. You communicate clearly, partner effectively across engineering, QA, and security, and mentor teams on best practices. You bring deep experience with Gradle (or are eager to specialize quickly), strong Git skills, and hands-on problem solving. C/C++ build experience and familiarity with EDA flows are pluses, as are cloud platform certifications (AWS/Azure/GCP) and experience operating self-hosted GitHub Actions runners. KEY RESPONSIBILITIES: Build System Engineering * Develop and maintain Gradle plugins (Java/Kotlin/Groovy) and shared build conventions. * Optimize task graphs, caching, and build performance; migrate legacy builds (Maven/Ant) to Gradle. * Debug dependency issues, annotation processors, and incremental build/cache misses. CI/CD and Infrastructure * Drive Release-as-Code; integrate gates (tests/security scans); manage GitHub Actions runners and/or Jenkins. * Containerize release tooling (Docker/K8s/Helm) when appropriate. Leadership and Enablement * Serve as SME and mentor for build/release topics; document plugin APIs and developer self-service patterns. Release Orchestration and Governance * Define branching/versioning/tagging, manage promotion across Dev/QA/Stage/Prod, and automate release notes/SBOMs. * Manage artifact repositories (e.g., Artifactory/Nexus), retention, and immutable release bundles. Patch and Security Response * Design hotfix/patch workflows; coordinate cherry-picks across maintenance brances; ensure timely CVE remediation. PREFERRED EXPERIENCE: * Strong object-oriented programming background, C/C++ preferred. * Solid experience in Release/Build/DevOps engineering with enterprise-scale CI/CD. * Expert-level Gradle or equivalent large-scale build system experience; hands-on custom plugin development preferred. * Deep GitHub and GITHub actions expertise; Perforce experience a plus. * Proven track record managing complex release trains, Day-2 operations (patching/hotfix), and artificial lifecycle. * Proficiency with Artifactory/Nexus; CI/CD (GitHub Actions and/or Jenkins); containers (Docker/K8s). * Experience with Windows, Linux and/or Android operating system development. * Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus. * Effective communication and problem-solving skills. ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent This role is not eligible for visa sponsorship. #LI-GW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ MEMBER OF TECHNICAL STAFF, PRODUCT ENGINEER THE ROLE: As a member of a highly seasoned Product Engineering team, the successful candidate will work closely with several R&D teams, internal application design teams and tier-1 customers to improve the Programmable Logic and overall SoC Partial Reconfiguration user experience and enable the next generation of designs across the UltraScale and Versal ACAP device families. THE PERSON: The Product Engineer position is in the Software & AI Products group and seek an experienced application engineer to focus on FPGA & ACAP design and compilation tools, ease-of-use, SW features specification, first-pass validation, documentation and key customers engagement. KEY RESPONSIBILITES: Drive or contribute to key product areas, such as design planning, partitioning, floorplanning, implementation, configuration and verification. Handle key customer escalations from analysis to closure, while collaborating with the Field team. Contribute to triaging reported issues in several Vivado product areas, such as design entry, floorplanning, programming, and help engineering address them effectively. Actively explore innovative methodologies, their impact on flow and design practices, with emphasis on design closure with clear messaging and DRCs, as well as productivity with the new Versal ACAP family. Work closely with AMD Business Units (Data Center, Wired, Wireless, Emulation & Prototyping, Test Equipment) to improve their designs, products and customer experience. Develop and deliver training materials on new features and methodologies. Stay current with and propose the internal use of industry approaches, algorithms, and practices. PREFERRED EXPERIENCE: Customer Awareness: Has excellent working knowledge of RTL-based design flows and expectations. Product Knowledge: Has good working knowledge of the entire FPGA or ASIC design process and tool flow, with intermediate-to-advanced understanding in timing analysis and closure. Scripting experience (Tcl, Python) is desired. Design Enablement: Has good understanding of design methodologies for design partitioning, floorplanning and verification. Problem Solving: Ability to handle and solve complex system level issues. Technical Communication: Can simplify and communicate even the most complex subjects, making options, tradeoffs, and impact clear. Can report out to management in a concise and actionable manner. Able to work with several teams across sites and domains with a positive attitude under variable workloads. ACADEMIC CREDENTIALS: MS or equivalent work experience in Electrical Engineering or similar technology area LOCATION: San Jose, Ca. #LI-JT1 Requisition Number: 182401 Country: United States State: California City: San Jose Job Function: Product Engineering Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. ***POSITION CAN BE DONE REMOTELY FROM U.S. AND CANADA*** THE ROLE: AMD is looking for a seasoned Member of Technical Staff Product Development Engineer with extensive experience in HW/SW system design and methodology to help boost design productivity and performance across current and future AMD Versal ACAP platforms. Versal ACAP combines ARM processors, programmable logic (FPGA), AI engine arrays and numerous cutting edge memory and connectivity IPs, assembled to deliver powerful heterogeneous acceleration for any application. The Product Engineer position is in the ACAP Interactive Design and Compilation Tools applications team, and is located in North America, preferably in Longmont CO or San Jose CA. THE PERSON: The successful candidate will work closely with several AMD software and hardware R&D teams to improve the current Vivado design creation experience and enable higher productivity for the next generation of designs across key markets (5G, wired communication, test & measurement, video, machine learning). The candidate will own one or several product areas, such as for example IP Integration, addressing, IP wizards, design project & infrastructure, compilation & simulation flows, which are major components of the Vivado design ecosystem. KEY RESPONSIBILITIES: Deep-dive on new and critical tool issues seen by customers or internal AMD teams, to identify work-arounds and drive resolution in future releases aiming at boosting. Interact with the Field team to review proposals and schedule. Work closely with Marketing and Engineering on tools specifications for Vivado and for the next generation Design and Compilation Tools. Develop and deliver training materials on new features. Interface with Senior Management, Quality, Tech Marketing and Application teams to ensure issues are resolved and corrective actions completed. Use HW/SW system design experience to drive methodologies, illustrate best practices by developing design examples, tutorials, short videos and demos. Stay current with and propose the internal use of industry approaches, algorithms, and practices. PREFERRED EXPERIENCE: Customer Awareness: Has excellent working knowledge of system design flows and expectations Product Knowledge: Has excellent working knowledge of the entire FPGA or ASIC design process and tool flow, with expertise in AXI or equivalent protocols, system software dependencies, Linux. Has hands-on experience with HDL, Tcl (or Python), physical implementation flows and verification tools Design Enablement: Expert in design performance analysis, verification methodologies, and demo creation Problem Solving: Ability to handle and solve complex system level issues, internally and with tier-1 customers Technical Communication: Can simplify and communicate complex subjects, by articulating options, tradeoffs, and clarifying potential impacts ACADEMIC CREDENTIALS: MS or equivalent work experience in Electrical Engineering or similar technology area, with minimum 8 years of relevant experience desired #LI-JW2 Requisition Number: 179362 Country: United States State: California City: San Jose Job Function: Product Engineering AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. PRODUCT DEVELOPMENT ENGINEER 2 THE ROLE: The Product Engineer position is in the Interactive Design and ACAP Compilation Tools applications team, located in Longmont, Colorado, USA, for a skilled and self-motivated engineer to focus on tools specification, early validation, training, documentation and key customer support. The successful candidate will work closely with several Xilinx software R&D teams, including IP, embedded processing, infrastructure, flow and GUI to improve the Vivado design entry experience and to enable higher design productivity for the next generation of designs across markets (5G, communication, test, acceleration, machine learning) and Xilinx devices. KEY RESPONSIBILITIES: Assist with defining specifications and propose creative solutions for future FPGA and ACAP SoC devices support or to solve existing persistent and pervasive customer issues Adopt proper tool methodology, and illustrate best practices via examples, tutorials and demos based on a diversity of HW designs Explore critical tool issues seen by customers and help identify workarounds and future enhancements Track, prioritize, and assign reported tool issues to the appropriate engineering teams Participate in cross functional meetings with other engineering, marketing and quality teams to ensure issues are resolved efficiently Author intuitive documentation tuned to the needs of the reader for their areas of expertise Continuously learn about complimentary Xilinx technologies, such as Vitis, HLS, System SW, Alveo boards Stay current with and proposing the internal use of industry approaches, algorithms, and practices PREFERRED EXPERIENCES: Customer Awareness: Has working knowledge of system design flows and expectations Product Knowledge: Has working knowledge of FPGA or ASIC design processes, tools and flows, and has exposure to AXI protocols, system software dependencies, and Linux. Has hands-on experience with HDL, Tcl (or Python), physical implementation flows and verification tools. Hands-on Vivado experience is a benefit but not strictly a requirement. Design Enablement: Experience with performance analysis, verification methodologies, and demo creation Problem Solving: Assist with solving complex system level issues with tier-1 customers Technical Communication: Can simplify and communicate complex subjects, by articulating options, tradeoffs, and clarifying potential impacts Beneficial Skills: Experience with embedded hardware systems, Linux based operating systems, system software, and device tree generation. Hardware design experience with Verilog, SystemVerilog, or VHDL are also beneficial. ACADEMIC CREDENTIALS: MS or equivalent work experience in Electrical Engineering or similar technology area, with minimum 2 years of relevant experience #LI-JY1 Requisition Number: 152968 Country: United States State: California City: San Jose Job Function: Product Engineering Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ The System Validation team plays a key role in validation of complex SOCs in pre-silicon and post silicon. Our most recent project Versal ACAP, a fully software-programmable, heterogeneous compute platform that combines Scalar Engines, Adaptable Engines, and Intelligent Engines to achieve dramatic performance improvements with dual core ARM processing system and Programmable logic is known for Industry's first Heterogeneous architecture. We are looking for a passionate engineer to work with us on our latest SOC - Versal. We are looking for an aspiring Systems Design Engineer with a strong background in software to join the System-level Test team in San Jose. As a System Validation Engineering Intern, you will be involved in the silicon life cycle from testing of emulated next-generation RTL through to silicon verification and characterization. You will have a view of the full system but also will become an expert in certain IP down to the register-level. We are looking for someone who can span the range of able to develop device drivers in software to debug on hardware. As an intern on our team, you will gain real engineering experience in working with complex SOC and validation software and make a difference to the quality of our products. Responsibilities Assist in bringing up system level validation tool on new silicon Run regressions and experiments to help root cause issues Enhance existing test software for system-level validation and verification of existing and new FPGA features. Design, develop, implement, test, and verify systems based on FPGAs with embedded Micro Blaze or ARM processors Help to develop novel methods for system-level modeling and verification Help automate design, test, and build processes Qualificiations Must be a student enrolled in a bachelor's or master's degree program in Electrical / Computer Engineering with an emphasis on embedded system development and/or computer architecture Computer Architecture class(es) required Programming languages: C, Python, Verilog To support our group, we are looking for a intern that can commit to a full time (40 hr per week), 4-12-month internship starting in January 2023. You must be able to work onsite at are San Jose, CA Office. Located at 2100 Logic Dr, San Jose, CA 95124 Shorter internships will NOT be considered. Requisition Number: 185604 Country: United States State: California City: San Jose Job Function: Student/ Intern/ Temp Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Graphics Memory Controller (GMC) is an IP that delivers into AMD's Discrete GPU (Navi) and Instinct (HBM) based SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for an experienced, conscientious logic design engineer in the Dram Controller IP at AMD's Santa Clara Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. THE PERSON: The ideal candidate for this role is an experienced and detail-oriented logic design engineer with a strong background in RTL development and a commitment to advancing graphics technologies. With over five years of experience in digital design, they bring expertise in high-speed memory interfaces such as HBM and GDDR and have a proven ability to deliver high-performance designs that meet timing, power, and area requirements. They are proficient in Verilog and familiar with industry-standard CAD tools from Synopsys, Cadence, and Mentor Graphics, with strong skills in simulation, synthesis, and timing analysis. This individual works effectively in dynamic, collaborative environments, communicates clearly across teams, and demonstrates strong analytical and problem-solving abilities. Their initiative and attention to detail make them a valuable contributor to AMD's Santa Clara Design Center, where they will support the development of next-generation discrete GPUs and data center solutions. KEY RESPONSIBILITIES: * Participate in the development of Architecture and Micro-architecture specifications for the Logic components. * Perform logic design, Register Transfer Level (RTL) coding for new features within existing blocks and design new blocks supporting HBM and GDDR DRAM Technologies * Deliver Designs that meet functional and performance requirements, * Deliver Design that meets physical/structural design constraints (timing, area, power) * Work with Verification Engineers to effectively communicate and resolve issues from test plan through feature bring up to coverage closure PREFERRED EXPERIENCE: * Logic design implementation using hardware description language (RTL) * Experience working on DRAM or similar high-speed interfaces is a big plus * Usage/execution of logic simulation, synthesis and familiarity with logic development flows * Strong RTL analysis skills including Verilog, Timing Analysis * Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics * Strong communication, Time Management, and Presentation Skills * Must be a self-starter, and be able to independently and efficiently drive tasks to completion * Excellent analytical and problem-solving skills along with attention to details * Aware of latest Power -aware design methodologies ACADEMIC CREDENTIALS: * Bachelor's or master's degree in computer engineering, Electrical Engineering, or a related field. #LI-DP1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the Graphics and Engineering group, you will help bring to life cutting-edge designs related to Artificial Intelligent/ High Performance Computing SOCs . As a member of the Physical design and SOC teams, you will work closely with the architecture, IP design, RTL design, CAD, silicon technology teams and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: * Physical design and signoff methodology development for advanced nodes and High performance * Automation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environment for an SOC * Full chip / sub-system/ Tile level timing analysis with bleeding edge STA methodologies * Full chip / sub system level Clock tree synthesis and advanced clock tree construction and analysis. * Block and top level Formal verification, Physical Verification and chip finishing methodologies. * Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion, IRdrop and logic equivalence * Statistical and Static Timing Analysis, Variation aware analysis, stdcell Library characterization enhancements * Developing and Integrating ML and LLM applications for Physical Design and Analysis flows * Performing data analysis and identifying design trends * Customizing and implementing solutions for new challenges * Collaborating with multi-site engineering teams to reach project goals * Hands-on in reference flows, excellent debugging skills. * Maintain and update technology collaterals PREFERRED EXPERIENCE: * Experience in ASIC Physical Design and/or CAD development * Hands-on experience with Place and Route, Timing Analysis, and Physical Verification tools from Synopsys, Cadence, like ICC2, Fusion Compiler, DSO.AI, Innovus, Cerebrus, Primetime, Primeshield, PT-PX, Formality, Conformal, RedHawk, etc. * Experience in 5nm and below technologies * Script development, scripting (TCL, Perl, Python, Pandas), ML/AI techniques * Knowledge and Experience in ML and LLM * Experience with data analytics applications, database management ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering This role is not eligible for Visa Sponsorship. #LI-PA1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Join our leading-edge Design and RTL Methodology team as a Hardware Development Engineer, contributing directly to the development of our latest FPGA products. In this role, you will help ensure the highest quality of RTL design that our customers rely on. THE PERSON: You are an experienced, proactive RTL Design Engineer who thrives in a fast-paced environment. You quickly ramp up on new tools and methodologies, and you're comfortable working on a small, highly capable team where you can take on significant responsibility. KEY RESPONSIBILITITES: * Collaborate with the design team to drive continuous improvements in front-end design methodologies, ensuring top-quality RTL across areas such as Lint, CDC, formal equivalence, and low-power verification. * Enhance and develop flows that analyze RTL and Unified Power Format (UPF) Files, including updating or creating new UPF to enable robust verification of power-domain crossings for AMD's next-generation monolithic and stacked FPGA-SoC product families. * Leverage corporate AI systems to increase productivity and streamline workflows. PREFERRED EXPERIENCE: * Proven experience in logic design and static verification (SystemVerilog, Verilog, or VHDL), ideally with contributions to at least two ASIC products brought to market. * Strong background in RTL/logic design, including specifying multi-power-domain architectures using IEEE 1801 Unified Power Format (UPF). * Programming skills in Perl, Python, and TCL. ACADEMIC CREDENTIALS: * Bachelor's degree in Electrical or Computer Engineering; Master's degree preferred. LOCATION: San Jose or other HYBRID office locations. #LI-GW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ SILICON DESIGN ENGINEER 2 THE ROLE: Join a team of silicon design engineers who utilize their skills in logical and physical circuit optimization to innovate and implement programmable logic interfaces. Our team owns the design and implementation from RTL to final layout database delivery, as well as supports silicon validation and characterization. You'll be part of a small and focused design team with a wide scope of responsibilities and technical opportunities using the latest in circuit design tools and methodologies. Your skills will be deployed in simulation, characterization, and model development for circuit performance and power at cell, critical path, and block-level designs. THE PERSON: We are looking for a self-motivated team worker, who possesses good verbal and written communication skills. The ideal candidate strives to tackle challenges in creative ways with solutions that can be applied in a wide range of applications. If you have a drive for high-quality, high-accountability design work, then you will be a great fit for our team! KEY RESPONSIBILITIES: Schematic capture Logical equivalency checks Test bench development Place and route constraint definition Physical design closure in APR tools Critical-path simulations for timing correlation with STA Electrical rule checks commensurate with each stage of the design Generating and characterizing models of circuit timing and power PREFERRED EXPERIENCE: Knowledge in VLSI design, design automation, IC design, and RTL design Knowledge of floor planning, synthesis, place & route, static timing analysis, and EM/IR analysis Knowledge of Cadence SPICE, Synopsys Primetime, and IC compiler preferred ACADEMIC CREDENTIALS: MS (preferred) or BS with additional experience in Electrical Engineering or Computer Engineering or related equivalent #LI-JY1 Requisition Number: 162224 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a design engineer in our CAD and methodology team, you will be responsible for leading and optimizing the EDA environment for Project CAD team in the Adaptive & Embedded Computing Group (AECG). You will oversee the complete SCH-to-GDS flow, manage tool deployments, and drive methodology development across multiple semiconductor projects. This is an opportunity to shape the technical direction of critical IC design workflows and lead a team of skilled CAD engineers. You will advise on tools selection, and interface with various EDA tool vendors and foundries to run the EDA tools, PDKs and other files necessary for the Silicon Development Team to operate efficiently. You will be responsible for defining and creating a unified environment that sets the versions of the tools, PDK and design for every individual chip in development. Additionally, you will interact with the various Silicon development teams who will be requesting newer versions of the tools and raise trouble tickets with CAD vendors as needed. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: * Execute in CAD infrastructure team supporting multiple IC design projects * Establish and maintain standardized design flows and methodologies * Implement and support customized CAD flows for Fabric design groups * Enable the team to meet design and development targets by working closely with external tool vendors * Develop tools flows methodologies on digital back-end domains, sign-off flows for timing, power, EM/IR, DRC/LVS/DFM, etc. * Improve engineering efficiency while improving design quality in IP release process * Be single point contact for bugs and issues for custom and analog physical design team * Build flow in TCL, Python to ensure quality and faster executions * Understand different methodologies used across industry to adopt best practices * Leverage and deploy AMD AI systems to design teams PREFERRED EXPERIENCE: * Proficiency in TCL, Python, PERL, or other scripting languages * Experience with PDKs and technology enablement * Skilled in Spice and PVT simulation environments * Hands-on expertise with Virtuoso-based custom layout tools and flows * Familiarity with Calibre extraction flows and EM/IR analysis using Totem and Redhawk * Working knowledge of SiliconSmart, PrimeTime, and Physical aspect of VLSI designs * Strong written and verbal communication skills ACADEMIC CREDENTIALS: * Bachelor's degree in Computer or Electrical Engineering, or equivalent; Master's degree preferred LOCATION: * San Jose #LI-GW1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This role is an excellent opportunity to work on the cutting-edge next generation technologies that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets. You will join one of the fastest-growing field of Chiplet Interconnect technology rapidly being adopted across the VLSI industry. The team works on supporting both AMD proprietary I/O protocols and is also a key driver for industry standard Universal Chiplet Interconnect Express. The IP portfolio caters to short/ultra-short reach die-2-die interconnect with different bounding boxes tied to beachfront, Power, BER requirements. As a member of this team, you get a chance to work on IP development, drive design-specification, work on digital design and collaborate in the whole spectrum of areas include DFT, Firmware, Design verification, and Physical Design. THE PERSON: Enjoys being an environment where they can grow and learn with sense of team spirit Strong analytical thinking and problem-solving skills, excellent attention to detail. Eager to learn new designs and implementation techniques. Must have good collaboration and interpersonal skills. Excellent communication skills with leadership qualities KEY RESPONSIBILITIES: * Experience with I/O protocols like USB, PCIe, CXL. * Experience in developing micro-architecture for any given module. * RTL design experience with multi-clock, high frequency designs, low latency, low power & high performance. * Debugging/Post Silicon Bring up * Good Documentation and presentation skills. * Micro-architecture of simple to complex digital blocks. * RTL development using best industry practices. * Optimize design for key metrics like Area, Power, Performance etc. * Ability to work with cross-functional teams like DFT, Implementation, Verification, Emulation, Firmware regularly. PREFERRED EXPERIENCE: * Experience in digital front-end implementation, including micro-arch. definition * Experience with scripting/automation languages like Python/Perl * Firmware on Hardware-Firmware co-design * Experience with state-of-the-art industry standard digital tools * Preferred experience in design with multiple clock domains * RTL design experience with multi-clock, high frequency designs * Knowledge in digital RTL Digital Design and Implementation * Experience with Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA) ACADEMIC CREDENTIALS: Master's/Bachelor's in electrical engineering or equivalent preferred LOCATION: San Jose, CA #LI-SL3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ TITLE: Design Engineer At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. THE ROLE: This position is within the AMD SERDES Technology team in San Jose, CA, looking for a talented and motivated team member with a focus on FPGA design and hands on silicon bring-up. You will use your knowledge of high-speed SerDes and design experience to develop various solutions for common high-speed SerDes interfaces and applications. RESPONSIBILITIES: FPGA design and IP solutions development Develop embedded firmware for validation and applications development Work with internal teams to create IP solution, debug features associated with physical layer functionalities Provide customer support and field debugging as required Preferred Skills & Experience: FPGA design and debug experience C/C++ for embedded system development Knowledge of physical layer specifications in IEEE 802.3 and / or PCIe Programming experience in Python or Perl scripting languages Hands-on experience with various lab equipment for silicon bring-up and validation Knowledge of 50G+ multi-level (i.e. PAM4) SERDES is preferred Excellent verbal and written communication skills ACADEMIC CREDENTIALS: B.S. or M.S. Electrical or Computer Engineering preferred Requisition Number: 179684 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

Category Engineering Hire Type Employee Job ID 12583 Base Salary Range $157000-$235000 Remote Eligible No Date Posted 21/08/2025 This position requires access to or use of information, which is subject to export restrictions, including the International Traffic in Arms Regulations (ITAR). All applicants for this position must be "U.S. Persons" within the meaning of the ITAR. "U.S. Persons" include U.S. Citizens, U.S. Lawful Permanent Residents (i.e. 'Green Card Holders'), Political Asylees, Refugees or other protected individuals as defined by 8 U.S.C. 1324b(a)(3). This role is required to work onsite in our Sunnyvale CA location. We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced engineer with a deep understanding of the RTL to GDSII flow. You thrive on solving complex technical issues and enjoy working closely with customers to enhance their experience with cutting-edge technology. With your strong background in synthesis, physical design, and static timing analysis, you excel in diagnosing and resolving technical challenges. You are an excellent communicator, capable of conveying technical concepts clearly and effectively to both technical and non-technical stakeholders. Your scripting skills in Perl, Tcl, and Python, along with your knowledge of CAD automation methods, make you a valuable asset to any team. You are motivated to work collaboratively with internal teams and customers to drive product adoption and satisfaction. What You'll Be Doing: * Providing technical and engineering insight to support and improve the usability, applicability, and adoption of Synopsys products. * Diagnosing, troubleshooting, and resolving complex technical issues on customer installations. * Deploying and training customers on new implementations and capabilities. * Reviewing and acting upon product feedback and solutions performance from customers and other application partners. * Working directly with R&D to develop and implement the technical roadmap, specifications, and validation for improvements and enhancements. * Partnering with customer technical managers and Sales to identify business challenges and develop effective technical solutions for new accounts. The Impact You Will Have: * Enhancing customer satisfaction by ensuring seamless product deployment and support. * Driving product adoption and utilization through effective technical training and support. * Contributing to the technical roadmap and product improvements based on customer feedback. * Supporting the sales team in acquiring new accounts by providing technical expertise. * Improving product performance and reliability through collaborative efforts with R&D. * Strengthening customer relationships by addressing and resolving technical challenges promptly. What You'll Need: * 7+ years of RTL to GDSII full flow experience or knowledge. * In depth experience debugging complex engineering issues related to STA, DRC/DRV and PPA optimization * Exceptional interest and knowledge of Advanced Node & Design methodologies. * Proven aptitude and motivation to work with internal and customer groups. * Excellent verbal and written presentation/communication skills. * Hands-on experience in synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis. * Knowledge of ASIC implementation domains outside of RTL2GDS including RTL coding, Verification, formal checking is a plus. * Good scripting skills (Python, Tcl, Perl); working knowledge of CAD automation methods. Who You Are: * A collaborative team player who thrives in a dynamic environment. * An excellent communicator with the ability to convey complex technical concepts effectively. * A proactive problem-solver with a keen eye for detail. * Customer-focused, with a passion for delivering exceptional service and support. * A continuous learner, always seeking to expand your technical knowledge and skills. The Team You'll Be A Part Of: You will be part of a highly skilled and dedicated team of engineers focused on providing exceptional technical support and solutions to our customers. Our team collaborates closely with R&D, Sales, and Customer Success to drive product innovation, adoption, and satisfaction. We value continuous learning, open communication, and a customer-centric approach in everything we do. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

Category Engineering Hire Type Employee Job ID 13867 Base Salary Range $109000-$163000 Remote Eligible No Date Posted 20/12/2025 At Synopsys, we drive the innovations that shape the way the world connects and computes. Our technology powers cutting-edge silicon in applications from mobile and AI to autonomous systems and advanced computing. Join us to help customers achieve breakthrough performance using our leading EDA tool suite. We are seeking a Physical Design Engineer with strong technical skills in digital implementation and optimization. In this role you will work with engineering teams and customers to deliver solutions that drive timing closure, power and area optimization, and robust RTL-to-GDS flows using Synopsys tools. You Are You are an ASIC/physical design engineer with 2-4 years of hands-on experience in digital implementation flows. You understand full RTL-to-GDS design flows and are comfortable applying state-of-the-art methodologies to achieve timing closure and quality signoff. You have solid scripting skills to automate flows and customize solutions, and you communicate clearly with internal teams and customers to solve complex design challenges. What You'll Be Doing * Execute RTL-to-GDSII digital implementation flows, including logic synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off quality closure. * Work with customers and internal teams to troubleshoot and optimize implementation challenges, propose solutions, and deliver highly-tuned PPA results. * Utilize Synopsys tools such as Fusion Compiler, PrimeTime, and DSO.ai/FusionAI in digital implementation and static timing analysis. * Develop and enhance automation scripts and flows using TCL, Python, Perl, or other scripting languages. * Perform static timing analysis (STA), debug timing violations, and implement ECOs to improve performance and timing closure. * Drive DRC/LVS/Signoff quality closures at advanced technology nodes. * Collaborate with customers, product teams, and research groups to share best practices and feedback to improve tool flows. What You'll Need * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. * 2-4 years of hands-on experience in digital physical design or backend implementation. * Experience with full RTL-to-GDS flows, including place & route methodologies, STA, timing closure, and signoff strategies. * Proficiency with Synopsys tools such as Fusion Compiler, PrimeTime, and familiarity with AI-assisted optimization tools (e.g., DSO.ai/FusionAI) is highly desirable. * Solid scripting skills in TCL, Python, Perl, or equivalent for flow automation. * Strong analytical ability to dissect complex timing, PPA, and design challenges. * Familiarity with unix/linux environments and engineering workflows. * Excellent communication skills and ability to work in collaborative team and customer-facing environments. Who You Are * A proactive self-starter who takes ownership of technical solutions and delivery. * Comfortable interfacing with customers and internal teams to understand requirements and deliver effective outcomes. * Able to adapt to evolving methodologies and rapidly learn emerging tool capabilities in EDA. * Detail-oriented and organized, capable of balancing multiple priorities in a fast-paced environment. The Team You'll Be Part Of Join a dynamic Applications Engineering team dedicated to customer success and powerful EDA solutions. You'll work closely with fellow engineers, researchers, and tool developers to enable high-performance physical design solutions and push the boundaries of what's possible in semiconductor design. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Are you looking to re-enter the workforce as a Physical Design Application Engineer after taking a career break for caregiving? Who is eligible to apply: Please ONLY consider applying if you are a Physical Designer and (IMPORTANT) who has been out of the workforce for caregiving for a period of at least two years and have a minimum of three years of Physical Design work experience. This role is not open to new college grads or interns. Please check our career site for those roles. Cadence is offering an opportunity to qualified candidates who meet our eligibility criteria to participate in a 16-week paid returnship program. You will be entered in a tailored program designed to jump start your skills through training, hands on projects and customer interaction. You will have an opportunity to update your resume, build connections and participate in fun events as you re-enter the workforce. In this program, you will work with best in class EDA tools, collaborate with R&D and the Sales team in a dynamic, innovative environment. Learn processes that are in the forefront of technology, how a company like Cadence works as well as experience how teams solve problems. We are seeking individuals with experience in Digital Synthesis, Place and Route and Signoff Analysis. Where is this returnship located: San Jose, CA What opportunity is offered: Candidates will find opportunities to be in the Application Engineering field spanning across Digital Synthesis, Place and Route and Signoff Analysis. How long is this returnship: 16 weeks Company Description: At Cadence, our core values are more than just words, they are the way we work, laugh, debate, care, question, and innovate together. We are One Cadence-One Team. Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation (EDA) company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Our team's shared passion for solving the world's toughest technical challenges and drive to do meaningful work makes us proud to be part of Cadence. Our unique culture has been recognized on FORTUNE Magazine's 100 Best Companies to Work For list and garnered accolades from the Great Place To Work Institute around the globe. #LI-MA1 The annual salary range for California is $59,500 to $110,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.