Design Engineer jobs at CCI Systems - 648 jobs

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering The DTECH team is part of the Global SOC organization and is responsible for STA methodology and signoff, foundry technology enablement and analysis, design automation and internal and external EDA tools, design analysis and optimization tools and platforms, low power architecture, methodology, and IP, and foundation IP development. About the Role As a member of the DTECH Methodology team, you will work closely with core and SOC teams to enable a state-of-the-art design analytics platform. Your work will have a consequential impact on the power, performance, area, and quality of Qualcomm's products. Required for this Role M.S/Ph.D. degree in Electrical Engineering or Computer Science with 1-2 years of relevant experience with ASIC/VLSI design tools and flows Strong programming skills in Python Hands‑on experience with static timing analysis (STA) tools, e.g., PrimeTime and Tempus Problem‑solving and analytical mindset Preferred Qualifications Critical thinking with good software architecture understanding to develop platforms at scale Familiarity with GenAI models (e.g., LLMs such as GPT, Llama, etc.) and their application in real‑world solutions, such as chatbots, etc. Experience designing and developing agentic AI systems Experience with version control tools like Perforce or Git Experience with place & route tools and a good understanding of the ASIC RTL‑GDSII design flow Where you will be working - this role requires the candidate to be onsite in San Diego or Santa Clara, CA. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. Please e‑mail disability‑accommodations@qualcomm.com or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Pay range and Other Compensation & Benefits: $115,600.00 - $173,400.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Base is building the foundation of American power. The grid is the largest, most complex machine in the world. Yet it's aging, struggling to keep up with today's demand, and is unprepared for our electrified future. Base is modernizing the grid as the first engineering‑led, technology‑driven power company. We're deploying a nationwide network of distributed batteries that strengthens critical infrastructure and saves Americans money. Our team of engineers, operators, creatives, technicians, and electricians design and deploy systems at speed. If you want to tackle the problem that will define this century and shape the future of American energy, now is the time. Join us. About the Role We are looking for a Mechanical Design Engineer to lead mechanical design for Base's high power residential inverter. You'll own key components, review others, and solve cross‑functional design challenges as they come up. This role is for someone with strong thermal fundamentals and experience designing mechanical components for power converters, including heat transfer solutions and packaging for magnetics and capacitors. What You'll Do Own the delivery of the best high power residential grid‑tied inverter. Own mechanical design of some components, check the mechanical design of others. Drive solutions to design problems, be the glue that fills the cracks between designers. What You'll Bring 5+ years expertise owning mechanical design for grid‑tied or similar power converters. Extremely strong thermal fundamentals, including modeling (1D, transient / steady state, FEA/CFD). Experience designing power electronics mechanical components such as magnetics, capacitors banks, etc. Experience designing heat transfer strategies of various types. Our Values We're building a winning culture and we're looking for people who are up for the challenge. Here's what we expect from day one: In‑Person Only: We work full‑time in the office. No hybrid. No remote. Challenge the Status Quo: Question assumptions. Fix broken systems. Principles > rules. Move Fast: Focus on what matters, act quickly, and learn by doing. Give & Get Feedback: Be direct, be humble. Challenge ideas-including your own. Own the Outcome: Take full responsibility. Deliver results. No excuses. Act Like an Owner: Be resourceful, mindful of impact, and committed to the business. Be Decisive: Drive clarity. Make bold calls with imperfect info. Bring the Intensity: This is not a 9‑to‑5. We're building something hard which requires real commitment. #J-18808-Ljbffr

A leading energy technology company in San Francisco is seeking a Mechanical Design Engineer to lead the design of high-power residential inverters. The candidate should have over 5 years of experience in mechanical design for similar power converters and strong thermal fundamentals. This role requires in-person work at the office without remote options. Competitive compensation is offered based on experience. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. Must be a U.S. citizen and eligible to receive a U.S. Government security clearance We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands‑on experience in RTL‑to‑GDSII flow, with a strong focus on Floor‑planning, Clock Tree Synthesis, Place‑n‑Route (PnR), DRC and Timing closure. This role involves architecting and implementing robust, low‑skew, power‑efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals. This role requires full‑time onsite work in San Diego, CA (5 days per week). Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Key Responsibilities: Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry‑standard tools (e.g., Innovus, ICC2). Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing, congestion, and DRC issues. Optimize design for power, performance, and area (PPA). Conduct formal equivalence checks between RTL and netlist. Support physical verification including DRC, LVS, and antenna checks. Work closely with backend teams for tapeout preparation and signoff. Excellent scripting skills (TCL, Python, Perl) for reference flow automation. Execute full‑chip and block‑level physical verification including DRC, LVS, ERC, antenna, and density checks using industry‑standard tools (e.g., Calibre, Pegasus, ICV). Customize and optimize reference physical verification flows to align with project needs and foundry requirements. Perform GDS‑to‑GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness. Debug and resolve physical verification violations, working closely with layout, design, and CAD teams. Collaborate with foundries to ensure compliance with latest design rule manuals (DRMs) and tapeout checklists. Support signoff verification, including multi‑corner/multi‑mode analysis and ECO validation. Develop and maintain automation scripts for verification flows, reporting, and regression testing. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability. Ensure timely delivery of clean GDSII for tapeout, with full verification signoff. Perform full‑chip and block‑level static timing analysis (STA) using industry‑standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners. Collaborate with RTL, synthesis, and physical design teams to ensure timing‑aware design practices. Debug and resolve setup, hold, and transition violations across various PVT corners. Drive timing closure through iterative optimization and ECO implementation. Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability. Analyze clock tree timing, including skew, latency, and jitter impacts. Support signoff timing verification, including cross‑domain timing and false/multicycle path handling. Define and implement low‑power architecture using CLP methodology across RTL and physical design stages. Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications. Customize and optimize low‑power reference flows to meet project‑specific requirements. Collaborate with RTL, synthesis, and physical design teams to integrate power‑aware features such as power gating, retention, isolation, and level shifting. Perform power‑aware static checks, simulation, and formal verification to validate power intent. Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing. Support signoff verification including power‑aware LVS/DRC, STA, and EM/IR analysis. Ensure compliance with foundry low‑power guidelines and contribute to successful tapeout. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 4+ years of experience in physical design, with a focus on clock tree design and implementation. Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design. Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime). Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies. Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis. Familiarity with low‑power design techniques, including clock gating and multi‑voltage domains. Preferred Skills: Experience with custom clock tree architectures such as H‑tree, mesh, or spine‑based topologies. Knowledge of EM/IR analysis, thermal‑aware clocking, and reliability modeling. Exposure to high‑speed interface clocking (e.g., SerDes, DDR, PCIe). Understanding of package‑level clock planning and signal integrity. Principal Duties & Responsibilities: Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system‑level requirements. Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of complex process flow from high‑level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages. Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects. Level of Responsibility: • Works independently with minimal supervision. • Provides supervision/guidance to other team members. • Decision‑making is significant in nature and affects work beyond immediate work group. • Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. • Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). • Tasks do not have defined steps; planning, problem‑solving, and prioritization must occur to complete the tasks effectively. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑************************** or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company Qualcomm Technologies, Inc. Job Area Engineering Group, Engineering Group > Video Systems, HW Architecture The Multimedia Video Hardware Design team at Qualcomm develops advanced IP cores supporting leading video codec standards. Key Responsibilities Implementing video codec standards (H.264, H.265, H.266, VP9, AV1) Collaborating across hardware, systems, and firmware teams to define specifications and develop IP cores Designing micro-architecture and RTL to meet performance, area, and power requirements Reviewing linting, synthesis, CLP, CDC, and DV coverage reports Maintaining comprehensive design documentation Supporting post-silicon debug Communicating effectively and managing multiple tasks Principal Duties RTL implementation using Verilog/SystemVerilog Design optimization for power, performance, area, and timing Partnering with verification teams for functional and gate-level verification Qualifications Experience in multimedia hardware development (imaging, video, display, audio) Knowledge of SoC bus, interconnect, and memory technologies MS degree with 3+ years in multimedia architecture, video codec standards, VLSI design, and verification Proficiency in Verilog/SystemVerilog, C/C++, SystemC Minimum Qualifications Bachelor's degree in Computer or Electrical Engineering, Computer Science, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. Master's degree in Computer or Electrical Engineering, Computer Science, or related field and 1+ year of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. PhD in Computer or Electrical Engineering, Computer Science, or related field. EEO Employer Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Pay range and Other Compensation & Benefits Salary: $122,500.00 - $183,700.00. Qualcomm also offers a competitive annual discretionary bonus program and opportunity for annual RSU grants. For additional benefits details, please refer to Qualcomm's US benefits information. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. ** Must be a U.S. citizen and eligible to receive a U.S. Government security clearance ** We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands‑on experience in RTL‑to‑GDSII flow, with a strong focus on floor‑planning, clock tree synthesis, place‑and‑route, DRC and timing closure. This role involves architecting and implementing robust, low‑skew, power‑efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals. This role requires full‑time onsite work in San Diego, CA (5 days per week). Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field. Key Responsibilities: Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry‑standard tools (e.g., Innovus, ICC2). Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing, congestion, and DRC issues. Optimize design for power, performance, and area (PPA). Conduct formal equivalence checks between RTL and netlist. Support physical verification including DRC, LVS, and antenna checks. Work closely with backend teams for tapeout preparation and signoff. Excellent scripting skills (TCL, Python, Perl) for reference flow automation. Execute full‑chip and block‑level physical verification including DRC, LVS, ERC, antenna, and density checks using industry‑standard tools (e.g., Calibre, Pegasus, ICV). Customize and optimize reference physical verification flows to align with project needs and foundry requirements. Perform GDS‑to‑GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness. Debug and resolve physical verification violations, working closely with layout, design, and CAD teams. Collaborate with foundries to ensure compliance with the latest design rule manuals (DRMs) and tapeout checklists. Support signoff verification, including multi‑corner/multi‑mode analysis and ECO validation. Develop and maintain automation scripts for verification flows, reporting, and regression testing. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability. Ensure timely delivery of clean GDSII for tapeout, with full verification signoff. Perform full‑chip and block‑level static timing analysis (STA) using industry‑standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners. Collaborate with RTL, synthesis, and physical design teams to ensure timing‑aware design practices. Debug and resolve setup, hold, and transition violations across various PVT corners. Drive timing closure through iterative optimization and ECO implementation. Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability. Analyze clock tree timing, including skew, latency, and jitter impacts. Support signoff timing verification, including cross‑domain timing and false/multicycle path handling. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing insights on timing risks and mitigation strategies. Define and implement low‑power architecture using CLP methodology across RTL and physical design stages. Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications. Customize and optimize low‑power reference flows to meet project‑specific requirements. Collaborate with RTL, synthesis, and physical design teams to integrate power‑aware features such as power gating, retention, isolation, and level shifting. Perform power‑aware static checks, simulation, and formal verification to validate power intent. Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing. Support signoff verification including power‑aware LVS/DRC, STA, and EM/IR analysis. Interface with EDA vendors to resolve tool issues and improve low‑power flow robustness. Participate in design reviews, providing insights on power architecture, risks, and mitigation strategies. Ensure compliance with foundry low‑power guidelines and contribute to successful tapeout. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 3+ years of experience in physical design, with a focus on clock tree design and implementation. Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design. Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime). Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies. Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis. Familiarity with low‑power design techniques, including clock gating and multi‑voltage domains. Preferred Skills: Experience with custom clock tree architectures such as H‑tree, mesh, or spine‑based topologies. Knowledge of EM/IR analysis, thermal‑aware clocking, and reliability modeling. Exposure to high‑speed interface clocking (e.g., SerDes, DDR, PCIe). Understanding of package‑level clock planning and signal integrity. Principal Duties & Responsibilities: Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates architectures, circuit specifications, logic designs, and/or system simulations based on system‑level requirements. Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of process flow from high‑level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package. Writes detailed technical documentation for EDA/IP/ASIC projects. Level of Responsibility: Works independently with minimal supervision. Decision‑making may affect work beyond immediate work group. Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). Tasks require multiple steps which can be performed in various orders; some planning, problem‑solving, and prioritization must occur to complete the tasks effectively. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits $115,600.00 - $173,400.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

We are seeking an experienced Dev/Research Engineer to support product development, compliance, and sustainability initiatives. The ideal candidate will lead research, engineering design, regulatory evaluation, and cross‑functional technical collaboration. This role offers high visibility and the opportunity to influence product strategies across multiple teams and business functions. Key Responsibilities Research, design, develop, and test mechanical systems, tools, machines, and product components. Evaluate customer requirements, specifications, and technical documentation for feasibility, cost, and compliance impact. Investigate mechanical or system issues, identify root causes, and recommend corrective actions. Support drafting and engineering documentation teams with design inputs, blueprints, and CAD oversight. Ensure proper installation, operation, and maintenance of mechanical systems in alignment with engineering standards. Review and interpret regulatory requirements-especially related to packaging waste and Extended Producer Responsibility (EPR). Develop and execute compliance strategies, documentation, and reporting. Work closely with Legal, Operations, Procurement, Logistics, and other cross‑functional teams. Collect, analyze, and interpret technical data to prepare accurate compliance and engineering reports. Represent the organization in meetings, technical forums, and industry associations. Qualifications Bachelor's degree in Engineering (Mechanical, Materials, Physics, Chemical, or related field). 10+ years of progressive experience in engineering, development, or regulatory compliance. Strong expertise in engineering drawings, blueprint interpretation, and CAD tools. Experience in regulatory or product compliance is preferred. Strong analytical skills with proficiency in Excel and technical reporting tools. Effective communicator with proven collaboration and stakeholder‑management experience. Demonstrated leadership, initiative, and ability to influence cross‑functional teams.

Education: BS/BA or AS/AA degree in a relevant engineering field. Experience: 8-10 years of hands-on experience in PCB eCAD design. Strong experience with Siemens Xpedition Layout and DxDesigner VX (MANDATORY). Proficient with PCB eCAD library management using EDM flow. Solid experience with Constraints Editor System, Fablink (panelization), Variant Manager, and Drawing Editor. Deep understanding of schematic to Gerber workflows. Experience designing digital, analog, and mixed-signal PCBs. Knowledge of high-speed interface design constraints and practices (e.g., SATA, DDR4/DDR5, USB, Ethernet, PCIe, PMIC). Familiarity with RF board design is a plus. Strong communication skills in English and ability to work collaboratively in teams.

Job Title: Industrial Engineer / Manufacturing Engineer Employment Type: Full-Time We are seeking an experienced Industrial / Manufacturing Engineer with strong expertise in Powertrain Fixture design or BIW & Welding systems. The ideal candidate will be responsible for designing, developing, and supporting manufacturing fixtures and equipment from concept through installation, while collaborating with global stakeholders. Key Responsibilities Design and develop Powertrain Jigs/Fixtures based on specification documents Create 2D detailing drawings in accordance with customer standards Prepare Bill of Materials (BOM)/Part lists Develop Pneumatic and Hydraulic schematics for equipment functionality Define kinematics for tooling and equipment Lead designs from concept through manufacturing and installation Perform basic engineering calculations for sizing machine components Analyze engineering problems and implement improvements to existing designs and equipment Apply knowledge of metal cutting and removal tools Conduct basic FEA simulations using SolidWorks Support project management activities, including scheduling and coordination Coordinate with offshore teams and ensure effective communication Interact with clients and stakeholders across North America and Canada to gather requirements Willingness to travel as required Required Skills & Qualifications 5-7 years of relevant experience in manufacturing/industrial engineering Strong understanding of Powertrain Fixture Design or BIW & Welding Hands-on experience with Powertrain Jig design Proficiency in SolidWorks 2020 Strong working knowledge of AutoCAD (Mandatory) Proficiency in MS Office (Mandatory) Good communication and stakeholder management skills Preferred Skills Exposure to automotive manufacturing environments Experience working in global/offshore delivery models

CoStar Group (NASDAQ: CSGP) is a leading global provider of commercial and residential real estate information, analytics, and online marketplaces. Included in the S&P 500 Index and the NASDAQ 100, CoStar Group is on a mission to digitize the world's real estate, empowering all people to discover properties, insights and connections that improve their businesses and lives. We have been living and breathing the world of real estate information and online marketplaces for over 35 years, giving us the perspective to create truly unique and valuable offerings to our customers. We've continually refined, transformed, and perfected our approach to our business, creating a language that has become standard in our industry, for our customers, and even our competitors. We continue that effort today and are always working to improve and drive innovation. This is how we deliver for our customers, our employees, and investors. By equipping the brightest minds with the best resources available, we provide an invaluable edge in real estate. Areas of Work 3D Reconstruction Semantic Understanding Generative AI Neural Rendering Responsibilities Collaborate with our team of researchers and engineers to develop and implement state‑of‑the‑art computer vision and machine learning algorithms. Participate in the design, training, and evaluation of deep learning models for various applications, including 3D reconstruction, object detection, and semantic segmentation. Contribute to the development and optimization of algorithms for processing and analyzing 3D spatial data. Conduct experiments, analyze results, and present findings to stakeholders in a clear and concise manner. Basic Qualifications Bachelor's degree or higher from an accredited, not‑for‑profit, in‑person institution in computer science or computer/software engineering, or comparable major graduating between December 2025 through June 2026 Minimum 3.0 cumulative GPA Must have previous, relevant internship experience Strong programming skills in Python and experience with deep learning frameworks such as PyTorch. Preferred Qualifications and Skills Ability to write understandable, maintainable, and well‑documented code. Familiarity with Agile Development processes and Software Development Lifecycle. Knowledge of web service design and development. What's in it for you Joining CoStar Group means becoming part of a culture of collaboration and innovation that attracts top talent across diverse fields. In addition to competitive compensation and performance‑based incentives, you'll receive support for both your professional and academic growth through internal training, and tuition reimbursement. Benefits Medical, Vision, Dental, and Prescription Drug coverage. Mental Health Wellness Program. Life, Legal, and Supplementary Insurance. Commuter and Parking Benefits. 401(K) Retirement Plan with matching contributions. Employee Stock Purchase Plan. Paid Time Off. Tuition Reimbursement. Access to an on‑site fitness center (or reimbursed fitness center membership costs), yoga studio, Peloton, personal training, group exercise classes, and Segways and bikes for the day. Complimentary gourmet coffee, tea, hot chocolate, prepared foods, fresh fruit, and healthy snacks. Be part of a team of professionals dedicated to learning, growth, and success in a rewarding environment. We encourage all qualified candidates eligible to work full‑time in the United States to apply. Please note that CoStar does not provide visa sponsorship for this position. CoStar Group is an Equal Employment Opportunity Employer, maintaining a drug‑free workplace and conducting pre‑employment substance abuse testing. CoStar Group accepts job applications from candidates in the United States solely through the following channels: The CoStar Group website. Email correspondence using only the CoStar domain of costar.com. Screening and interaction via telephone, Microsoft Teams, or Zoom platforms. Please be cautious: CoStar does not use Wire, Google Hangouts, or any other platform for recruitment‑related activities. Disregard any solicitation or request for information regarding job applications with CoStar via any means other than those listed above. CoStar will never ask candidates to make any personal financial investment related to employment with the company. This position offers an annual base salary range of $82,300 - $179,000 based on relevant skills and experience and includes a generous benefits plan. CoStar Group is an Equal Employment Opportunity Employer; we maintain a drug‑free workplace and perform pre‑employment substance abuse testing. #J-18808-Ljbffr

Design experience in analog/digital electronic circuits for automotive application Good knowledge in automotive hardware development Experience in the Automotive domain with hands on knowledge of ISO 26262 Functional Safety Standard Should have hands on experience on design analysis such as WCCA, DFMEA, FMEDA, FTA using tools Experiences in various software tools such as Mathcad, Ansys Medini etc.

We are seeking an experienced Electrical Engineer to support high-power system design and testing initiatives for our client in San Jose, CA. The ideal candidate will have strong hands-on experience with high-voltage circuits, power components, and lab testing, along with exposure to manufacturing support and documentation. Key Responsibilities: Design, develop, and implement technical solutions for high-voltage and high-power systems Support high-power testing and design testing fixtures Select and evaluate power components for electrical systems Perform hands-on testing using lab instruments such as oscilloscopes, RLC analyzers, and related equipment Create and maintain cable harness drawings using AutoCAD or similar tools Prepare and manage Bill of Materials (BOM) documentation Support manufacturing activities by troubleshooting issues and providing engineering solutions Collaborate with cross-functional engineering and production teams Required Skills & Qualifications: Experience working with high-voltage circuits and power component selection Hands-on experience with lab instruments (oscilloscopes, RLC analyzers, etc.) Experience designing testing fixtures for high-power systems Proficiency in AutoCAD for cable harness design Experience with BOM creation and manufacturing support Strong problem-solving and communication skills

Paint Project Engineer Princeton, IN Must Haves: This team has started a newmodel project, looking for an engineer who can investigation, make process plans, create specifications, work with vendors, improvement and refurbishment projects, as well as implement equipment modifications for new model launches. Project management experience, manage project timelines, budgets, scopes, and documentation equipment specifications and issue tracking. Adherence to safety standards and regulations. Experience: 2-3 years in a similar engineering / project management role, ideally within the manufacturing sector. Strong understanding of manufacturing systems and equipment. Strong problem solving mindset, critical thinking. Some knowledge of CATIA and 3D programming would be a plus. OT: 12% (Ability to work weekends, holidays.) Bachelor's is required, any field is fine.

A digital content company based in San Francisco seeks a Senior Engineering Manager for its Growth Platform. This role requires over 7 years of engineering experience, including management of successful teams. The manager will innovate systems for user acquisition and retention while ensuring high technical standards. Above-average pay and flexible work arrangements are part of the package, making it an attractive opportunity for tech leaders who aim to make a measurable impact across the organization. #J-18808-Ljbffr

Expertise in Pinpoint MES for 3+ years and MES 10+ years Has knowledge in Automotive domain Assist in providing assembly planning support for Building Construction product/ Earth moving equipment. Experience with setting up Assembly Value streams in Pinpoint with Section/ station/ Zone and Assembly operations. Set up Pinpoint with Assembly line Torque tools, fixtures, and other in-process validation (IPV) checks. Integrate Torque tool, sockets and other Quality inspection devices with Pinpoint to improve preventive control and, interlock mechanisms in the assembly process. Integrate Andon process with pinpoint application and exposure with production tracking dashboard to develop station/ Zone wise metrics in terms of Cycle time, Material downtime, tool/ fixture downtime etc. Experience with Manufacturing Execution system for Assembly (MESA). Update standard work and visual work instructions as needed, following established standards and guidelines Carry out continuous improvement projects to assist with better through put and quality for product lines being manufactured including Value Stream Mapping (VSM) Responsible for supporting the manufacturing operation by providing tooling, processes, equipment, etc. to provide for the needs of the shop operations. Establishes standards and works with shop personnel to resolve problems related to process, tooling, equipment, etc. The expected salary range for this position is between $74,500 to $80,500 annually. The actual salary may vary based upon several factors including, but not limited to, relevant skills/experience, time in role, base salary of internal peers, prior performance, business line, and geographic/office location.

We are seeking a proactive and detail‑oriented Manufacturing Engineer to support production operations and lead continuous improvement initiatives. You will work closely with cross‑functional teams to ensure that all manufacturing processes meet safety, quality, delivery, and cost objectives. Key Responsibilities Analyze and optimize manufacturing processes to improve efficiency and reduce downtime. Conduct time studies, workflow analysis, and standard work audits. Develop and maintain process documentation including Standard Work, PFMEA, Control Plans, visual aids, and process flow diagrams. Interpret and create engineering drawings, schematics, and technical reports. Support production teams by troubleshooting issues, identifying root causes, and implementing corrective actions. Plan and coordinate work assignments based on capacity, performance, and production schedules. Prepare charts, graphs, and reports to communicate process performance. Collaborate daily with operations, engineering, and quality teams. Required Qualifications Bachelor's degree in Industrial, Manufacturing, Mechanical Engineering, or a related field (or equivalent experience). 2+ years of experience in a manufacturing or production environment. Strong ability to read and interpret blueprints, technical drawings, and schematics. Proficiency with CAD software and engineering tools. Strong analytical, problem‑solving, and communication skills. Comfortable working both on the production floor and in an office setting. Preferred Skills Experience with PLCs, robotics, automation systems, or manufacturing software. Background in lean manufacturing, continuous improvement, or Six Sigma. Ability to lead and participate in cross‑functional projects. What We're Looking For Strong communicator and team player Detail‑oriented with excellent organizational skills Analytical mindset and passion for problem-solving Comfortable in fast‑paced, hands‑on environments

Title: Manufacturing Engineer Employment Type: Full-Time We are seeking a Manufacturing Engineer to design, integrate, and optimize automation systems across plant operations. This role will lead automation initiatives, drive process improvements, and support data-driven manufacturing excellence. Key Responsibilities Design and integrate automation systems (Pick & Place, conveyors, bowl feeders, robotics) Lead equipment upgrades, modifications, and validation activities Support automation business cases and project justification Ensure maintenance, repair, and compliance with OEM standards Improve safety, ergonomics, quality, and productivity Apply A3, KT, DMAIC and structured problem-solving methods Track progress, analyze trends, and present performance reports Collaborate with cross-functional plant teams Required Skills Automation design experience (robotics preferred) Hands-on robotics programming, troubleshooting, diagnostics AutoCAD, SolidWorks, Excel, and Minitab Strong analytical mindset and manufacturing problem-solving experience

We are seeking an experienced Industrial Engineer to support manufacturing and assembly operations with a strong focus on Lean principles, process optimization, and continuous improvement. The ideal candidate will have hands-on experience in time studies, line balancing, value stream mapping, and root cause analysis within an assembly or manufacturing environment. Key Responsibilities: Study assembly lines and manufacturing processes to identify improvement opportunities using Lean principles. Perform time studies and line balancing, including elemental breakdowns, video time studies, VA/NVA/RNVA analysis, and Muri analysis. Develop current-state and future-state line balancing models. Create Value Stream Maps (VSM) to identify bottlenecks, waste, inefficiencies, and conduct capacity analysis. Establish current baselines and define future-state improvements. Identify productivity and process improvement opportunities and provide Level 1, 2, and 3 improvement recommendations with a detailed roadmap. Develop and update standard work instructions and video-based work instructions. Perform root cause analysis for quality issues, defects, downtime, and support corrective actions through Kaizen and continuous improvement initiatives. Assist in fixture design and process support as required.

The ideal candidate possesses both a high level of technical expertise and an innate passion to build. You will play a critical role in creating and refining processes in order to improve manufacturing safety, quality, and productivity. Responsibilities Create and maintain work instructions and manufacturing specifications Identify and recommend methods for improving worker efficiency and reducing waste of materials and utilities Collaborate cross-functionally to facilitate production process and evaluate potential changes Qualifications Bachelor's degree in either Industrial or Mechanical Engineering At least 1 - 2 years' of engineering experience Experience with Lean, Six Sigma, Kaizen, Kanban and 5S