Mechanical Engineer jobs at Chenega - 13144 jobs

At Kargo, our mission is to build a connective tissue between the physical world of freight and the digital ecosystem used to manage it. We believe that advancements in smart infrastructure are critical to enabling a safer and more efficient future for logistics. Our loading dock sensor platform verifies all incoming and outgoing freight, aggregating data that enables shippers and carriers to efficiently manage dock operations, switch out suppliers and understand material flow in real time. We care deeply about delivering the best solutions for our customers. As a member of the Kargo team, you will have the opportunity to develop and deploy tomorrow's hardware & software solutions and help revolutionize logistics. Responsibilities Lead sustaining engineering for existing products. Lead development efforts on next generation products. Manage rapid prototyping efforts in machine shop. Develop CAD models and simulations in the designs of your responsible parts. Design fixtures and test set ups to validate designs. Document designs and test results. Draft drawings for all responsible parts and integrate into PLM. Experience 3+ years experience in Mechanical Design or related role. Strong fundamentals in mechanical engineering first principles. Experienced in CAD software (SolidWorks preferred). Experienced in using SolidWork PDM and PLM softwares (Arena preferred). Experience in Design for Manufacturing principles. Experienced in electronics packaging design. (Preferred) Experience in optics design cameras and/or lighting. (Preferred) Structural or thermal design and simulation experience. Bachelor's Degree or the equivalent experience in a technical discipline preferred. Kargo is an equal opportunity/affirmative action employer committed to an inclusive and diverse workplace. All qualified applicants will receive consideration for employment without regards to race, color, religion, sex, sexual orientation, gender identity, national origin, disability status, protected veteran status or any other basis prohibited by law. We also consider qualified applicants with criminal histories consistent with applicable federal, state and local law. #J-18808-Ljbffr

A leading technology company is seeking a Mechanical Design Engineer to lead sustaining engineering efforts for existing products and develop next-generation solutions. The ideal candidate will have 3+ years of experience in mechanical design, strong fundamentals in engineering, and proficiency in CAD tools like SolidWorks. A Bachelor's degree in a relevant discipline is preferred. Join us to revolutionize logistics with cutting-edge hardware and software solutions. #J-18808-Ljbffr

A leading technology company seeks a Machine Learning Engineer to innovate product designs through predictive simulations. This role demands strong expertise in machine learning and finite element analysis with an M.S. or Ph.D. in a related field. Responsibilities include developing ML methods and collaborating with design teams. Competitive pay range is $139,500 to $258,100, alongside comprehensive benefits and opportunities for stock ownership. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking a Staff Power Module Design Engineer. You'll develop innovative power module products and collaborate with industry experts. The role requires a strong educational background in Power Electronics and significant experience in switching power converter design. This position offers competitive pay within a vibrant engineering team, fostering professional growth and mentorship opportunities. #J-18808-Ljbffr

Responsibilities Work with internal customers to define the automated system specifications. Select the main components, such as motion stages, vision components, sensors, pneumatical components, commercial tooling, frame, and etc. Layout the system and review the initial design with the customer. Detailed design all subsystems and related components. Generate necessary part drawings for part manufacturing. Work with technicians and manage the system assembly. Modify and improve the system design as needed. Design and implement automated assembly, test, and inspection systems for company internal customers. Utilize SolidWorks software to layout and design the automated system, subsystem, components, etc. Generate drawings for mechanical parts machining and surface treatment. Create BOM for the system support and additional system building. Document all designs in Agile database. Collaborate with teams to develop and transfer the new process to manufacturing site. Education & Experience Minimum 9 yr. of mechanical engineering experience in automated process and test systems development is a must. BS/MS in Mechanical Engineering or equivalent degree. Familiar with small tooling fixture design is preferred. Knowledge of laser technology is preferred. Skills Experience with semi-automated and automated processing systems. Familiarity with Microsoft Office, such as Power Point, Excel, and Word. Meticulous and thorough; diligent with design documentation. Ability to speak, read, write, and comprehend English is required. Integrity and self-motivated Ability to work in fast paced team and independent setting. Knowledge of machining, vision, and electrical engineering is useful. Working Conditions Primarily office-based with regular time spent in lab or manufacturing environments for system assembly, testing, and troubleshooting. May require occasional lifting of mechanical components or tools (up to 25 lbs) during equipment assembly. Frequent use of computer-aided design (CAD) software and other engineering tools in a seated position for extended periods. Occasional travel to manufacturing sites or supplier locations may be required to support equipment transfer or installation. Exposure to standard shop-floor conditions, including noise, moving mechanical parts, and the need for personal protective equipment (PPE). Physical Requirements Onsite or hybrid work. Ability to lift and move mechanical components or equipment weighing up to 25 pounds during system assembly or testing. Must be able to stand, walk, bend, and reach in a lab or manufacturing environment for extended periods when supporting equipment builds or troubleshooting. Safety Requirements All employees are required to follow the site EHS procedures and Coherent Corp. Corporate EHS standards. Quality and Environmental Responsibilities Depending on location, this position may be responsible for the execution and maintenance of the ISO 9000, 9001, 14001 and/or other applicable standards that may apply to the relevant roles and responsibilities within the Quality Management System and Environmental Management System. Culture Commitment Integrity - Create an Environment of Trust Collaboration - Innovate Through the Sharing of Ideas Accountability - Own the Process and the Outcome Respect - Recognize the Value in Everyone Enthusiasm - Find a Sense of Purpose in Work Coherent Corp. is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. Note to recruiters and employment agencies: We will not pay for unsolicited resumes from recruiters and employment agencies unless we have a signed agreement and have required assistance, in writing, for a specific opening. Job Info Job Identification 2009041 Posting Date 10/21/2025, 06:50 PM Degree Level Bachelor's Degree Job Schedule Full time Locations 5100 Patrick Henry Drive, Santa Clara, CA, 95054, US (On-site) #J-18808-Ljbffr

A leading robotics company in Waltham is seeking a Principal Mechanical Engineer for its Spot robot team. You will lead cross-functional teams to develop and implement complex robotic subsystems. The ideal candidate must hold a BSME with at least 10 years of relevant experience, including advanced skills in CATIA and strong technical writing. This position offers a competitive salary range and generous benefits including medical, dental, vision, 401(k), and paid time off. #J-18808-Ljbffr

Copy link Google Sunnyvale, CA, USAMidExperience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. Academic, educational, internship, or project experience with RTL coding, Verilog, or SystemVerilog. Preferred qualifications: Experience with scripting language (e.g., Python or Perl). Experience applying engineering best practices (e.g. code review, testing, refactoring). Experience interacting with software, architecture, and other cross-functional teams. Knowledge of processor design or accelerators. Knowledge of high-performance and low power design techniques. Knowledge of processor design, accelerators, or memory hierarchies. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As an RTL Design Engineer, you will be part of a team developing ASICs to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google. Responsibilities Understand the overall application of the chip, proposing and developing improvements in overall design. Design and document one or more blocks of an ASIC, including functionality and timing. Work closely with software teams on functionality, interfaces, and documentation. Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire. #J-18808-Ljbffr

5+ years of mechanical design experience. Knowledge of a variety of (metal) manufacturing methods, e.g. machining, stamping, molding, welding, brazing, casting, plating, 3D printing, etc. Knowledge and experience in sheet metal fabrication and rack and chassis designs Strong analytical and computational skills in structural, heat transfer, fluid dynamics, and tolerance studies for mechanical and thermal consideration. Able to multitask between several projects and designs and handle a lot of details. Must be self-motivated with the ability to work effectively in a team environment and meet project deadlines. Skills Leadership capabilities to command design decision. Strong interpersonal, teaming, and problem-solving skills. Work effectively with other members of Coherent engineering Strong collaborative and communications skills are required for interactions with customers, with the design, process, and manufacturing teams. Strong analytical problem-solving skills for product design and debug Working Conditions This position is on-site May require occasional off-site meetings or travel Regular use of a computer and other office equipment is necessary Interaction with team members and external contacts is a regular part of the job May require occasional overtime and flexibility in work hours to accommodate the executive's needs Physical Requirements Sitting for extended periods while working on a computer or conducting meetings. Use of hands and fingers for typing, writing, and handling documents. Occasional lifting of objects or materials up to 20 pounds for administrative tasks. Ability to communicate verbally and in writing. Mobility within the office environment to attend meetings or interact with colleagues. Safety Requirements All employees are required to follow the site EHS procedures and Coherent Corp. Corporate EHS standards. Quality and Environmental Responsibilities Depending on location, this position may be responsible for the execution and maintenance of the ISO 9000, 9001, 14001 and/or other applicable standards that may apply to the relevant roles and responsibilities within the Quality Management System and Environmental Management System. CultureCommitment Integrity - Create an Environment of Trust Collaboration - Innovate Through the Sharing of Ideas Accountability - Own the Process and the Outcome Respect - Recognize the Value in Everyone Enthusiasm - Find a Sense of Purpose in Work Coherent Corp. is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. Coherent is a global leader in lasers, engineered materials and networking components. We are a vertically integrated manufacturing company that develops innovative products for diversified applications in the industrial, optical communications, military, life sciences, semiconductor equipment, and consumer markets. Coherent provides a comprehensive career development platform within an environment that challenges employees to perform at their best, while rewarding excellence and hard-work through a competitive compensation program. It's an exciting opportunity to work for a company that offers stability, longevity and growth. Come Join Us! Note to recruiters and employment agencies: We will not pay for unsolicited resumes from recruiters and employment agencies unless we have a signed agreement and have required assistance, in writing, for a specific opening. About the Team II-VI Aerospace & Defense is a high technology company, offering careers in offices and campuses in California, Colorado, Florida, Pennsylvania, and Ohio. We work with emerging technology in areas of atmospheric sensing and imaging, adaptive optics, optical communications, coherent beam combining, and numerical performance analysis of atmospheric optics systems. II-VI A&D has recently been awarded several new government contracts and we are offering opportunities to leverage your technical experience and interpersonal skills for something more than a simple paycheck. If this sounds like the type of environment you are seeking at this point in your career, and if your background meets these qualifications, please apply. We will offer a competitive salary and benefits. Since II-VI A&D is a rapidly expanding organization, it means that significant opportunities exists for career advancement and professional development. Job Info Job Identification 2009614 Posting Date 01/13/2026, 05:14 PM Degree Level Master's Degree Job Schedule Full time Locations 48800 Milmont Drive, Fremont, CA, 94538, US (On-site) #J-18808-Ljbffr

A global semiconductor company in San Jose is seeking a Principal Power Module Design Engineer. This role involves new product development in power electronics, requiring at least a master's or Ph.D. in Power Electronics and 5+ years of experience in related design. Applicants should possess strong skills in switching power converter design and analog circuit design. The position offers competitive compensation, a collaborative environment, and opportunities for professional growth. #J-18808-Ljbffr

A cutting-edge AI lab in San Francisco is seeking experienced end-to-end engineers to join their small, talent-dense team. The role involves building innovative software products, enhancing user experiences, and collaborating closely with product teams. Ideal candidates should have experience with Python, Typescript, and React. Strong achievers who thrive in fast-moving environments are encouraged to apply. #J-18808-Ljbffr

corporate_fare Google place Sunnyvale, CA, USA Apply Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with physical design. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with scripting languages such as Perl, Python, or Tcl. Experience with constraints, synthesis or clock tree synthesis (CTS). Experience in block/subchip level place and route for SoC or with multiple-cycles of SoC in ASIC design. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As a Physical Design Engineer, you will collaborate with RTL, design for testing (DFT), floorplan, and full‑chip signoff teams. Additionally, you will solve technical problems with micro‑architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full‑time position is $113,000-$161,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google. Responsibilities Participate in the physical design of blocks for TPU chips. Contribute to the design and closure of the subchip and individual blocks from RTL-to-GDS. Collaborate with RTL/Design and physical design (PD) teams to achieve the best power/performance/area (PPA) possible. Conduct feasibility studies for new microarchitectures as well as optimizing runs for best quality of result (QoR). Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire. Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr

corporate_fare Google place Sunnyvale, CA, USA Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Apply link Copy link Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with physical design. Experience in physical design areas such as synthesis, place and route, Static Timing Analysis (STA), verification, or power analysis. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience in block/subchip level PnR for complex SoC. Experience with multiple-cycles of SoC in ASIC design. Experience with scripting languages such as Perl, Python, or Tcl. Experience with layout verification and design rules. Experience in IP integration (e.g., memories, IO's and Analog IP) with the knowledge of semiconductor device physics and transistor characteristics. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a System on a Chip (SoC) Physical Design Engineer, you will collaborate with Register-Transfer Level (RTL), Design for Testing (DFT), Floorplan, and full-chip Sign off teams. Additionally, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Participate in the Physical Design of blocks for complex Tensor Processing Unit (TPU) chips. Contribute to the design and closure of the subchip and individual blocks from Register-Transfer Level-to-Graphic Design System . Collaborate with RTL/Design and Product Development teams to achieve the best Power Performance Area (PPA) possible. This includes conducting feasibility studies for new micro-architectures as well as optimizing runs for best Quality of Results (QoR). Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr

Apply Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Qualifications PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. Academic, educational, internship, or project experience with physical design. Preferred qualifications Experience in scripting using Languages like Python, Tcl, Perl. Proficiency in fundamental SoC architecture and hardware description languages such as Verilog, facilitating effective collaboration with logic design teams to resolve timing issues. Knowledge of fundamental VLSI and physical design principles, including expertise in semiconductor device physics and transistor structures (e.g., finfet, Gate all around). Understanding of Static Timing Analysis(STA), Clock Domain Crossings (CDC), clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis. Understanding of standard cells, SRAMs, power, noise, and IR analysis. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As a Physical Design Engineer, you will collaborate with Register‑Transfer Level (RTL), Design for Testing (DFT), floorplan, and full‑chip sign off teams. Additionally, you will solve technical problems with innovative micro‑architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full‑time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Participate in the physical design of blocks for complex Tensor Processing Unit (TPU) chips. Contribute to the design and closure of the subchip and individual blocks from Register‑Transfer Level‑to‑Graphic Design System (RTL2GDSII). Collaborate with RTL/Design and Product Development teams to achieve the best Power Performance Area (PPA) possible. This includes conducting feasibility studies for new micro‑architectures as well as optimizing runs for best Quality of Results (QoR). Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr

A healthcare technology startup in San Francisco is seeking a Product Engineer to join their founding team. The role involves building and maintaining core applications that improve patient safety through AI analytics. Candidates should have 3+ years in software engineering with a strong grasp of modern web technologies and a passion for turning innovative ideas into practical applications. This position offers ownership and autonomy in a mission-driven environment aiming to transform healthcare. #J-18808-Ljbffr

Pharos is an early-stage startup dedicated to improving patient safety in hospitals through advanced AI-powered reporting and analytics. Our mission is to make healthcare safer by automating hospital quality reporting and helping staff identify and prevent the root causes of avoidable harm. Our vision is an AI system reviewing every chart at scale, identifying patterns and giving clinicians the insights they need to prevent the 100k avoidable deaths that occur in U.S. hospitals every year. We raised a $5m seed funding round at the end of 2024. About the Role This is a pivotal role as a founding member of the engineering team at Pharos. As a Product Engineer, you will bridge the critical gap between product vision and technical execution. You will be responsible for building, shipping, and maintaining our core user-facing applications, working in close partnership with the founders and design team. These products include an interface for users to review and correct AI-generated results to medical questions, as well as an analytics and root cause analysis platform where users can visualize clinical quality trends and drill down into the causes of specific patient safety events. The scope of this role is intentionally broad. As one of our first engineers, you will be an integral part of the founding team, working at the intersection of product design, user experience, and full-stack engineering. We are creating a new category of product, requiring 0-to-1 innovation - turning a novel vision into a real, tangible application without existing examples to lean on. You'll be translating complex requirements and detailed designs into beautiful, functional, and reliable applications. You will have autonomy and ownership over the entire product lifecycle, from the first line of code to deploying in production and monitoring its impact. Your work will directly build the tools healthcare workers use every day to make healthcare safer. What You'll Do End-to-End Feature Development: Own the end-to-end development of new user-facing features, from technical design and implementation to testing, deployment, and monitoring. Design-to-Production: Collaborate closely with designers to translate Figma prototypes into pixel‑perfect, responsive, and intuitive web applications. Full‑Stack Implementation: Build and maintain all components of our product, including the front‑end and the back‑end APIs and services that power them. Product Ownership: Act like a product owner. Rapidly prototype new ideas, participate in user feedback sessions, and use your product intuition to advocate for the best user experience. Infrastructure & Deployment: Manage and improve our CI/CD pipelines, cloud infrastructure, and deployment processes to ensure reliability, scalability, and a fast development loop. Uphold Quality: Champion high standards for code quality, testing, and engineering best practices within a fast-moving startup environment. Cross‑Functional Collaboration: Work side‑by‑side with the founders, designers, and AI research team to solve complex problems and build a cohesive, mission‑critical product. What We're Looking For Required: Engineering Experience: 3+ years of professional experience as a software engineer, with a strong track record of building and shipping user‑facing products. Web‑Stack Proficiency: Deep expertise in modern web technologies, including a front‑end framework (e.g., React, Vue), TypeScript, design systems and document databases. Production Experience: Experience deploying and maintaining applications in a cloud environment (e.g., AWS, GCP, Azure). Product & Design Sense: Strong product intuition and a keen eye for design. You care deeply about the 'why' behind what you're building and the user's experience. Communication: Excellent ability to communicate complex technical concepts to diverse audiences, including non‑technical stakeholders. Strongly Preferred: Startup Experience: Previous experience as an early‑stage employee at a startup, demonstrating an ability to thrive in a fast‑paced environment. Healthcare Informatics: Familiarity with healthcare data, electronic health records (EHRs), or interoperability standards (FHIR, HL7) is a major plus. Design Systems: Experience building or using design systems to maintain UI consistency and accelerate development. Our Technology Stack As a product engineer, you'll primarily work with our modern, high-performance stack: Frontend: React, TypeScript, Vite, and TailwindCSS. Backend & Services: TypeScript on Bun (for application backends) and Python (for AI/ML services). Database & Auth: Firebase (Firestore, Auth, Hosting) integrated closely with GCP. Infrastructure: Google Cloud Platform (GCP), especially Cloud Run, Pub/Sub, and Google Healthcare API. Tooling: Nx for monorepo management, Biome (JS) and Ruff (Python) for linting/formatting. Architecture: We run a microservices architecture with event‑driven patterns using Pub/Sub. Personal Attributes: High agency: You're excited by the opportunity to take ambiguous product challenges and drive them from idea to execution without waiting for direction. Motivated by impact: You're energized to work hard as part of a high-performing team - holding a meaningful equity stake in a company with the real potential to save thousands of lives. Ownership mindset: You take pride in acting like an owner, taking full responsibility for the quality and outcomes of your work. Comfortable with ambiguity: You thrive in an early‑stage startup environment where there's no rigid hierarchy, everyone wears many hats, and you have real power to influence the path of the company. What We Offer Foundational Impact: A rare chance to build a category‑defining healthcare AI company from the ground up and directly improve patient outcomes at scale. Product + Technical Growth: Unique opportunity to develop expertise at the intersection of product, design, user‑facing engineering, and cutting‑edge AI. Ownership and Autonomy: Take ownership of the core user‑facing product and have significant autonomy in your technical and product decisions. Significant Outcome Potential: Meaningful equity stake as a founding team member. Mission‑Driven Work: Every day, work on technology that has the potential to prevent avoidable patient harm and save lives. Culture Creation: Actively shape a positive, collaborative, innovative, and mission‑driven culture that values both technical excellence and user impact. Benefits: Good healthcare, dental and vision plans and 401k. Location San Francisco, USA. We expect our core team to be in the office most working days. #J-18808-Ljbffr

A leading technology company in San Jose is seeking an experienced engineer to join their analog/mixed signal IP design team. This role involves designing next generation I/O interfaces, with a strong emphasis on mixed signal design and leading technical projects. The ideal candidate will possess a degree in Electrical Engineering and have hands-on experience with high speed designs and communication tools. This position offers competitive benefits and is not eligible for visa sponsorship. #J-18808-Ljbffr

A leading electronic design automation company in California seeks an experienced SoC/ASIC Digital Design Engineer with a strong focus on Design for Test (DFT) methodologies. The ideal candidate will have substantial expertise in scan chain insertion, compression scan technologies, and automatic test pattern generation (ATPG), along with strong problem-solving skills and the ability to work collaboratively in a cross-functional team environment. This is a fantastic opportunity to contribute to essential technology projects. #J-18808-Ljbffr

We are an applied AI lab building end-to-end software agents. We're the makers of Devin, the first AI software engineer. Now is the most interesting time to join Cognition - we're seeing record growth and demand, the code generation industry is developing at lighting speed and we're doing this with one of the smallest teams thanks to Devin. We are small and talent-dense. Among our founding team, we have world-class competitive programmers, former founders, and leaders from companies at the cutting edge of AI including Scale AI, Cursor, Waymo, Tesla, Lunchclub, Modal, Google DeepMind, and Nuro. If you're excited to solve some of the world's most challenging problems and build AI that can reason on real-world tasks, join us. About the Role We're looking for experienced end-to-end engineers who thrive at fast-moving startups, and are excited to push the boundaries of how developers will interact and work with coding agents. You'll work closely with other engineers on the team, the product and go-to-market teams at Cognition, and our design partners. In this role, you will: Ship product and talk to users! Punch through technical walls Build performant and beautiful experiences that developers love Set the standard for UX of agent products Requirements for the role: A record of exceptional achievements and impact Willingness to work hard, move fast and grow quickly in a rapidly changing environment An exceptional ability to learn Experience with Python, Typescript, & React in complex products #J-18808-Ljbffr

A leading technology company is seeking a Machine Learning Platform Engineer in Mountain View, CA. The role involves designing and developing advanced machine learning platforms for advertising, mentoring junior engineers, and collaborating with cross-functional teams. Candidates should have extensive experience in machine learning frameworks and strong programming skills. A comprehensive benefits package is offered, including health insurance and a competitive salary range from $240,000 to $280,000. #J-18808-Ljbffr