Controls engineer jobs in Vista, CA - 656 jobs

A leading technology company is seeking a Senior RF Design Engineer in San Diego to develop RF subsystems for advanced communications. The role requires a Bachelor's degree in Electrical Engineering and at least 5 years of RF hardware experience. Responsibilities include PCB layout, RF performance tuning, and troubleshooting production issues. The compensation ranges from $140,000 to $190,000 annually. Benefits include medical, dental, vision, and paid time off. #J-18808-Ljbffr

A leading aerospace and defense company is looking for a Senior Principal Electronics Engineer - Hardware and Software Integration Lead in San Diego. This role involves leading the development of next-generation ground system solutions, managing software supplier interactions, and coordinating various engineering efforts. Candidates should have a strong background in STEM, relevant work experience, and active security clearance. The position requires on-site work but could offer hybrid options in the future. #J-18808-Ljbffr

We are seeking an experienced PCB Design Engineer to join our advanced electronics design team in Irvine, CA. The ideal candidate will have strong hands-on experience with Cadence Allegro PCB design, high-speed digital interfaces, and PCB manufacturing best practices. This role involves working on high-reliability airborne and defense electronic systems. Key Responsibilities Design and develop high-speed, high-density PCB layouts using Cadence Allegro Create multilayer PCB stack-ups and manage layout constraints Perform PCB layout for low-pitch BGAs, SMDs, and high-density connectors Apply DFM and DFT principles to ensure manufacturability and testability Handle impedance control, length matching, shielding, and power integrity design Work on Ethernet (2.5G/5G/10G), PCIe, DDR, and high-speed memory interfaces Prepare and maintain Product Data Packages (PDP) including BOM, item lists, documentation, COTS, materials & process details Collaborate with electronics, mechanical, and systems engineering teams Consider thermal, mechanical, EMI/EMC, and shock constraints in airborne environments Support SI/PI simulation activities (preferred) Required Skills & Qualifications 5+ years of experience in electronic/PCB design Strong hands-on experience with Cadence Allegro PCB design tool Solid knowledge of PCB manufacturing processes, materials, and component packaging Experience with high-speed digital interfaces (Ethernet, PCIe, DDR, etc.) Strong understanding of DFM, DFT, EMI/EMC, SI/PI, and power integrity Experience working in airborne, aerospace, or high-reliability electronic environments Strong communication and collaboration skills Good to Have Experience in Defense / Aerospace / Avionics systems Ability to work independently as an individual contributor

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. Must be a U.S. citizen and eligible to receive a U.S. Government security clearance We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands‑on experience in RTL‑to‑GDSII flow, with a strong focus on Floor‑planning, Clock Tree Synthesis, Place‑n‑Route (PnR), DRC and Timing closure. This role involves architecting and implementing robust, low‑skew, power‑efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals. This role requires full‑time onsite work in San Diego, CA (5 days per week). Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Key Responsibilities: Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry‑standard tools (e.g., Innovus, ICC2). Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing, congestion, and DRC issues. Optimize design for power, performance, and area (PPA). Conduct formal equivalence checks between RTL and netlist. Support physical verification including DRC, LVS, and antenna checks. Work closely with backend teams for tapeout preparation and signoff. Excellent scripting skills (TCL, Python, Perl) for reference flow automation. Execute full‑chip and block‑level physical verification including DRC, LVS, ERC, antenna, and density checks using industry‑standard tools (e.g., Calibre, Pegasus, ICV). Customize and optimize reference physical verification flows to align with project needs and foundry requirements. Perform GDS‑to‑GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness. Debug and resolve physical verification violations, working closely with layout, design, and CAD teams. Collaborate with foundries to ensure compliance with latest design rule manuals (DRMs) and tapeout checklists. Support signoff verification, including multi‑corner/multi‑mode analysis and ECO validation. Develop and maintain automation scripts for verification flows, reporting, and regression testing. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability. Ensure timely delivery of clean GDSII for tapeout, with full verification signoff. Perform full‑chip and block‑level static timing analysis (STA) using industry‑standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners. Collaborate with RTL, synthesis, and physical design teams to ensure timing‑aware design practices. Debug and resolve setup, hold, and transition violations across various PVT corners. Drive timing closure through iterative optimization and ECO implementation. Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability. Analyze clock tree timing, including skew, latency, and jitter impacts. Support signoff timing verification, including cross‑domain timing and false/multicycle path handling. Define and implement low‑power architecture using CLP methodology across RTL and physical design stages. Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications. Customize and optimize low‑power reference flows to meet project‑specific requirements. Collaborate with RTL, synthesis, and physical design teams to integrate power‑aware features such as power gating, retention, isolation, and level shifting. Perform power‑aware static checks, simulation, and formal verification to validate power intent. Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing. Support signoff verification including power‑aware LVS/DRC, STA, and EM/IR analysis. Ensure compliance with foundry low‑power guidelines and contribute to successful tapeout. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 4+ years of experience in physical design, with a focus on clock tree design and implementation. Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design. Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime). Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies. Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis. Familiarity with low‑power design techniques, including clock gating and multi‑voltage domains. Preferred Skills: Experience with custom clock tree architectures such as H‑tree, mesh, or spine‑based topologies. Knowledge of EM/IR analysis, thermal‑aware clocking, and reliability modeling. Exposure to high‑speed interface clocking (e.g., SerDes, DDR, PCIe). Understanding of package‑level clock planning and signal integrity. Principal Duties & Responsibilities: Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system‑level requirements. Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of complex process flow from high‑level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages. Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects. Level of Responsibility: • Works independently with minimal supervision. • Provides supervision/guidance to other team members. • Decision‑making is significant in nature and affects work beyond immediate work group. • Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. • Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). • Tasks do not have defined steps; planning, problem‑solving, and prioritization must occur to complete the tasks effectively. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑************************** or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. Must be a U.S. citizen and eligible to receive a U.S. Government security clearance We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands‑on experience in RTL‑to‑GDSII flow, with a strong focus on Floor‑planning, Clock Tree Synthesis, Place‑n‑Route (PnR), DRC and Timing closure. This role involves architecting and implementing robust, low‑skew, power‑efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals. This role requires full‑time onsite work in San Diego, CA (5 days per week). Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Key Responsibilities: Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry‑standard tools (e.g., Innovus, ICC2). Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing, congestion, and DRC issues. Optimize design for power, performance, and area (PPA). Conduct formal equivalence checks between RTL and netlist. Support physical verification including DRC, LVS, and antenna checks. Work closely with backend teams for tapeout preparation and signoff. Excellent scripting skills (TCL, Python, Perl) for reference flow automation. Execute full‑chip and block‑level physical verification including DRC, LVS, ERC, antenna, and density checks using industry‑standard tools (e.g., Calibre, Pegasus, ICV). Customize and optimize reference physical verification flows to align with project needs and foundry requirements. Perform GDS‑to‑GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness. Debug and resolve physical verification violations, working closely with layout, design, and CAD teams. Collaborate with foundries to ensure compliance with latest design rule manuals (DRMs) and tapeout checklists. Support signoff verification, including multi‑corner/multi‑mode analysis and ECO validation. Develop and maintain automation scripts for verification flows, reporting, and regression testing. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability. Ensure timely delivery of clean GDSII for tapeout, with full verification signoff. Perform full‑chip and block‑level static timing analysis (STA) using industry‑standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners. Collaborate with RTL, synthesis, and physical design teams to ensure timing‑aware design practices. Debug and resolve setup, hold, and transition violations across various PVT corners. Drive timing closure through iterative optimization and ECO implementation. Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability. Analyze clock tree timing, including skew, latency, and jitter impacts. Support signoff timing verification, including cross‑domain timing and false/multicycle path handling. Define and implement low‑power architecture using CLP methodology across RTL and physical design stages. Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications. Customize and optimize low‑power reference flows to meet project‑specific requirements. Collaborate with RTL, synthesis, and physical design teams to integrate power‑aware features such as power gating, retention, isolation, and level shifting. Perform power‑aware static checks, simulation, and formal verification to validate power intent. Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing. Support signoff verification including power‑aware LVS/DRC, STA, and EM/IR analysis. Ensure compliance with foundry low‑power guidelines and contribute to successful tapeout. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 4+ years of experience in physical design, with a focus on clock tree design and implementation. Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design. Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime). Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies. Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis. Familiarity with low‑power design techniques, including clock gating and multi‑voltage domains. Preferred Skills: Experience with custom clock tree architectures such as H‑tree, mesh, or spine‑based topologies. Knowledge of EM/IR analysis, thermal‑aware clocking, and reliability modeling. Exposure to high‑speed interface clocking (e.g., SerDes, DDR, PCIe). Understanding of package‑level clock planning and signal integrity. Principal Duties & Responsibilities: Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system‑level requirements. Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of complex process flow from high‑level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages. Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects. Level of Responsibility: • Works independently with minimal supervision. • Provides supervision/guidance to other team members. • Decision‑making is significant in nature and affects work beyond immediate work group. • Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. • Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). • Tasks do not have defined steps; planning, problem‑solving, and prioritization must occur to complete the tasks effectively. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑************************** or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Job Description: Electrical Engineer (Multiple Levels: Electrical Designer | Electrical Engineer | Senior Electrical Engineer) We are seeking skilled and motivated Electrical professionals across multiple experience levels to join our team in the building industry. This opportunity is open to candidates ranging from Electrical Designers to experienced and Senior Electrical Engineers specializing in building systems. The ideal candidate will possess expertise in electrical engineering principles with a focus on building systems and a strong understanding of how electrical systems integrate with multidisciplinary MEP designs. A solid working knowledge of California regulations, including the California Building Code and California Electrical Code, is essential for engineering-level roles. Proficiency in utilizing Revit and BIM (Building Information Modeling) software is a key component of this position. Responsibilities and level of responsibility will be aligned with the candidate's experience, skill set, and licensure. Responsibilities: Design and Planning: Assist with or lead the development of electrical design concepts, specifications, and calculations for various building types, including multifamily, commercial, retail, industrial, and life science projects, in accordance with applicable codes and standards. Create electrical layouts, schematic diagrams, single-line diagrams, and system drawings for power distribution, lighting, and low-voltage systems. Collaborate with architects, engineers, and project stakeholders to ensure coordinated and integrated electrical system designs. Support continuous improvement of electrical design efficiency, sustainability, and cost-effectiveness while maintaining safety and compliance.. System Analysis: Perform or support load calculations, voltage drop analysis, short-circuit calculations, lighting calculations, and coordination studies, as appropriate to experience level. Assist with evaluating energy-efficient technologies and sustainable design strategies for electrical systems. Technical Documentation: Prepare detailed electrical drawings, plans, and specifications for construction documentation using AutoCAD and Revit/BIM. Generate technical reports, project documentation, and compliance materials as required by project and regulatory standards. Project Management & Coordination: Support or lead coordination of electrical designs with mechanical, plumbing, architectural, and structural disciplines. Participate in project meetings and internal design reviews. Review and coordinate electrical drawings prior to transmittal to ensure completeness and accuracy. Assist with project scheduling, budgeting, and resource planning related to electrical tasks. Quality Assurance: Conduct reviews to ensure electrical designs comply with applicable codes, standards, and project requirements. Collaborate with internal quality assurance processes to verify performance and safety of electrical installations. Client Engagement (Mid- to Senior-Level): Communicate effectively with clients and project teams regarding electrical design questions. Support responses to RFIs, submittals, and design clarifications as needed. Professional Development: Stay current with industry trends, electrical codes, and emerging technologies. Identify opportunities for innovation and improvements in electrical system design. Requirements: Electrical Designer / Junior Level: Bachelor's degree in Electrical Engineering, Electrical Design, or a related field preferred, or equivalent professional experience. Proficiency in AutoCAD; Revit experience preferred. Basic understanding of electrical building systems and construction documentation. Strong attention to detail and ability to work collaboratively. Electrical Engineer: Bachelor's degree in Electrical Engineering or a related field. Experience in electrical design for building systems. Working knowledge of the California Building Code and California Electrical Code. Proficiency in AutoCAD and Revit/BIM. Strong analytical, organizational, and problem-solving skills. Senior Electrical Engineer: Extensive experience in electrical engineering within the building industry. Strong knowledge of California codes and jurisdictional requirements. Ability to lead projects, coordinate across disciplines, and mentor junior staff. Professional Engineering (PE) licensure in California preferred but not required. Familiarity with sustainable design practices and energy efficiency is a plus. Compensation & Benefits: The compensation range is dependent on the facts and circumstances of each case. The factors considered in making compensation decisions include skill sets, experience and training, licensure and certifications, and other business and organizational needs. We offer a competitive benefits package including: A competitive salary. Medical coverage reimbursement Personal time off (PTO) Paid company holiday. Flexibility with work schedule. Employee Assistance Program If you are a Electrical professional with a passion for building systems and a desire to grow within an MEP engineering firm, we invite you to apply and join the 120 Degreez team. Other Information: 120 Degreez is an equal opportunity employer that is committed to diversity and inclusion in the workplace. We prohibit discrimination and harassment of any kind based on race, color, sex, religion, sexual orientation, national origin, disability, genetic information, pregnancy, or any other protected characteristic as outlined by federal, state, or local laws.

We are looking to bring on a senior-level Electrical Engineer to join a technical consulting team that works across a wide range of building types and industries. This role is ideal for someone who is confident in the field, strong in electrical fundamentals, and comfortable delivering clear, defensible engineering opinions to clients and legal teams. The work focuses on investigating electrical system failures and damage, determining cause and responsibility, and supporting complex matters that may involve insurance claims, disputes, or litigation. Assignments span commercial, industrial, infrastructure, municipal, and residential facilities. Responsibilities Perform on-site investigations of electrical systems and equipment to document existing conditions and damage following loss events such as fires, floods, storms, and equipment failures Analyze electrical components and systems to determine cause, origin, and contributing factors related to design, installation, construction practices, or product performance Apply applicable electrical and building codes to develop repair scope recommendations and support technical conclusions Review construction documents, drawings, specifications, and records to evaluate compliance with design intent and industry standards Provide electrical support to fire origin and cause investigations when electrical involvement is suspected Prepare clear, well-organized technical reports explaining findings, opinions, and recommendations Communicate regularly with clients, contractors, attorneys, and code officials to address technical issues and project needs Manage multiple active assignments while meeting schedules, budgets, and quality expectations Support the development and maintenance of client relationships Travel as required, sometimes on short notice Qualifications Bachelor of Science degree in Electrical Engineering from an ABET-accredited program Licensed Professional Engineer in California, with additional state licenses or the ability to obtain them preferred Minimum of seven years of electrical engineering experience, including design, field investigation, forensic work, or related technical roles Strong working knowledge of electrical and building codes including NEC, NFPA, and ICC standards Solid understanding of electrical systems, equipment, and construction practices across multiple facility types Hands-on field experience evaluating electrical systems and equipment in real-world conditions Experience estimating electrical repair or replacement scope is a plus Strong written and verbal communication skills, with the ability to explain technical issues to non-technical audiences Experience supporting litigation, including depositions, mediation, arbitration, or trial, is desirable Existing client relationships or business development experience is a strong advantage

About Arm Arm is the industry's leading supplier of microprocessor technology, offering the widest range of microprocessor cores to address the performance, power, and cost requirements for almost all application markets. With a vibrant ecosystem of over 1,000 partners and more than 150 billion processors shipped, our technology is at the heart of a computing and connectivity revolution that continues to transform the way people live and businesses operate. Job Overview Join our dynamic FPGA Prototyping team, a key part of Arm's Solutions Engineering group, as a Verification Engineer! We are a dedicated group of engineers providing a robust platform to build and test software on Arm's brand-new subsystems and System-on-Chips (SoCs). Our mission is to accelerate the development process by offering a versatile and high-performance prototyping environment that enables seamless software integration and validation. These solutions target a wide range of market segments including mobile, server, IoT, automotive, and more. As a member of this team your day-to-day work will consist primarily of driving verification of SoC RTL designs that are modified for FPGA implementation, developing and maintaining SoC verification testbench, integrating third party VIPs & FPGA specific IP models, writing Testcases in C, reusing C Testcases from internal IP/ SoC frontend team, creating test‑plans, developing tools using scripting languages like Python, Perl, Shell for automation of tasks. If you are looking for a role that combines hardware and software skills in an environment where you can make a meaningful contribution, we'd love to hear from you! Join our committed team that builds innovative FPGA solutions and collaborates closely to achieve great results. Responsibilities Implement verification strategies to ensure detailed testing of the assigned Subsystem or SoC module. Work closely with design engineers, architects, and other verification engineers to understand design requirements and plan verification. Apply excellent verbal and written communication skills to report verification progress, issues, and results to customers. Automate test cases and regression suites to improve verification efficiency and coverage. Required Skills and Experience Solid understanding of SoC Verification (using C Testcases), hardware description and verification languages e.g. SystemVerilog, Verilog, VHDL. Understanding of Computer architecture, bus protocols (e.g., AXI, AHB), and peripherals. Experience with Tcl, Python or other scripting languages. “Nice To Have” Skills and Experience Experience with ARM-based designs and/or ARM System Architectures. Familiarity with ARM debugger and trace features e.g ARM DS, DSTREAM. Knowledge of memory subsystems and/or high speed peripherals (e.g. PCIe/CXL) will be a plus, including integration of these IP models into a design. Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: ************************************** #LI-RJ1 Salary Range $241,100-$326,100 per year We value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm's approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team's needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don't discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. #J-18808-Ljbffr

- V&V Engineer/System Verification Engineer rate- $55/hr Job descriptions: V&V Engineer (Verification & Validation Engineer), Matlab/Simulink Bachelor's Engineering degree in computer science, or related field 9 plus years of experience in system/software testing in Aerospace domain Experience in embedded System/software testing is mandatory Experience in scripting or coding implementing test cases into automation test scripts is mandatory Experience in Flight Controls systems or relevant aerospace systems Experience in Avionics standards like DO-178b or ARP-4754A guidelines Execution of test scripts on test environment and debugging Defect tracking and PR process Experience in data transfer protocols such as A429, CAN, etc Experience in Tools such as DOORS, SVN or MKS Soft Skills Excellent communication and leadership abilities. Ability to manage multiple priorities and deliver within deadlines.

HCLTech is looking for a highly talented and self-motivated Electrical Design Engineer to join it in advancing the technological world through innovation and creativity. Job Title: Electrical Design Engineer Position Type: Fulltime Location: Irvine, CA Key Responsibilities: Core Expertise End-to-end New Product Development (NPD) experience including system architecture, design, rapid prototyping, integration, testing, V&V, and design transfer. Strong knowledge of medical capital systems product lifecycle and disposables (e.g., catheters, endoscopes, pumps). Hands-on design experience in analog and digital board design involving microprocessors, microcontrollers, memory, sensors, and amplifiers. Proficiency in interface protocols such as I²C, UART, SPI, USB, and PCI. Expertise in high-density cable design, harnessing, and cabling. Tools & Standards Skilled in ECAD tools (OrCAD, Allegro) for schematic generation and PCB layout, including DFx and Gerber release. Experience in component engineering and BOM creation for prototype, pilot, and production phases. Strong understanding of IEC 60601, FDA submission requirements, and medical regulatory standards. Familiarity with VAVE analysis, vendor qualification, and supplier discussions. Testing & Validation Proficient in using test equipment such as oscilloscopes, multimeters, flow meters, and signal analyzers for troubleshooting and validation. Ability to draft test protocols, generate reports, and perform bench testing, system characterization, and verification. Soft Skills Excellent communication skills and ability to collaborate effectively with cross-functional teams. Strong problem-solving mindset and attention to detail. Education & Experience Bachelor's degree in Electrical Engineering or equivalent (Master's preferred). Minimum 5+ years of relevant experience in electrical design and development. Pay and Benefits Pay Range Minimum: $85000 per year Pay Range Maximum: $130000 per year HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to ****************** for investigation. Compensation and Benefits A candidate's pay within the range will depend on their work location, skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year. How You'll Grow At HCLTech, we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior-level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best.

This position supports the engineering and design needs of the control panel and process electrical design. This position will engage with various internal and external resources to gather data for best-in-class design and final products. External resources include manufacturer representatives and customer personnel. Responsibilities Develop electrical and controls system design solutions based on engineering principles. Evaluate P&IDs to determine I/O requirements. Develop electrical schematics, panel layouts, and BOM's. Design and facilitate production of control panels per NEC & UL standards. Maintain a neat, clean, and efficient work area daily. Develop and execute QC process for quality assurance. Provide support to field electricians to ensure projects are completed as scheduled. Qualifications Experience designing industrial electrical control systems. Experience in Electrical Construction Drawings Must have knowledge and understanding of AC / DC power circuits, pushbuttons, circuit breakers, power supplies, overloads, contactors, relays, motors, VFD's, PLC's Must have knowledge of National Electrical Code (NFPA 70) Design to UL Standards for Industrial Control Panels (UL508A) (preferred) Able to interpret NEC for Control Panel to meet the NEC and or field installation. Calculate conductor sizing, de-rating, temperature de-rating. Design to hazardous location requirements for class 1, class 2, division 1 & 2 requirements. (preferred) Design to IS requirements (UL698) (preferred) Perform three phase and single-phase load calculations Perform SCCR calculations Highly organized with strong analytical skills. Safety-minded and follow safety regulations Valid Driver's License Travel Potential for up to 25% travel to client sites to evaluate and detail clients existing conditions. Specific/Special Skills Strong software knowledge in Microsoft Word, Excel and Outlook. Familiarity with AutoCAD, ePLAN, Plant 3D, Revit or similar programs. Education Technical/other training or better in Automatic Control Systems (preferred) About Us We plan, design, engineer, and build food plants for major brands across the country and the world. For the past three decades, we've focused exclusively on the food and beverage industry, helping your favorite brands put your favorite foods in the grocery store. Simply put, food isn't one thing we do, it's all we do. Dennis Group offers competitive compensation packages commensurate with experience. We provide comprehensive employee benefits including medical, dental, vision, life and disability insurance, paid time off including an open vacation policy, as well as bonus, profit-sharing, and retirement plans. Dennis Group is proud to provide equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, or genetics. JOB CODE: 1002667

Job Title: Electrical and Amphibious Engineering Technician IV Location: Various Naval Shipyards / Onboard U.S. Navy Vessels FLSA Status: Non-Exempt Clearance: Active DoD Secret (or ability to obtain) Reports To: Lead Electrical Engineer / Project Supervisor Position Summary The Electrical and Amphibious Engineering Technician IV provides advanced technical support for the installation, maintenance, troubleshooting, and testing of shipboard electrical and control systems on U.S. Navy surface combatants and amphibious class ships. The position requires in-depth knowledge of marine electrical distribution, propulsion controls, and auxiliary systems, along with the ability to perform infrared (IR) thermographic inspections, cableway assessments, and system diagnostics per NAVSEA and MIL-STD standards. Essential Duties and Responsibilities The Electrical and Amphibious Technician IV shall support repair and maintenance of surface and shipboard systems. Electrical Systems Installation and Maintenance Install, test, and maintain new and existing electrical cables, power and lighting circuits, and distribution systems operating at 4160 VAC, 1000 VDC, 450 VAC, and 115 VAC. Support ship control, propulsion, and auxiliary systems, including: Ship Service Diesel Generators (SSDGs) and Main Propulsion Diesel Engines (MPDEs) Gas/steam turbine generators and exciters Automatic Bus Transfer (ABT) switches, transformers, switchgear, and load centers Hybrid Electric Drive Systems (HEDS), Auxiliary Propulsion Motors (APM), and synchronizer controls Degaussing, cathodic protection, and battery charging systems Maintain Marine Electrical Systems, Lube Oil Purifier Heaters, Vent Fog Precipitators, and Helicopter/Aircraft Electrical Servicing Stations (HESS/AESS). System Testing and Troubleshooting Diagnose electrical faults and perform repairs on shipboard power generation, propulsion, and auxiliary control systems. Conduct testing and calibration of controllers, power analyzers, UPS systems, and converters. Verify proper operation of governor control, load shedding, reverse power relays, and circuit breaker protection systems. Infrared (IR) Survey and Analysis Perform IR thermographic inspections on electrical equipment and systems per MIP 3000 and SW210-AP-GYD-010 Thermal/Infrared Imaging Inspection Guide Book. Identify and document overheating conditions in electrical circuits, components, breakers, and control equipment. Support IR surveys on all ship classes, including engineering, propulsion, and combat systems spaces. Provide technical analysis and recommendations for corrective maintenance. Cableway Inspection and Documentation Conduct shipboard electrical cableway inspections per NAVSEAINST 9304.1. Identify hazards, deficiencies, and recommend repair priorities. Review as-built drawings and verify compliance with MIL-STD-2003 and NAVSEA Standard Items. Required Training, Licenses, and Certifications Infrared (IR) Survey Certification: Level I IR Technician (minimum 30% of personnel within 60 days of support) Level II IR Technician (at least one of the Level I technicians within 6 months) Recertification every 5 years Training source: The Snell Group Marine Electric Propulsion / High Voltage Electrical Safety Training Must be completed within 60 days of support Training source: MEBA Engineering School High Voltage Safety PPE Certification Proficiency using PPE rated for 4160 VAC IR surveys and switchboard inspections. Knowledge, Skills, and Abilities Proficient with Navy electrical documentation and NAVSEA Standard Items Skilled in electrical theory, motor controllers, circuit analysis, and power generation equipment. Experience with digital and hydraulic control systems, propulsion generators, automatic controls, and synchronization systems. Ability to interpret and apply engineering drawings, schematics, and technical manuals. Familiarity with infrared imaging tools, data interpretation, and thermographic reporting. Strong troubleshooting, analytical, and documentation skills. Experience and Education Education: Associate degree or completion of U.S. Navy Electrician's Mate "A" School, or equivalent technical training. Experience: Minimum 5-10 years of experience in shipboard electrical or marine propulsion systems, including 3+ years performing system diagnostics, cableway inspections, or IR surveys on naval platforms. Preferred: Prior U.S. Navy experience or shipyard technician experience (DDG 1000, LPD 17, LSD 47, LHD 1/8 class ships). Working Conditions Shipboard, shipyard, and industrial environments; climbing ladders, confined spaces, and exposure to high-voltage equipment. Must comply with all NAVSEA safety procedures, wear protective PPE, and maintain safety certifications. Security Clearance Must possess or be eligible for a Secret clearance.

Who we are: Globalstar pioneered personal safety by introducing its SPOT Satellite GPS Messenger in 2007. Today, leveraging its low-earth orbit (LEO) satellite constellation, Globalstar reliably connects and protects assets, transmits key operational data, and saves lives - from any location - for consumers, industrial companies and government agencies in over 120 countries. What you will be doing at Globalstar Globalstar is seeking a Spacecraft Operations Control Systems Engineer to join our satellite team. You will be responsible for mission‑critical software supporting 24×7 satellite operations. In this role, you will be a key contributor throughout the full lifecycle of the ground control system, helping ensure system reliability, operational efficiency, and a seamless user experience for satellite operators. You will work closely with satellite engineering teams, operations analysts, and third‑party software vendors to enhance system performance, troubleshoot complex issues, and support continuous improvement initiatives. This position requires a strong technical foundation, excellent problem‑solving skills, and the ability to thrive in a high‑availability, mission‑critical environment. Duties/Responsibilities: * Support, maintain, and enhance Telemetry, Tracking, and Control (TT&C) core applications and peripheral systems used in satellite operations. * Collaborate with subject matter experts to perform root‑cause analysis on reported issues, ensuring rapid resolution and adherence to high‑availability requirements for mission‑critical systems. * Assist in developing, refining, and executing efficient software release and deployment processes to minimize operational disruptions. * Participate in system architecture planning, working with subject matter experts to optimize capabilities while ensuring alignment with project scope, timelines, and budget constraints. * Create, update, and manage system documentation, technical references, and training materials to support operational readiness and knowledge transfer. * Contribute to continuous improvement initiatives by identifying functional gaps, evaluating potential solutions, and preparing proposals or recommendations for leadership review. * Provide on‑call support as required to ensure system reliability and mission continuity. What you will bring to Globalstar * Bachelor's or higher in Information Technology, Information Systems, Computer Engineering, or a related technical field. Equivalent experience may be substituted for a bachelor's degree. * 10+ years of prior experience in satellite operations or other mission‑critical environments required. * 5+ years of experience with both Linux and Windows operating systems, including hands‑on experience in operational or production environments. * Familiarity with mission‑critical, high‑availability systems and the principles required to maintain system reliability. * Experience with time series databases, visualization tools such as Grafana, multi region cloud applications, and infrastructure as code tools preferred - troubleshooting. It's a bonus if you have: * Master's or higher in Information Technology, Information Systems, Computer Engineering, or a related technical field. Equivalent experience may be substituted for a master's degree. * Experience writing Python applications * Experience working with operational hardware such as steerable antennas, motor controllers, RF equipment, and other satellite ground system components. Highly desired Skills and Competencies: * Excellent verbal and written communication skills, with the ability to clearly and concisely collaborate across departments and all levels of management. * Strong customer‑service orientation with the ability to support both technical and non‑technical stakeholders. * Demonstrated ability to act with integrity, professionalism, and maintain confidentiality. * Exceptional organizational skills and strong attention to detail. * Ability to manage multiple priorities and meet deadlines in a fast‑paced, mission‑critical environment. * Strong time‑management skills, including the ability to effectively prioritize tasks as operational needs evolve. * Ability to adapt quickly to changing project priorities and operational requirements. * Strong analytical thinking and logical reasoning abilities. * Expertise in troubleshooting methodologies, diagnostic tools, and structured problem‑solving frameworks. * Highly skilled in fault isolation techniques for complex systems. * Strong self‑motivation and willingness to tackle challenging or ambiguous technical problems. Physical Requirements: * Prolonged periods of sitting at a desk and working on a computer * Willingness and ability to travel as needed * Willingness and ability to work after regularly scheduled hours as needed * Ability to sit at a desk for prolonged periods working on a computer (4 to 8 hours) * Ability to operate the equipment used for the job * Ability to lift 15 pounds at times * Reasonable accommodation may be made to enable individuals with disabilities to perform the essential functions of this job Marginal Functions: A review of this may have omitted some of the marginal functions of the position that are incidental to the performance of the job duties and responsibilities. This job description, in no way, states or implies that these are the only duties and/or responsibilities to be performed by the employee in this position. The employee in this position will be required to follow any other job-related instructions and to perform any other job-related duties requested by his/her supervisor. What Globalstar offers: * Work/Life Balance: Paid Time Off, Paid Holidays * Financial Benefits: 401(k) Plan with Company Match, Employee Stock Purchase Program, Voluntary and Company Paid Group Life Insurance, Short- and Long-Term Disability Insurance, Medical FSA, Dependent Care, Competitive Salaries * Health & Wellness: Health Insurance, Dental Insurance, Vision Insurance, Employee Assistance Program, Comprehensive and Interactive Wellness Program

Full-time Description Automation /Controls Engineer, San Diego, CA Verus is looking for a self-motivated, organized, and results-driven Controls Engineer to join our collaborative team. Someone who is passionate about solving complex problems alongside our clients. Our clients are important to us, and we are seeking someone who enjoys a good challenge, is accountable, well-organized, and takes pride in meeting deadlines and milestones. The ideal candidate for this position has experience developing and programming various control systems. The candidate must be able to implement control strategies, design control panels, specify instrumentation, and program common PLC/HMI packages. The candidate must be comfortable working in both office and field environments. The position requires some travel domestically. Most importantly, we are looking for someone who will fit in with our existing team - someone who is authentic, personable, trustworthy, and who has a good sense of humor, approachable, and humble. RESPONSIBILITIES: The responsibilities of the Controls Engineer include, but are not limited to, the following: · Develop SCADA, HMI, and PLC programs based on control strategies and specifications · Design control panels and specify components · Develop system specifications and sequence of operations based on client requirements · Perform system commissioning and field support functions · Work with discipline leads, PMs, and other team members to manage and run programming efforts for the project. · Prioritize and set deadlines, while also being adaptable and flexible to changing needs. · Commission control system programming · Conduct effective design review meetings and interface regularly with clients regarding the scope of work, deliverable requirements, and project status. · Able to promote and market programming scope to new and existing clients. · Mentor junior controls engineers. · Able to generate and maintain full project life cycle documentation. WHAT SETS VERUS APART? Verus is a Latin word that means true, authentic, fair, and sincere. It's a word that we feel describes who we are as a firm. We pride ourselves on our client-focused approach, our innovation, and our desire to provide effective solutions to deliver our clients' business and operational objectives. We've assembled a group of industry leaders who bring unparalleled technical experience and knowledge to each of our projects. We're an employee-owned company, and this is reflected in how we work together as a team, and how we take ownership in the work we do for our clients. A few reasons to consider us: Verus employees care for and respect one another Our people and culture are genuine We invest in our employees with competitive pay and benefits We have a work hard, play hard culture and respect work/life balance There are opportunities for growth. Learn more about us at **************** Requirements · Bachelor's degree in engineering or computer science from an accredited university or equivalent experience · 15+ years' applicable experience · Experience successfully leveraging technology · Track record of success with documented results · PLC Programming (Allen-Bradley, Siemens, Modicon, GE) · HMI Programming (Ignition, Wonderware, Cimplicity, FTViewSE) · Knowledge of computer configuration and networking · Demonstrated ability to work effectively as part of a multi-disciplinary team · Self-motivated, energetic individual with a can-do attitude · Strong problem-solving and organizational skills · Excellent written and verbal communication skills

A leading tech company in San Diego is seeking a Wireless Design Verification Engineer to play a crucial role in silicon design and validation. Responsibilities include developing test benches, executing tests, and collaborating with design teams. The ideal candidate will have strong knowledge in Verilog, SystemVerilog, and UVM, along with a bachelor's degree. Competitive compensation and benefits are offered. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. ** Must be a U.S. citizen and eligible to receive a U.S. Government security clearance ** We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands‑on experience in RTL‑to‑GDSII flow, with a strong focus on floor‑planning, clock tree synthesis, place‑and‑route, DRC and timing closure. This role involves architecting and implementing robust, low‑skew, power‑efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals. This role requires full‑time onsite work in San Diego, CA (5 days per week). Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field. Key Responsibilities: Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry‑standard tools (e.g., Innovus, ICC2). Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing, congestion, and DRC issues. Optimize design for power, performance, and area (PPA). Conduct formal equivalence checks between RTL and netlist. Support physical verification including DRC, LVS, and antenna checks. Work closely with backend teams for tapeout preparation and signoff. Excellent scripting skills (TCL, Python, Perl) for reference flow automation. Execute full‑chip and block‑level physical verification including DRC, LVS, ERC, antenna, and density checks using industry‑standard tools (e.g., Calibre, Pegasus, ICV). Customize and optimize reference physical verification flows to align with project needs and foundry requirements. Perform GDS‑to‑GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness. Debug and resolve physical verification violations, working closely with layout, design, and CAD teams. Collaborate with foundries to ensure compliance with the latest design rule manuals (DRMs) and tapeout checklists. Support signoff verification, including multi‑corner/multi‑mode analysis and ECO validation. Develop and maintain automation scripts for verification flows, reporting, and regression testing. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability. Ensure timely delivery of clean GDSII for tapeout, with full verification signoff. Perform full‑chip and block‑level static timing analysis (STA) using industry‑standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners. Collaborate with RTL, synthesis, and physical design teams to ensure timing‑aware design practices. Debug and resolve setup, hold, and transition violations across various PVT corners. Drive timing closure through iterative optimization and ECO implementation. Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability. Analyze clock tree timing, including skew, latency, and jitter impacts. Support signoff timing verification, including cross‑domain timing and false/multicycle path handling. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing insights on timing risks and mitigation strategies. Define and implement low‑power architecture using CLP methodology across RTL and physical design stages. Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications. Customize and optimize low‑power reference flows to meet project‑specific requirements. Collaborate with RTL, synthesis, and physical design teams to integrate power‑aware features such as power gating, retention, isolation, and level shifting. Perform power‑aware static checks, simulation, and formal verification to validate power intent. Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing. Support signoff verification including power‑aware LVS/DRC, STA, and EM/IR analysis. Interface with EDA vendors to resolve tool issues and improve low‑power flow robustness. Participate in design reviews, providing insights on power architecture, risks, and mitigation strategies. Ensure compliance with foundry low‑power guidelines and contribute to successful tapeout. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 3+ years of experience in physical design, with a focus on clock tree design and implementation. Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design. Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime). Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies. Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis. Familiarity with low‑power design techniques, including clock gating and multi‑voltage domains. Preferred Skills: Experience with custom clock tree architectures such as H‑tree, mesh, or spine‑based topologies. Knowledge of EM/IR analysis, thermal‑aware clocking, and reliability modeling. Exposure to high‑speed interface clocking (e.g., SerDes, DDR, PCIe). Understanding of package‑level clock planning and signal integrity. Principal Duties & Responsibilities: Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates architectures, circuit specifications, logic designs, and/or system simulations based on system‑level requirements. Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of process flow from high‑level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package. Writes detailed technical documentation for EDA/IP/ASIC projects. Level of Responsibility: Works independently with minimal supervision. Decision‑making may affect work beyond immediate work group. Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). Tasks require multiple steps which can be performed in various orders; some planning, problem‑solving, and prioritization must occur to complete the tasks effectively. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits $115,600.00 - $173,400.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Compensation Package The approximate base salary range is $90,000 - $120,000 (Incumbent's final compensation is determined on experience, knowledge, abilities, etc.). Performance Bonus & Profit-Sharing Bonus. 401k + Company Match. Open Vacation Policy. Paid Holidays. Paid Parental Leave. Health, Vision, Dental, Life Insurance, Disability. Tuition Reimbursement & Professional Employee Licensing. Job Summary As a design build engineering firm and general contractor that designs and builds food and beverage processing facilities, Dennis Group's automation & controls engineers work closely with our process, packaging and building engineers to meet our clients' expectations in startup, commissioning, and qualifying their food and beverage production facilities. The role requires regular onsite presence to ensure necessary diagnoses, troubleshooting, and operational startup of our client's production lines, equipment, and facilities. Our automation & controls engineers are frequently facing engineering challenges in applying standard engineering techniques to design, develop, and maintain instrumentation or control systems. Both software and hardware design and troubleshooting skills and abilities is required for this role. Typical responsibilities include, but not limited to: Responsibilities Handles moderately complex issues and problems and refers more complex issues to higher-level engineer With general supervision, designs and troubleshoot both software and hardware necessary for control systems utilizing PLCs for integration of manufacturing systems. Automates manufacturing processes through the use of instrumentation or controls systems. Design, diagnose, and troubleshoot network infrastructures - Ethernet, DeviceNet, AS-i, Profibus etc. Develops new PLC applications, interfaces, or embedded controls Develops new or modifies existing set-up and commissioning of new facilities or upgrading of existing facilities Design, specify, wire, and procure control panel equipment, e.g. safety circuits, I/O, networks, etc. Design, specify, and procure electrical equipment, e.g. MCCs, panelboards, transformers, etc. Specify, procure, configure, and troubleshoot controls hardware and field instrumentation Assist with coordinating with other engineer disciplines Troubleshoots and resolves malfunctions and makes recommendations that will improve efficiency or quality of operations Develop bid documentation for Electrical, Automation, and Low Voltage (network, security) vendors Documents specifications and operating procedures Project primary client technical contact Interface and manage installation contractors during construction Researching Automation & Controls materials and best practices Supporting talent growth within our organization Provide coaching and/or mentoring to a subordinate group when directed by supervisor. Required Education Skills and Experience Degree in Electrical Engineering or a related field 4-7 years of experience with Allen Bradley/Rockwell, Siemens, GE Fanuc, Honeywell Systems. 4-7 years of experience in Visual Basic, SQL, MS ACCESS Database programming skills a plus 4-7 years of experience with Design and implement process network infrastructure (Ethernet, Device Net, Control Net, ProfiBus, etc.) 4-7 years of experience in an industrial manufacturing setting Database programming skills a plus Proficiency with MS Office and AutoCAD Required This role is client facing, those successful in this role are professional, self-motivated, and energetic individuals with excellent communication and inter-personal skills. Must meet travel requirement - you will spend significant time in our client's facilities during installation and startup/commissioning/qualification phases of a project - 35% to 50% of any given time of the year. Physical Requirements Prolonged periods sitting at a desk and working on a computer. Prolonged periods of standing and walking during installation, commissioning and startup. Must be able to lift-up to 30 pounds at times. Travel Requirement Up to 50% travel required to visit project site and other offices. About Us We plan, design, engineer, and build food plants for major brands across the country and the world. For the past three decades, we've focused exclusively on the food and beverage industry, helping your favorite brands put your favorite foods in the grocery store. Simply put, food isn't one thing we do, it's all we do. Dennis Group offers competitive compensation packages commensurate with experience. We provide comprehensive employee benefits including medical, dental, vision, life and disability insurance, paid time off including an open vacation policy, as well as bonus, profit-sharing, and retirement plans. Dennis Group is proud to provide equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, or genetics. JOB CODE: 1002598

Job DescriptionDescription: Automation /Controls Engineer, San Diego, CA Verus is looking for a self-motivated, organized, and results-driven Controls Engineer to join our collaborative team. Someone who is passionate about solving complex problems alongside our clients. Our clients are important to us, and we are seeking someone who enjoys a good challenge, is accountable, well-organized, and takes pride in meeting deadlines and milestones. The ideal candidate for this position has experience developing and programming various control systems. The candidate must be able to implement control strategies, design control panels, specify instrumentation, and program common PLC/HMI packages. The candidate must be comfortable working in both office and field environments. The position requires some travel domestically. Most importantly, we are looking for someone who will fit in with our existing team - someone who is authentic, personable, trustworthy, and who has a good sense of humor, approachable, and humble. RESPONSIBILITIES: The responsibilities of the Controls Engineer include, but are not limited to, the following: · Develop SCADA, HMI, and PLC programs based on control strategies and specifications · Design control panels and specify components · Develop system specifications and sequence of operations based on client requirements · Perform system commissioning and field support functions · Work with discipline leads, PMs, and other team members to manage and run programming efforts for the project. · Prioritize and set deadlines, while also being adaptable and flexible to changing needs. · Commission control system programming · Conduct effective design review meetings and interface regularly with clients regarding the scope of work, deliverable requirements, and project status. · Able to promote and market programming scope to new and existing clients. · Mentor junior controls engineers. · Able to generate and maintain full project life cycle documentation. WHAT SETS VERUS APART? Verus is a Latin word that means true, authentic, fair, and sincere. It's a word that we feel describes who we are as a firm. We pride ourselves on our client-focused approach, our innovation, and our desire to provide effective solutions to deliver our clients' business and operational objectives. We've assembled a group of industry leaders who bring unparalleled technical experience and knowledge to each of our projects. We're an employee-owned company, and this is reflected in how we work together as a team, and how we take ownership in the work we do for our clients. A few reasons to consider us: Verus employees care for and respect one another Our people and culture are genuine We invest in our employees with competitive pay and benefits We have a work hard, play hard culture and respect work/life balance There are opportunities for growth. Learn more about us at **************** Requirements: · Bachelor's degree in engineering or computer science from an accredited university or equivalent experience · 15+ years' applicable experience · Experience successfully leveraging technology · Track record of success with documented results · PLC Programming (Allen-Bradley, Siemens, Modicon, GE) · HMI Programming (Ignition, Wonderware, Cimplicity, FTViewSE) · Knowledge of computer configuration and networking · Demonstrated ability to work effectively as part of a multi-disciplinary team · Self-motivated, energetic individual with a can-do attitude · Strong problem-solving and organizational skills · Excellent written and verbal communication skills

A leading technology company is seeking a PHY Design Verification Engineer in San Diego, California. In this role, you will be crucial in pre-silicon RTL verification for wireless products, ensuring design quality with the latest methodologies. The ideal candidate will have a bachelor's degree and advanced knowledge in Verilog, SystemVerilog, and UVM. The position offers a competitive salary range from $120,300 to $181,200 and comprehensive benefits including medical coverage, retirement plans, and stock options. #J-18808-Ljbffr