Senior Electrical Engineer jobs at DRS - 6263 jobs

Western Extrusions Corporation, headquartered in Carrollton, Texas, is a leading manufacturer of high-quality extruded aluminum products. Serving critical infrastructure industries such as transportation, renewable energy, and commercial construction, the company is committed to supporting American industries. Known for fostering a learning-focused and improvement-driven environment, Western Extrusions prioritizes employee development and customer satisfaction. By combining industry-leading capabilities with exceptional service, the company continuously delivers superior quality and innovative solutions. Role Description This is a full-time, on-site role for a Senior Controls Engineer located in Carrollton, TX. The Senior Controls Engineer will be responsible for designing, implementing, and optimizing control systems to support manufacturing operations. This includes maintaining and troubleshooting process control systems, developing and programming automation solutions, and working with robotics and motion control equipment. The role also involves collaborating with cross-functional teams to improve operational efficiency and ensure the reliability of electrical and automation systems. Qualifications Expertise in Process Control and Motion Control Strong knowledge and experience in Robotics and Automation Proficiency in Electrical Engineering principles and practices Excellent Troubleshooting skills for control systems and electrical equipment Strong communication and problem-solving abilities Bachelor's degree in Electrical Engineering or a related field Experience in industrial manufacturing environments is preferred Knowledge of programming languages commonly used in automation is a plus Experienced with AC & DC electrical systems up to 480 volts Experienced with Allen Bradley PLCs, RSLogix 5000, Studio 5000, and FactoryTalk View Studio Experienced with AC Drives and motor controls ·Experienced with Ethernet/IP networking Knowledge of AutoCAD Electrical a plus. Familiarity with industrial safety and NFPA 70E a plus

corporate_fare Google Sunnyvale, CA, USA Apply Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 7 years of experience with physical design (e.g. from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure). Experience in Python, Tcl, or Perl scripting. Preferred qualifications: Experience working with external partners on Physical Design (PD) closure. Experience in Static Timing Analysis (STA), with an understanding of how to define timing corners, margins and derates. Experience with Synopsys/Cadence PnR tools. Experience with backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.). Understanding of DFT including Scan, MBIST and LBIST. Understanding of performance, power and area (PPA) trade-offs. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As an ASIC Physical Design Engineer, you will collaborate with RTL, Design for Testing (DFT), Floorplan, and full‑chip Signoff teams. Additionally, you'll solve technical problems with innovative micro‑architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full‑time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Participate in the Physical Design of complex blocks. Contribute to the design and closure of the full chip and individual blocks from RTL‑to‑GDS. Collaborate with internal logic and internal and external teams to achieve the best Power/Performance Analysis (PPA). This includes conducting feasibility studies for new microarchitectures as well as optimizing runs for finished RTL. Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr

A technology company is seeking a Principal Hardware Design Engineer to develop advanced hardware solutions for high-performance electronic systems. This role involves leading hardware design from conception to production, providing technical guidance, and mentoring. Candidates should have over 10 years of experience in hardware design, proficiency in Verilog HDL, and a strong understanding of high-speed digital systems. This hybrid position is based in California, specifically in San Jose, with competitive compensation ranging from $167K to $250K. #J-18808-Ljbffr

A leading aerospace and defense company is looking for a Senior Principal Electronics Engineer - Hardware and Software Integration Lead in San Diego. This role involves leading the development of next-generation ground system solutions, managing software supplier interactions, and coordinating various engineering efforts. Candidates should have a strong background in STEM, relevant work experience, and active security clearance. The position requires on-site work but could offer hybrid options in the future. #J-18808-Ljbffr

A leading aerospace and defense company in Baltimore is offering a SkillBridge internship for the role of Principal Electronics Engineer. This position involves the design and fabrication of Electrical Ground Support Equipment (EGSE) to support flight hardware testing. Candidates should possess a Bachelor's degree in STEM and relevant experience in hardware design. An Active Secret security clearance is also required for this role. Join us to make an impact in the defense sector. #J-18808-Ljbffr

A leading tech company is seeking an RTL Design Engineer in Sunnyvale, CA to shape the future of AI/ML hardware acceleration. The ideal candidate will work on cutting-edge TPU technology, taking part in ASIC development to enhance computational efficiency in data centers. Responsibilities include defining project scope, design, and documentation of next-generation data center accelerators, alongside collaborative efforts with cross-functional teams to drive innovations that empower billions of users globally. Comprehensive education and experience in relevant engineering fields are essential. #J-18808-Ljbffr

A leading tech company in Sunnyvale seeks a Physical Design Engineer to contribute to the development of cutting-edge TPU technology. You will collaborate with various teams to enhance design processes, focusing on innovative solutions for AI/ML applications. Candidates should have relevant experience in physical design, strong qualifications in Electrical Engineering, and skills in scripting languages like Python. The role offers a competitive salary range and numerous benefits, with a strong emphasis on diversity and inclusion. #J-18808-Ljbffr

A leading semiconductor company in Santa Clara, CA, seeks a skilled digital design engineer. The role involves RTL design, power management features, and collaboration across teams. Candidates should have strong Verilog skills and experience in IP design. A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required. This position offers an opportunity to be part of a company that values innovation and teamwork, but it is not eligible for visa sponsorship. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE As a member of the AMD, you will help bring to life cutting‑edge designs and deliver IPs to SOC. As a member of the front‑end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first‑pass silicon success. THE PERSON You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem‑solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi‑site environment are keys to being successful in this role. KEY RESPONSIBLITIES RTL design of high speed design, clock/reset/power features, IP Integration, sub‑system level design Architect and design of power management features. Design optimization for implementing power efficient IP, implementing the RTL using low power techniques Responsible for the inter‑IP integration issues resolution Own the Clock‑Domain crossing, Linting aspects of the overall design of the IP and the subsystem Work closely with FEINT, DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Architecting, micro‑architecting and documentation of the design features Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. REFERRED EXPERIENCE Extensive experience in Digital IP/ASIC design and Verilog RTL development Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification Well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects. Should possess expertise in front‑end EDA tools sign‑off and its flows Familiarity with low power design and low power flow is an added plus Ability to program with scripting languages such as Python or Perl is a plus Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements Proven interpersonal skills, leadership and teamwork Excellent writing skills in the English language, editing and organizational skills required; Skilled at prioritization and multi‑tasking Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts Knowledge of, or experience in, functional design verification or design is highly desired ACADEMIC CREDENTIALS Bachelors or Masters degree in computer engineering / Electrical Engineering This role is not eligible for visa sponsorship. LOCATION: Santa Clara, CA Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include firmware, device drivers, RTOS porting, and board bring-up. Prodapt is seeking a highly skilled and adaptable engineer to join our dynamic team, focusing on System-on-Chip (SoC) verification. In this role, you will work on complex SoC designs and collaborate with various teams to ensure the successful development and validation of our products. Sunnyvale, CA or Austin, TX 2 year Project Responsibilities Collaborate with cross-functional teams to ensure the effective verification of complex SoC designs. UVM Expertise Develop and maintain scripts using languages like Perl, Python, Unix shells, and Makefiles to automate testing and verification processes. Gain an in-depth understanding of high-speed interfaces, including PCIe, USB, NOC, NVMe, Ethernet, LPDDR5, and HBM2, to ensure seamless integration into complex SoC designs. Collaborate with lab managers to set up and manage the necessary infrastructure for emulation and verification activities. Contribute to the development of comprehensive verification plans, testbenches, and methodologies. Identify and propose improvements to streamline the emulation and verification process. Requirements Bachelor's or higher degree in Electrical Engineering, Computer Science, or a related field. ✔8+yearsof SystemVerilog/UVMexperience (IP,sub-system,or SoClevelverification) ✔Strongscriptingskills (Python,TCL,Perl,Shell)forautomationandtooldevelopment ✔EDAtoolexpertise (VCS,Xcelium,Questa,Verdi,Spyglass,etc.) ✔Experienceindebugging,root-causeanalysis,anddrivingverificationclosure ✔FamiliaritywithCPU/GPUverification,AI/ML,Networking,ormicro-architecturalperformanceverificationisaplus ✔High-speedinterfaceverification (PCIe,DDR,HBM,Ethernet,RoCE)preferred #J-18808-Ljbffr

Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include firmware, device drivers, RTOS porting, and board bring-up. A “Great Place To Work Certified™” company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of The Jhaver Group, which employs over 32,000 people across 80+ locations globally. Prodapt is seeking a highly skilled Design Verification Engineer to focus on functional and performance verification of cutting-edge GPU designs, ensuring they meet stringent quality and specification requirements. In this role, you will develop and execute verification plans, build and maintain UVM-based environments, and collaborate closely with design and architecture teams to drive verification closure on complex GPU blocks and subsystems. 6 month contract Onsite in Austin, TX Responsibilities Develop and execute comprehensive verification plans for GPU designs, including defining verification goals, test strategies, and coverage metrics. Design, develop, and maintain verification testbenches and environments using SystemVerilog, UVM, and C++ to verify GPU functionality, performance, and power-related features. Create complex test scenarios and test cases to achieve comprehensive functional and performance coverage of GPU features and micro-architecture. Analyze simulation and regression results, debug complex GPU designs, identify root causes, and drive bug resolution in collaboration with design and architecture engineers. Work closely with cross-functional teams, including design, architecture, and software, to align verification efforts with project milestones and product requirements. Maintain accurate and up-to-date documentation for verification plans, testbenches, test cases, and results to support traceability and reviews. Requirements Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field; or equivalent practical experience. 10+ years of industry experience with a Bachelor's, 8+ years with a Master's, or 6+ years with a PhD in relevant domains of ASIC/SoC/GPU/CPU development. 5+ years of hands-on experience in GPU/CPU design verification or closely related IP/subsystem verification. Strong proficiency in SystemVerilog and UVM for block-level and/or subsystem-level verification. Experience with industry-standard verification tools and simulators (e.g., VCS, Xcelium, Questa, Verdi or similar) and coverage-driven verification flows. Proficiency with scripting languages such as Python and Perl for automation, regression management, and data analysis. Demonstrated strength in debugging, root-cause analysis, and driving verification closure in complex designs. Excellent communication and interpersonal skills, with the ability to work effectively in a collaborative, cross-functional environment. #J-18808-Ljbffr

A leading technology company is seeking a skilled Design Verification Engineer to focus on functional and performance verification of GPU designs in San Jose, California. This role involves developing verification plans, maintaining UVM-based environments, and collaborating with multiple teams to ensure adherence to specifications. The ideal candidate should have a Bachelor's degree and significant experience in ASIC/SoC/GPU/CPU development, particularly in verification processes. It is a 6-month onsite contract position. #J-18808-Ljbffr

A leading semiconductor company is seeking an ASIC Design STA engineer in San Jose, CA to contribute to the development of large SoCs. You will be responsible for building and verifying timing constraints and collaborating on complex design projects. Ideal candidates should have strong SDC and EDA tool expertise, along with experience in Tcl scripting. This role offers a collaborative work environment and is hybrid. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE AMD is looking for a Senior ASIC/RTL Design Engineer to contribute to the development of large SoCs, featuring multiple physical blocks and complex timing constraints. The candidate's responsibilities will include RTL ownership and integration, building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred. THE PERSON The ideal candidate demonstrates high energy, excellent written and verbal communication skills, and a structured, organized approach to work. They are collaborative and strongly focused on achieving team and organizational goals. KEY RESPONSIBILITIES Responsible for RTL design and integration. Contribute to all aspects of SoC design including chip definition, architecture development and modeling, development of micro-architectural specification, conversion of micro-architectural specifications to logic implementation, verification, emulation, debug, synthesis and timing closure. Develop complex multi-mode/multi-corner timing constraints that are compatible for RTL and signoff. Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency. Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA (static timing analysis) checks. Collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows. Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts). Continuously review and identify areas for process improvements and early issue detection during the design phase. PREFERRED EXPERIENCE Experience with SoC designs that includes RTL design and integration. Worked with EDA tools that enable RTL quality checks. Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Ability to multitask, grasp new flows/tools/ideas. Experience in improving the methodologies. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT). Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters. Strong analytical and problem-solving skills. ACADEMIC CREDENTIALS Bachelor's or Master's degree in Electrical Engineering or Computer Engineering LOCATION San Jose This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate\'s responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred. The Person High energy candidates with strong written and verbal communication skills, and structured, well-organized work habits will be successful. Team and goal oriented are essential. Key Responsibilities Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency. Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA checks. Collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows. Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts) Preferred Experience Worked with EDA tools that enable RTL quality checks Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Ability to multitask, grasp new flows/tools/ideas. Experience in improving the methodologies. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT) Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters Strong analytical and problem-solving skills Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering Location: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A technology company in San Jose is seeking a Senior ASIC/RTL Design Engineer to contribute to the development of large SoCs. The role requires expertise in RTL ownership, complex timing constraints, and EDA tools, alongside strong communication skills. Candidates should have a Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. This is a non-remote role requiring in-person presence, and does not offer visa sponsorship. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE Adaptive and Embedded Computing Group (AECG) seeks a Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high‑speed Crypto, Network‑on‑Chip (NoC), and cutting‑edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal‑based verification environments at both block and SoC‑level to achieve first‑pass silicon success. THE PERSON The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre‑Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities Lead the verification of high‑speed Crypto, Network‑on‑Chip (NoC), cutting‑edge DRAM Memory controller (LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal‑based verification environments at IP and SoC‑level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion‑based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. Preferred Experience Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Strong understanding of state of the art of verification techniques, including assertion and metric‑driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high‑performance IP and/or VLSI designs is a plus. Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate‑level simulation, power‑aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. Academic Credentials BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. #LI-CJ2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Senior Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network‑on‑Chip (NoC), and cutting‑edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal‑based verification environments at both block and SoC‑level to achieve first‑pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre‑Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities: Lead the verification of high‑speed Crypto, Network‑on‑Chip (NoC), cutting‑edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal‑based verification environments at IP and SoC‑level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion‑based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. Proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analysed and verified system‑level Performance and QoS (Quality of Service) requirements. Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including assertion and coverage‑driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high‑performance IP and/or VLSI designs is a plus. Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate‑level simulation, power‑aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. ACADEMIC CREDENTIALS: BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD/Xilinx programmable devices. THE PERSON: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware and firmware engineers to understand the new features to be verified Take ownership of block level verification tasks Define test plans, test benches, and tests using System Verilog and UVM Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes Review functional and code coverage metrics to meet the coverage requirements Develop and improve existing verification flows and environments PREFERRED EXPERIENCE: Strong understanding of computer architecture and logic design Knowledge of Verilog, system Verilog and UVM is a must Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification Working knowledge of C/C++ and Assembly programming languages Exposure to scripting (python preferred) for post-processing and automation Experience with gate level simulation, power and reset verification ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr