Design engineer jobs in Mountain View, CA - 15,252 jobs

A leading technology company in Santa Clara is seeking a Physical Design Engineer. The role involves developing chip floor plans, implementing design methodologies, and working with EDA tools. Ideal candidates hold a BSEE, MSEE or PhD and have deep knowledge in VLSI and physical design concepts. Competitive salary ranges from $96,000 to $184,000 depending on experience. Join a diverse team in a dynamic and innovative environment. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking a Staff Power Module Design Engineer. You'll develop innovative power module products and collaborate with industry experts. The role requires a strong educational background in Power Electronics and significant experience in switching power converter design. This position offers competitive pay within a vibrant engineering team, fostering professional growth and mentorship opportunities. #J-18808-Ljbffr

A leading technology company in Santa Clara seeks an experienced ASIC Design Engineer specializing in GPU/ML Shader Core. In this role, you will define micro-architecture, implement RTL, and collaborate with various engineering teams. Ideal candidates will have experience in micro-architecture and an undergraduate degree in Computer Engineering or Electrical Engineering. Enjoy a vibrant culture that fosters innovation and teamwork, while pushing the boundaries of next-generation computing. This role does not offer visa sponsorship. #J-18808-Ljbffr

Engineers with experience in HW emulation and prototyping required to build ASIC/System on Chip (SoC) and IP for data center applications. Responsibilities Deliver high-quality emulation and prototyping models on industry-standard emulation and prototyping platforms Design, build, and execute comprehensive emulation test plans to ensure model accuracy and support pre-silicon validation efforts Lead the development and adoption of best-in-class emulation methodologies to accelerate hardware verification and software development Collaborate with Design, DV, validation, and software teams to develop tools, flows, and mechanisms that demonstrate key performance indicators such as functionality, performance, and power efficiency Enhance and mature standard interfaces including PCIe, DDRx, USB, and other interfaces on emulation components such as speed bridges, transactors, and virtual components Continuously improve the efficiency and effectiveness of emulation components and workflows for testing, debugging, analysis, and automation Partner with vendors to troubleshoot issues, deploy new emulation capabilities, and drive ongoing improvements Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ Years of experience with EDA tools and scripting languages used to build tools and flows for complex emulation environments Experience with current emulation technologies and methods, simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods Preferred Qualifications Track record of successful ASIC/SoC where emulation is a critical workflow Experienced in compilation and build flows and creating build flows from scratch with necessary design modifications for emulation Experience in creating emulation systems for Multi-chip/SoC/IP designs and understanding of trade-offs between emulation resource consumptions, performance and ease of debug Experience managing multiple programs and enabling verification to achieve coverage closure and SW to achieve left shift of software development Experience with SystemVerilog and C++ to model RTL components and transactors Experience with post-silicon bring up, debug, and reproducing issues on emulators Experience with cadence (palladium/protium) and Synopsys (zebu) tools Experience with scripting languages such as Python, Perl and TCL Public Compensation $142,000/year to $203,000/year + bonus + equity + benefits Industry Internet Equal Opportunity Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com. #J-18808-Ljbffr

About ALSO. We're ALSO, an electric mobility company originally conceived as a part of Rivian. We're a passionate team of builders, dreamers, doers and innovators, focused on creating entirely new (not to mention, innovative and delightful) vertically integrated, small EVs designed to meet the global mobility challenges of today and tomorrow. Our mission is to inspire everyone to ride ALSO-replacing many local car, truck and SUV miles with ones on vehicles that are more affordable, more enjoyable and 10-50x more efficient. We are looking for an exceptional mechanical engineer that will be responsible for drivetrain structure design engineering. What You Will Do Design and 3D modeling of mechanical components and assemblies including high pressure die casting, gravity casting, injection molded plastics, sheet metal, fasteners, etc. Create drawing packages and manufacturing instructions for parts and assemblies. Execute a design verification process and report (DVP&R) to validate requirements. Topology optimization, blending strength and NVH objectives to help identify necessary ribbing structure within the available package space to meet structural and NVH constraints. Sealing analysis with expertise in component hyper‑elastic analysis NVH analysis (modal, frequency response, mount mobility) Linear static stress analyses for complete drive unit systems Develop and maintain program‑specific design failure mode and effects analyses (DFMEAs). Coordinate validation efforts between Tier 1 and Tier 2 suppliers Collaborate with other mechanical, electrical, control, manufacturing, and test engineers to take designs from a clean sheet through prototypes and into mass production. Assist hands‑on in engineering prototype builds and component fabrication. What You Will Bring Experience with high volume manufacturing processes such as injection molding, stamping, etc. Proficiency in 3D/2D modeling tools (Catia V5/V6 preferred but not required) Proficiency in hands‑on mechanical integration, assembly, troubleshooting and documentation of mechanical and electromechanical systems. Proficiency with CAE analysis software package like Ansys, Abaqus, Hyperwork, or similar Proficiency with understanding boundary conditions and their application on various drive unit components to capture realistic interactions. Experience with Matlab and/or Python. Knowledge of geometric dimensioning and tolerancing (GD&T) and tolerance stack‑up analyses Proficiency with understanding loads and their applications on various drive unit components Strong fundamental knowledge of material properties, heat treatment Strong fundamental knowledge of statics, dynamics, and mechanics of materials The salary for this position ranges from $180,000 to $200,000 per year, depending on experience and qualifications. Why ALSO. We're passionate about helping the world find a better way to get there-wherever it is you're headed. We're located in the heart of Silicon Valley and have brought together a world‑class team from some of the biggest brands in the technology, automotive, cycling, outdoor recreation and retail spaces. Together we're working hands‑on to imagine, design and build an entirely new solution to a global set of transportation challenges. Perks and Benefits Robust health coverage. Excellent health, dental and vision insurance covered up to 100% by ALSO with FSA & HSA options. One Medical membership and dedicated insurance advocates. Rich fertility and family building benefits with Progyny. Flexible time off. 401(k) match. #J-18808-Ljbffr

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best‑in‑class engineers to help maximize Starlink's utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting‑edge next‑generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network. Responsibilities: Evaluate architectural trade‑offs based on features, performance requirements and system limitations Define micro‑architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design Work closely with verification team to ensure all aspects of the design are covered and verified Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check) Participate in silicon bring‑up and validation Basic Qualifications: Bachelor's degree in electrical engineering, computer engineering, or computer science 5+ years of experience in RTL implementation Preferred Skills And Experience: Ability to solve complex problems including clock domain crossings and power optimization ASIC/SoC system integration experience Experience with multicore CPU subsystem design Experience with standard bus protocols (e.g. AXI, AHB, etc.) Experience with embedded processors Experience with high speed and low power design techniques Scripting skills (Python, TCL, etc.) Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II) Ability to work in a dynamic environment with changing needs and requirements Team‑player, can‑do attitude and ability to work well in a group environment while still contributing on an individual basis Enjoys being challenged and learning new skills Additional Requirements: Must be willing to work extended hours and weekends as needed Compensation & Benefits: Pay range: $170,000.00 - $230,000.00 per year. Your actual level and base salary will be determined on a case‑by‑case basis and may vary based on the following considerations: job‑related knowledge and skills, education, and experience. Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long‑term incentives, in the form of company stock, stock options, or long‑term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long‑term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year. Itar Requirements: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here. SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. Applicants wishing to view a copy of SpaceX's affirmative action plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to ************************. #J-18808-Ljbffr

Physical Design Engineer Job at Apple, Cupertino, CAJob Description Physical Design Engineer Department: Hardware Imagine what you can do here. Apple is a place where extraordinary people gather to do their best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Description Apple Inc. has the following available in Cupertino, California, and various unanticipated locations throughout the USA. Responsible for physical design and implementation of partitions. Build partition architecture and drive physical aspects early in the design cycle. Physically implement design partitions (from netlist to tape-out) for a highly complex System-on-Chip (SoC) utilizing state-of-the-art process technology. Work on partition-level place and route (P&R) implementation, including floor planning, clock and power distribution, timing closure, physical and electrical verification. Complete netlist to GDSII implementation for partitions meeting schedule and design goals. Oversee timing, physical, and electrical verification, and drive the signoff closure for the partitions. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. The base pay range for this role is between $151,091 - $214,500/year, depending on skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees have the opportunity to participate in Apple's stock programs, receive benefits including medical and dental coverage, retirement benefits, discounts, free services, educational reimbursement, and potential bonuses or relocation assistance. Learn more about Apple Benefits. Minimum Qualifications Master's degree or foreign equivalent in Electrical Engineering or related field. 2 years of relevant experience. 1 year of experience with each of the following: Encounter Design System tool, QRC, Calibre, Voltus, Primetime. Preferred Qualifications N/A Apple is an equal opportunity employer committed to inclusion and diversity. We promote equal opportunity for all applicants regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics. Note: Apple benefits, compensation, and employee stock programs are subject to eligibility and other terms. This job posting appears to be active and does not indicate it is expired. #J-18808-Ljbffr

Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams Chip/Block Level Floorplanning and pin assignment Review top-level/block-level clock specifications for completeness and feasibility Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing) Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification) Presentations and Customer Interaction in customer meetings Necessary Qualifications: BSEE, with 9+ years of experience or equivalent experience. MSEE preferred. Experience in ASIC Physical Design; Experience in an SoC product development organization with tapeouts at 28nm/16nm design nodes. Hands-on Experience with implementation EDA tools like ICC2/Innovus. Scripting (Perl/Tcl/Python) is required. Good understanding of ASIC frontend design. Experience in both Flat and Hierarchical layouts. Strong problem‑solving skills and ability to analyze and resolve physical design issues related to library, timing constraints or CAD tools is required. Experience with power analysis and IR‑drop tools (primepower/Redhawk) and Static Timing Analysis (Primetime). Experience with Physical Verification and fix PV errors in layout. Expert handling of Verilog HDL based Netlists, Physical design libraries. Team player with good interpersonal and communication skills; ability to explain processes and answer customer questions during meetings. Compensation: $190,000.00 - $200,000.00 per year MAKING THE INDUSTRY'S BEST MATCHES DBSI Services is widely recognized as one of the industry's fastest growing staffing agencies. Thanks to our longstanding experience in various industries, we have the capacity to build meaningful, long‑lasting relationships with all our clients. Our success is a result of our commitment to the best people, the best solutions and the best results. Our Story: Founded in 1995 Privately Owned Corporation Managing Partner Business Model Headquartered in New Jersey US Based Engineers Only Methodology and Process Driven Top performing engineers are the foundation of our business. Our priority is building strong relationships with each employment candidate we work with. You can trust our professional recruiters to invest the time required to fully understand your skills, explore your professional goals and help you find the right career opportunities. #J-18808-Ljbffr

About Commonwealth Fusion Systems: Commonwealth Fusion Systems is on a mission to deliver the urgent transition to fusion energy. Combining decades of research, top talent, and new technologies, we're designing and building commercially viable fusion power plants. And working with policymakers and suppliers to build the energy industry of the future. We're in the best position to make it happen. Since 2018, we've raised nearly $3 billion in capital, making us the largest and leading private fusion company in the world. Now we're looking for more thinkers, doers, builders, and makers to join us. People who'll bring new perspectives, solve tough problems, and thrive as part of a team. If that's you and this role fits, we want to hear from you. Principal Mechanical Engineer We're looking for a Principal Mechanical Engineer to join our R&D and equipment design team to help build the next generation of thin‑film deposition technology. The Principal Mechanical Engineer will be responsible for the design and implementation of advanced R&D equipment and complex machinery. This role requires strong technical expertise, procedural discipline, and the ability to collaborate across engineering and technology functions to ensure safe, reliable, and high‑performance equipment. If you enjoy working on complex design problems, mentoring others, and solving problems in a collaborative, fast‑paced environment, this is your opportunity to make an impact. What you'll do: Lead the design and implementation of advanced R&D equipment for thin‑film processing, including ownership of key mechanical modules and sub‑systems Define system level requirements and drive innovative design concepts to meet these requirements Lead design reviews for overall mechanical system and key mechanical subsystems Generate and maintain interfaces with other engineering subsystems Report on and be accountable for project progress to stakeholders Work effectively within a multi‑disciplinary team of top scientists and engineers Mentor engineering staff for effectiveness and delivery of on‑time & in‑spec outcomes Get things done: drive projects, consistently deliver, act with speed What we're looking for: Master's degree in Mechanical Engineering or related field (or equivalent industrial experience) 15+ years of experience with at least 7 years of experience working as a principal mechanical design engineer or engineering team lead in a relevant context: design and implementation of R&D systems and manufacturing equipment Ability to conceive of novel solutions for complex engineering systems in challenging environments Expertise with 3D modeling; preferred experience with SolidWorks and NX Experience with COMSOL, ANSYS or other FEA tools Ability to select and qualify vendors for components or subsystems Demonstrated ability to lead in either direct or matrix structures Strong verbal and written communication skills and a dedication to high‑quality documentation Bonus points for: Ph.D. in Mechanical Engineering or related field (or equivalent industrial experience) Prior success building first‑of‑kind or experimental tools for material science or semiconductor R&D Familiarity in applying Semi‑S8, ASME, ACI, ASTM, and other mechanical standards to design solutions Experience with the operation of equipment in a manufacturing environment Must‑have Requirements: Ability to occasionally lift up to 50 lbs Perform activities such as stooping, climbing, standing, or sitting for extended periods of time Dedication to safety to mitigate industrial hazards that may include heat, cold, noise, fumes, strong magnets, lead (Pb), high voltage, and cryogenics Willingness to travel or work required nights/weekends/on‑call occasionally $150,000 - $225,000 a year Benefits Competitive compensation with equity 12.5 Company‑wide Holidays Flexible vacation days 10 sick days Generous parental leave policy Health, dental, and vision insurance 401(k) with employer matching Professional growth opportunities Team‑building activities #LI‑Onsite At CFS, we excel in fast‑paced environments, driven by our values of integrity, execution, impact, and self‑critique. As we grow, we're eager to bring on mission‑driven folks who offer diverse perspectives and fresh ways to tackle challenges. We value diversity deeply and are proud to be an equal opportunity employer by choice. We consider all qualified applicants equally, regardless of race, color, national origin, ancestry, citizenship status, protected veteran status, religion, physical or mental disability, marital status, sex, sexual orientation, gender identity or expression, age, or any other basis protected by law. This role requires compliance with U.S. laws concerning the export of controlled or protected technologies or information (collectively, “Export Control Laws #J-18808-Ljbffr

A leading technology company in San Mateo is seeking an exceptional founding design engineer to create intuitive product experiences. The role requires expertise in TypeScript and React, with responsibilities that include crafting polished user interfaces and translating advanced AI technologies into high-quality products. Candidates should have a strong design sensibility and experience shipping products used by millions. This opportunity offers competitive compensation and a dynamic work culture. #J-18808-Ljbffr

About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical designs, and will help Etched as we work to improve iteration speed on physical design. Representative projects Supervise the outsourcing of physical design to a 3rd party service Deeply understand what is involved in physical design Running Physical Design flows to close blocks, support ASIC infrastructure, automate Physical Design flows, improve CAD infrastructure Drive dashboards that show the convergence of projects related to Physical Design Optimize tool flows, working with EDA vendors to incorporate the latest features Accountable for block level closure Requirements 2+ years of previous experience with PD Tools, flow, and design methodology from RTL synthesis to GDSII sign-off Experience with back-end design and timing closure on 3nm-7nm Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis Deeply creative and able to think from first principles Desired qualifications: Familiarity with transformer models and machine learning. Familiarity with Cadence or Synopsys automated RTL-to-GDSII flows Ability to program with Python or another scripting language. We encourage you to apply even if you do not believe you meet every single qualification. Benefits: Full medical, dental, and vision packages, with generous premium coverage Housing subsidy of $2,000/month for those living within walking distance of the office Daily lunch and dinner in our office Relocation support for those moving to West San Jose Compensation Range $150,000 - $275,000 How we're different: Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. #J-18808-Ljbffr

Altera .# **Job Details:**### ## **Job Description:****About the Role:**As a Physical Design Engineer at Altera, you will play a critical role in the backend implementation flow - from RTL/netlist through GDSII/tape-out for FPGA/SoC devices. You will collaborate with architecture, logic design, DFT, CAD/EDA, and manufacturing teams to achieve performance, power, and area (PPA) goals, with a particular emphasis on programmable logic structures, block and full-chip integration, and the unique demands of FPGA technologies (e.g., configurable logic blocks, routing fabrics, I/O rings, on-chip power domains).**Key Responsibilities:*** Execute physical design implementation tasks (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist to GDSII.* Apply PPA optimization techniques (performance/timing closure, power reduction, area efficiency) across block-level and full-chip hierarchies.* Collaborate with front-end design, architecture, and CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets, and DFT insertions are met.* Develop and enhance physical design flows, methodologies, scripts, and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR, and reduce manual intervention.* Participate in timing, power, EM/IR integrity, signal/power noise, and DRC/LVS/ERC verification for sign-off readiness.* Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization.* Debug physical design issues and interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.**$127,400 - $184,400 USD**We use artificial intelligence to screen, assess, or select applicants for the position.### ## **Qualifications:****Minimum Qualifications:**Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 6+ years of experience in:* Hands-on digital/SoC physical design (synthesis through P&R and sign-off).* Industry-standard EDA tools (e.g., Synopsys IC Compiler/Fusion, Cadence Innovus/Encounter, PrimeTime, STAR-RCX, Calibre) for high-speed digital ASIC/SoC implementation.* Scripting/programming (TCL, Python, Perl, shell) for flow automation and productivity enhancement.* Physical design flow: floorplanning, CTS, placement, routing, power domain gating, clock domain crossing, multi-power domain design, timing closure, ECOs, and DRC/LVS/DFM resolution.* Power/IR analysis, signal/power integrity reporting, and corrective action planning.* Interfacing with front-end teams (RTL, architecture), CAD/EDA tool teams, and manufacturing/packaging teams.**Preferred Qualifications:*** Experience with advanced process nodes (7nm, 5nm or smaller) or FPGA/programmable logic device flows.* Familiarity with FPGA architecture: routing fabrics, programmable logic blocks (PLBs), on-chip networks, I/O rings, static/dynamic reconfiguration.* Expertise in low-power design methodologies, power grid design, power gating, multi-voltage domain implementation, and power sign-off flows.* Prior exposure to full-chip integration flows (block-to-chip convergence) and high-frequency (1 GHz+) timing closure.* Experience in high-volume manufacturing environments, including yield and DFM/DFY considerations.* Experience mentoring or leading small physical design sub-teams or owning major P&R blocks.### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr

A leading tech company in California is seeking a Technical Marketing Lead who will own marketing systems and build automation tools. You'll create AI-native workflows and work with tools like Claude Code and Cursor. Ideal candidates will have 4-8 years of B2B marketing experience and a track record of building and deploying effective systems. This is a chance to take ownership from day one and prove yourself in a rapidly evolving environment. #J-18808-Ljbffr

At Array Labs, we are building the world's most advanced satellite radar constellation to create a high-resolution 3D digital twin of the Earth. Our mission is to provide "lidar-like" 3D data and imagery from space, serving critical applications for both commercial and defense customers. This is a deep tech challenge in the truest sense. We're solving complex problems that span hardware, software, and data-from designing satellite systems for the harshness of space to building the massive "data factory" that turns raw sensor data into beautiful 3D products. We are looking for first-principles engineers who want to build, deploy, and scale a one-of-a-kind, vertically-integrated system from the ground up. The hardware engineering team is responsible for the analysis and design of our satellite and ground-station electronics, which spans the range of radar, communications, power management and processing subsystems. As a lead engineer, you will own the design of hardware solutions that will be integrated into satellites and cutting-edge ground infrastructure. You will work cross-functionally with our antenna, RF, communications and radar engineers to rapidly move from clean-sheet designs to full operational deployment in space. In this role, you'll help shape the design of the world's first formation-flying radar imaging constellation, which will deliver a quantum-leap in humanity's ability to rapidly and comprehensively understand our ever-changing world. Responsibilities Develop advanced electronic platforms, from architecture to manufacturing Work closely with software, firmware, RF, antenna, digital, and mechanical design engineers to design and validate state-of-the-art spacecraft electronics Create requirements, perform system trades, select components, capture schematics, design complex electronic assemblies and manage manufacturing Lead prototyping, hardware bring-up, debug, manufacturing, and test campaigns. Rapidly iterate on and improve electronic designs based on laboratory, environmental and on-orbit testing Basic Qualifications B.S. in Electrical Engineering, or a related field. Experience in electronics design, fabrication, and test Excellent teamwork and communication skills Learns new concepts rapidly, completely, and in a self-directed manner High levels of self-motivation and personal accountability Ability to work in a fast-paced environment under significant time constraints Preferred Skills and Experience Bachelor's or Master's degree in electrical engineering, or a related field 4+ years of proven electrical engineering work experience with full-life cycle development (concept to production) of consumer electronics, power electronics, communications, automotive, aerospace, and/or robotics Solid background in high-speed board design, simulation, and validation techniques including PCB stack-up, PCB fabrication, floorplanning, component selection, placement and routing, simulation and measurement Solid background in electromagnetic theory and RF fundamentals such as s-parameters, transmission lines, and broadband impedance matching Hands-on experience designing high-performance platforms including compute (SoCs, FPGAs, MCUs),storage (DDR, SSDs),high-speed interfaces (PCIe, SPI, JESD204B),RF components (PAs, LNAs, switches) Proficiency with schematic capture and layout using CAD tools such as Altium Designer, Allegro, and ORCAD Experience with EMC requirements and EMI mitigation techniques Expertise in signal and power integrity simulation and measurement Expertise in EM and thermal simulation of printed circuit boards Experience with analysis and simulation tools such as LTSPICE, ADS and Microwave Office Experience with data analysis and programming in MATLAB or python Hands-on experience with test equipment such as oscilloscopes and network analyzers ITAR Requirements To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Equal Opportunity Employer Array Labs is an Equal Opportunity Employer. Employment decisions are made on the basis of merit, competence, and job qualifications and will not be influenced in any manner by gender, color, race, ethnicity, national origin, sexual orientation, religion, age, gender identity, veteran status, disability status, marital status, mental or physical disability or any other legally protected status. $U150,000 - $U300,000 a year Interview Process We will conduct three interviews via Zoom; the typical process takes around 2-4 weeks to complete from start to finish. Hiring and Compensation Strategy Our hiring and compensation strategy is simple: 1) find uncommonly good people 2) pay them uncommonly well You can anticipate competitive pay, with high flexibility between salary and equity-based compensation. Why you should join Array Labs Array Labs is launching a constellation of satellites to create the first high-resolution, real-time, three-dimensional model of Earth. Our next-generation satellite technology will offer image quality 60x greater than traditional techniques, profoundly expanding humanity's ability to understand and respond to events on a global scale. In forging an affordable, accessible, accurate representation of Earth, our work has the potential to transform the face of dozens of fields, including autonomy, telecommunications, disaster relief, gaming, climate science, defense and construction. #J-18808-Ljbffr

A global technology company is looking for a seasoned software engineer to enhance AI capabilities within their observability platform. Candidates should have a strong background in AI/ML systems, cloud computing, and robust technical leadership. This role is pivotal in driving innovation in data analysis and delivering scalable solutions. The ideal candidate will thrive in an agile environment and provide mentorship to junior engineers. Enjoy competitive salaries and benefits while contributing to impactful technology solutions. #J-18808-Ljbffr

An automotive giant is seeking a Staff ML Engineer for their ML Compute Platform to scale backend services and contribute to AI infrastructure. Responsibilities include designing software components, improving system efficiency, and leading initiatives. Candidates should have 7+ years of experience and expertise in languages like Go, C++, or Python, as well as a solid background in distributed systems. Join a team that's transforming mobility and tackling complex engineering challenges with AI applications. #J-18808-Ljbffr

Change the world. Love your job. We are seeking a highly skilled and experienced Analog and Mixed Signal Designer to drive the development of leading edge GaN and Si smart power stages, drivers and controllers, targeting the next gen solutions to power High performance computing. The ideal candidate will have a very strong analog design background, detailed familiarity with DC/DC converters and hands on experience in developing multiple power product families. Key Responsibilities: Conceptualize, design, develop and verify various mixed signal Ips associated with developing best in class power products Drive innovation in circuit design and packaging to address industry challenges in power density and thermal management associated with HPC solutions Collaborate with world-wide cross-functional teams, including layout, process technology, test engineering, and product teams Ensure designs meet technical specifications, project timelines, and quality standards Identify and mitigate design risks, ensuring robust circuit performance under process, voltage, and temperature (PVT) variations Stay updated on industry trends, emerging technologies, and best practices in HPC space Drive continuous improvement in design methodologies, tools, and workflows #J-18808-Ljbffr

A leading technology research organization in California seeks a machine learning engineer to develop foundational models for robotics. The role involves enhancing hardware infrastructure, building APIs for data handling, and designing evaluation metrics. Ideal candidates have hardware and communication protocol experience, along with strong software skills in Python and a passion for robotics. Competitive pay ranges from $176,000 to $264,000, with a comprehensive benefits package. #J-18808-Ljbffr

A leading technology firm in California is looking for an experienced Staff Machine Learning Engineer. In this role, you will drive the technical direction of machine learning technology, design and build impactful solutions, and lead cross-team initiatives. The ideal candidate has extensive experience in machine learning and is skilled in collaboration and mentorship. This position offers competitive compensation with equity options and emphasizes a diverse and inclusive workplace. #J-18808-Ljbffr