Full Job Description
Have you taken a career break and had your resume rejected because of your resume gap? Intel is offering 16-week paid returnships for experienced professionals ready to return to the workforce.
If you have taken a break of at least one year for the following reasons we welcome, you to apply:
Starting or raising a family Military service/military spouse Community service/volunteer work Caring for a family member or self Teaching
At Intel we are excited to have a Return-to-Work program because we appreciate the skills individuals who are returning to work can offer. This program offers you a chance to revamp your skills, update your resume with new experience, and make connections with others transitioning back to the workforce.This position is hybrid during the 16-week returnship program. The goal of this program is to hire individuals who were successful throughout the program duration. A full-time offer will be hybrid.By applying to this posting your resume and profile will become visible to Intel's Recruiting team, and will allow them to consider you for current/future job openings aligned with the skills and positions listed below. You'll be considered for multiple roles within the Design Enablement team of our Technology Development Organization.
Responsibilities may be quite diverse and are technical in nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job.
Qualifications:
Minimum Qualifications:
Candidates must have been out of the paid workforce for at least one year.Bachelors or Master's degree in Electrical Engineering, Computer Science, Computer Engineering or related field with Industry experience in at least one the following areas:Foundry design rules and layout concepts on advanced process nodes Experience with layout and layout tools on chips Design rule checking (DRC) and Layout vs Schematic (LVS) Familiarity with scripting or programming languages, such Perl, Python, TCLAnalog Circuit DesignDevice physics DRC/LVS/Extraction runsets Custom or ASIC layout design CMOS silicon process technology OR VLSI design.EDA Tools: Cadence Virtuoso or Custom Compiler
Job Type:
Intel Contract Employee
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
US, California, Folsom, US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, Austin
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.