Electrical engineer internship jobs in Santa Cruz, CA - 877 jobs

A leading technology company in Santa Clara is seeking a Physical Design Engineer. The role involves developing chip floor plans, implementing design methodologies, and working with EDA tools. Ideal candidates hold a BSEE, MSEE or PhD and have deep knowledge in VLSI and physical design concepts. Competitive salary ranges from $96,000 to $184,000 depending on experience. Join a diverse team in a dynamic and innovative environment. #J-18808-Ljbffr

Engineers with experience in HW emulation and prototyping required to build ASIC/System on Chip (SoC) and IP for data center applications. Responsibilities Deliver high-quality emulation and prototyping models on industry-standard emulation and prototyping platforms Design, build, and execute comprehensive emulation test plans to ensure model accuracy and support pre-silicon validation efforts Lead the development and adoption of best-in-class emulation methodologies to accelerate hardware verification and software development Collaborate with Design, DV, validation, and software teams to develop tools, flows, and mechanisms that demonstrate key performance indicators such as functionality, performance, and power efficiency Enhance and mature standard interfaces including PCIe, DDRx, USB, and other interfaces on emulation components such as speed bridges, transactors, and virtual components Continuously improve the efficiency and effectiveness of emulation components and workflows for testing, debugging, analysis, and automation Partner with vendors to troubleshoot issues, deploy new emulation capabilities, and drive ongoing improvements Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ Years of experience with EDA tools and scripting languages used to build tools and flows for complex emulation environments Experience with current emulation technologies and methods, simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods Preferred Qualifications Track record of successful ASIC/SoC where emulation is a critical workflow Experienced in compilation and build flows and creating build flows from scratch with necessary design modifications for emulation Experience in creating emulation systems for Multi-chip/SoC/IP designs and understanding of trade-offs between emulation resource consumptions, performance and ease of debug Experience managing multiple programs and enabling verification to achieve coverage closure and SW to achieve left shift of software development Experience with SystemVerilog and C++ to model RTL components and transactors Experience with post-silicon bring up, debug, and reproducing issues on emulators Experience with cadence (palladium/protium) and Synopsys (zebu) tools Experience with scripting languages such as Python, Perl and TCL Public Compensation $142,000/year to $203,000/year + bonus + equity + benefits Industry Internet Equal Opportunity Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com. #J-18808-Ljbffr

A technology firm is seeking an experienced Front-End SoC/ASIC Design Engineer for their SoC business unit. This role involves supporting design execution phases, ensuring project milestones are met while maintaining quality, and collaborating with global teams. Candidates must have a Bachelor's in Electrical Engineering, 5+ years of experience in ASIC front-end design, and skills in digital design and micro-architecture. Compensation ranges from $180,000 to $200,000 annually. #J-18808-Ljbffr

Quantum computing holds the promise of humanity's mastery over the natural world, but only if we can build a real quantum computer. PsiQuantum is on a mission to build the first real, useful quantum computers, capable of delivering the world-changing applications that the technology has long promised. We know that means we will need to build a system with roughly 1 million qubits that supports fault tolerant error correction within a scalable architecture, and a data center footprint. By harnessing the laws of quantum physics, quantum computers can provide exponential performance increases over today's most powerful supercomputers, offering the potential for extraordinary advances across a broad range of industries including climate, energy, healthcare, pharmaceuticals, finance, agriculture, transportation, materials design, and many more. PsiQuantum has determined the fastest path to delivering a useful quantum computer, years earlier than the rest of the industry. Our architecture is based on silicon photonics which gives us the ability to produce our components at Tier-1 semiconductor fabs such as GlobalFoundries where we leverage high-volume semiconductor manufacturing processes, the same processes that are already producing billions of chips for telecom and consumer electronics applications. We also benefit from the quantum mechanics reality that photons don't feel heat or electromagnetic interference, allowing us to take advantage of existing cryogenic cooling systems and industry standard fiber connectivity. In 2024, PsiQuantum announced two government-funded projects to support the build-out of our first Quantum Data Centers and utility-scale quantum computers in Brisbane, Australia and Chicago, Illinois. Both projects are backed by nations that understand quantum computing's potential impact and the need to scale this technology to unlock that potential. And we won't just be building the hardware, but also the fault tolerant quantum applications that will provide industry-transforming results. Quantum computing is not just an evolution of the decades-old advancement in compute power. It provides the key to mastering our future, not merely discovering it. The potential is enormous, and we have the plan to make it real. Come join us. There's much more work to be done and we are looking for exceptional talent to join us on this extraordinary journey! Job Summary The mission of PsiQuantum's Principal Hardware Design Engineer role is to support the Electronics team by owning hardware designs integral to the underlying system of the quantum computer. This engineer will collaborate in cross-functional teams of thermal, mechanical, firmware, optical engineers. The designs will meet the requirements of the overall system architecture and physical framework of the quantum computer. Responsibilities Design, create schematics, and oversee PCB layout of analog and digital circuitry consisting of but not limited to high-speed transceivers, 10+ Gbps electrical and optical data links, FPGA's, microcontrollers, clock distribution, and power distribution. Ensure signal integrity and EMI suppression is accounted for in all designs. Design and create test set-ups for testing of electro-optic modules. Characterize, optimize, and debug analog, digital, and electro-optic circuitry using equipment such as mixed signal & sampling oscilloscopes, vector network analyzers, signal generators, multimeters, DC power supplies. Develop software to drive measurements. Analyze data and extract key performance parameters. Maintain detailed documentation of hardware designs, test results, and design changes. Software tools: Orcad Schematic Capture and Allegro PCB Layout C++, Python, RTL (VHDL or Verilog) Keysight PathWave ADS Microsoft Office Experience / Qualifications 12 years of experience with a Master Degree. 8-15 years of experience with a B.S. Degree. Results oriented. Delivers on commitments. Attention to detail. Data-driven in decision-making. Strong problem-solving skills. Proven team player with an ability to work effectively across departments, sites, time zones in direct and matrix team environments. Excellent verbal and written communication skills with an ability to communicate effectively to a variety of audiences ranging from senior leadership and technical experts to entry-level staff. PsiQuantum provides equal employment opportunity for all applicants and employees. PsiQuantum does not unlawfully discriminate on the basis of race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, gender expression, national origin, ancestry, citizenship, age, physical or mental disability, military or veteran status, marital status, domestic partner status, sexual orientation, genetic information, or any other basis protected by applicable laws. Note: PsiQuantum will only reach out to you using an official PsiQuantum email address and will never ask you for bank account information as part of the interview process. Please report any suspicious activity to *************************. We are not accepting unsolicited resumes from employment agencies. U.S. Base Pay Range: $230,000 - $250,000 USD. Bay Area Pay Range: $240,000 - $260,000 USD. #J-18808-Ljbffr

A leading satellite technology company is seeking a Lead Engineer to oversee the design of advanced satellite electronics. You'll collaborate with cross-functional teams to construct cutting-edge platforms suitable for space. The ideal candidate has a B.S. in Electrical Engineering and 4+ years in electronics design. This role offers competitive compensation ranging from $150,000 to $300,000 annually and the opportunity to work on transformative satellite technology. #J-18808-Ljbffr

Change the world. Love your job. We are seeking a highly skilled and experienced Analog and Mixed Signal Designer to drive the development of leading edge GaN and Si smart power stages, drivers and controllers, targeting the next gen solutions to power High performance computing. The ideal candidate will have a very strong analog design background, detailed familiarity with DC/DC converters and hands on experience in developing multiple power product families. Key Responsibilities: Conceptualize, design, develop and verify various mixed signal Ips associated with developing best in class power products Drive innovation in circuit design and packaging to address industry challenges in power density and thermal management associated with HPC solutions Collaborate with world-wide cross-functional teams, including layout, process technology, test engineering, and product teams Ensure designs meet technical specifications, project timelines, and quality standards Identify and mitigate design risks, ensuring robust circuit performance under process, voltage, and temperature (PVT) variations Stay updated on industry trends, emerging technologies, and best practices in HPC space Drive continuous improvement in design methodologies, tools, and workflows #J-18808-Ljbffr

A leading utility company in Santa Clara seeks an Electric Division Manager to oversee Transmission and Distribution operations. This role requires strong leadership skills, in-depth knowledge of compliance, and experience managing a team in a union environment. The ideal candidate will balance repair work with new construction and ensure adherence to safety regulations. A Bachelor's degree in Engineering or Business is essential. Competitive compensation and relocation assistance offered. #J-18808-Ljbffr

About Us We're building a co-pilot for hardware designers. Our mission is to enable millions of hardware designers and engineers to iterate through designs 1000x faster. We are building our geometry + physics driven foundation model for each class of part design. Our first model is shipped and we are expanding our capabilities! Backed by Khosla Ventures and Eclipse Ventures About You You've shipped AI products that operate in high-dimensional, multimodal domains - computer vision, geometry, or simulation-based workflows. You have experience building models that don't just analyze data, but generate complex, structured outputs under real-world constraints. You're comfortable navigating both classic modeling techniques and modern deep learning architectures, and you care about building systems that are principled, testable, and physically meaningful. What You'll Work On Design conditional generative models for 3D geometry tailored to hardware design workflows, including mesh-based, parametric (e.g., CAD) and implicit representations Develop models that generate geometry conditioned on constraints, partial designs, simulation outcomes, or functional requirements. Support inverse design tasks where the model proposes viable geometries given desired performance or physical behavior Implement cutting-edge generative architectures for 3D data such as: Diffusion models for point clouds, voxel grids, or triangle meshes Neural implicit representations (SDFs, DeepSDF, NeRF variants for shape modeling) Transformer or autoregressive models for topological and geometric sequence modeling CAD-aware generation pipelines (sketch-based or parametric component generators) Develop pipelines for geometry-aware learning and generation combining: Mesh and geometry processing (remeshing, simplification, subdivision) Differentiable simulation or physics-informed learning components Conditioning on design constraints, performance targets, or class-specific priors Collaborate with domain experts in physics, geometry, and simulation to: Integrate physical principles and simulation feedback into the generation loop Ensure designs meet functional, physical, and manufacturability requirements Translate domain knowledge into data priors, architectural biases, or constraints Design experiments and benchmarks to evaluate generation quality such as: Geometry fidelity and resolution Physical plausibility and constraint satisfaction Generalization to novel design tasks or unseen part types Build product-facing generative tools, including: Auto-complete or correction of partial designs LLM to CAD generation Proposal of high-quality geometry variants from a design prompt> Design-space exploration tools guided by downstream simulation outcomes Own projects end-to-end: rapidly prototype models, test ideas, gather feedback and contribute to production deployment in collaboration with cross-functional teams Qualifications 4+ years of experience developing and shipping products Strong background in deep learning, especially applied to 3D or spatial data. Hands-on experience with mesh generation, implicit surfaces, or neural fields (e.g., NeRF, SDF, DeepSDF, Occupancy Networks). Experience with the related technologies, libraries, and languages: Python, C++, PyTorch (3D)/TensorFlow/JAX; plus to have GPU programming Experience with diffusion models for 3D generation Startup experience is a strong advantage. Understanding of geometry representations (mesh, voxel, point cloud, NURBS, parametric surfaces). Familiarity with 3D geometry processing, including mesh handling, surface reconstruction, spatial data structures, and basic topology, to support effective 3D model manipulation and analysis #J-18808-Ljbffr

About Voltai Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits. About the Team Backed by Silicon Valley's top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents. About this Role You'll design, bring up, and validate the next generation of compute and storage platforms powering Voltai's AI-driven design engines. You'll work across board design, mechanical integration, and thermal systems to build efficient, scalable hardware optimized for simulation, training, and verification workloads. You might thrive if you have 5+ years of experience in Server or board-level design for high-speed computing Signal and power integrity analysis Thermal management, mechanical design, and system bring-up Post-silicon validation, instrumentation, and failure analysis #J-18808-Ljbffr

We are looking for a junior, motivated and talented problem solver. The ideal candidate will be responsible for testing and assembling electrical and mechanical components into devices. They will also help design and manufacture our product, organize the lab and work with suppliers as needed. They should be able to make quality assurance checks in order to keep the product standard high. Responsibilities Evaluate electrical products and systems by designing testing methods Organize lab Test finished products and system capabilities Keep necessary equipment operational Contribute to team efforts by accomplishing related results Qualifications Bachelor's degree in Electrical Engineering or related field Have knowledge of sensors, mechanical parts and electronic boards Can solder electrical components on PCB Strong problem solving, technical, math and science skills Strong written and verbal communication

Redwood Electric Group is looking for a detail-oriented and technically skilled Electrical PV Designer to support our project teams in the design and drafting of photovoltaic and energy storage systems. This role plays a critical part in ensuring the accuracy, efficiency, and code compliance of our electrical designs while collaborating closely with engineers, project managers, and construction teams. About us Redwood Electric Group is a large business providing electrical construction and design services. We operate throughout the Greater Bay Area with offices in Santa Clara, San Leandro, Vacaville, and Sacramento. At Redwood Electric Group, our philosophy is focused on the commitment to our customers. Their success is a direct reflection of our success. Our business continues to reflect strong growth through innovation and our team's commitment to exceed customer expectations. Duties/Responsibilities Develop electrical single-line diagrams for AC and DC PV systems. Design PV array layouts, considering site conditions, shading, and component options. Perform electrical calculations, including voltage drop, conductor sizing, and inverter loading. Select appropriate PV modules, inverters, combiners boxes, and other system components. Create detailed electrical drawings, including site plans, equipment layouts, and installation details. Ensure compliance with the California Electrical Code (CEC) and other relevant codes and standards. Utilize PV design and Autodesk software and to create accurate and efficient designs. Coordinate with structural engineers on mounting system design and integration. Collaborate with engineers, project managers, and construction teams to integrate electrical designs into overall project plans. Provide technical support during the installation and commissioning phases of PV projects. Stay up-to-date with the latest advancements in PV technology and industry best practices. Required Skills/Abilities Proficiency in AutoCAD, Helioscope, & PVsyst for electrical distribution and PV system layout. Familiarity with California Electrical Code and other relevant codes and standards. Strong problem-solving skills with an analytical approach to electrical system design. Knowledge of PV system components and distribution equipment. Ability to manage multiple projects and deadlines in a dynamic team environment. Effective verbal and written communication skills to collaborate across teams. Contribute to a team environment where your input is valued. Education and Experience Bachelor's degree in Electrical Engineering or a related field (preferred), or equivalent relevant experience. 1-2 years of experience of electrical design for a design-build electrical contractor or engineering firm. Proficiency in AutoCAD MEP. Revit is appreciated. Basic knowledge of Microsoft Office applications. Strong time management, communication, and interpersonal skills. FE (EIT certification) appreciated. LEED project experience appreciated. Working Conditions This position is based in our Santa Clara office and is not eligible for remote work. Work may be performed in an office or on active job sites, depending on role and project needs. Office work includes sitting, typing, and using a computer for extended periods. Field environments may involve walking, standing, bending, or lifting materials (up to 30 lbs). Noise levels range from quiet (office) to high (job sites). May require occasional travel to project locations or meetings. REG will provide reasonable accommodations as required by the ADA and applicable state law. Disclaimer The duties and responsibilities listed above are representative of the work typically performed in this role but are not intended to be a comprehensive list. Actual responsibilities may vary depending on department needs, project scope, or business requirements. Employees may be assigned additional tasks as needed to support company goals and operations.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. Make the choice to join us today.Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You will also be eligible for equity and .Applications for this job will be accepted at least until November 18, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts with the floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team to come up with an efficient clock programming sequence. The team works with the silicon solution team to triage silicon or programming bugs in the lab.**What you'll be doing:*** As a Clocks team member, you will be architecting the clock domain to satisfy functional, physical and testing design requirements.* Engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural/design/physical constraints.* Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.* Collaborate with Physical design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking.* Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams.* Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.**What we need to see:*** BS in Electrical Engineering or equivalent experience (MS preferred)* 3+ years of relevant work experience.* Deep understanding of logic optimization techniques and PPA trade-offs.* Excellent interpersonal skills and ability to collaborate with multiple teams.* Experience in RTL design (Verilog), verification and logic synthesis.* Strong coding skills in python or other industry-standard scripting languages.* Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.* Implementing on-chip clocking networks is a bonus**Ways to stand out from the crowd:*** Experience with clocks controller, clocks logic design* Understanding of system level artifacts like power, noise, etc* Experience with scalable designs and architecture.* Hands- on silicon debug is a plus.#LI-Hybrid #J-18808-Ljbffr

Santa Clara, California, United States Hardware Apple is building the world's fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy. Responsibilities Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore architecture trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem. Work on front-end netlist and area/timing analysis of the cache subsystem. Work with physical design team on the timing closure of the cache subsystem. Minimum Qualifications In-depth knowledge of memory subsystem Academic experience with RTL/micro-architecture development Good understanding of PPA (performance/power/area) tradeoffs B.S. in a relevant field + 0 years of industry experience Preferred Qualifications Cache design background including good understanding of different memory organizations and tradeoffs Experience with multi-processor cache coherence protocols Knowledge of high-performance coherent memory systems or interconnect architectures Knowledge of high-performance DRAM controller M.S in a relevant field. Compensation and Benefits At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $126,800 and $190,900, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . #J-18808-Ljbffr

We are seeking a Front-End SoC/ASIC Design Engineer for our SoC business unit. Responsibilities Support customer's design through all phases of ASIC execution at Socionext. Ensure designs meet product Performance-Power-Area-Schedule requirements. Tasks may include Architecture / micro-Architecture; Logic Design; RTL integration and coding; Lint/CDC/DFT checks; Synthesis & supporting timing‑closure; Contribute to and support Verification; Supporting Firmware and FPGA teams; Silicon bring‑up. Ensure deadlines for project milestones are met while maintaining quality. Work effectively with internal and external (including customer and vendors) teams (Note: Socionext has teams located globally). Display a results‑focused attitude and accomplish Company/Team‑goals. Qualifications Bachelor's Degree in EE or similar degree. 5+ years of professional design experience, provided the work experience is solid micro‑architecture and front‑end design. Hands‑on ASIC front‑end design, ideally in design services environments (product backgrounds acceptable). Skills Required - Micro‑architecture at module/sub‑system/chip‑level; digital design of complex modules/sub‑systems, with solid understanding of clock‑domain crossings; integration of IPs/modules/sub‑systems designed by internal/external teams; experience using AMBA bus protocols; System Verilog experience; Lint and CDC execution and analysis; writing timing constraints and timing analysis; excellent debug skills; customer support. Technical document writing skill Teamwork, dedication, collaborative, strong communications, and interpersonal skills. Ability to meet stringent deadlines and project timelines. Skills Strongly Desired - SoC Architecture experience. Experience and domain‑knowledge in at least 2‑3 of these: CPU (preferably, ARM and/or RISC‑V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low‑power design and verification; high‑speed peripheral interfaces such as CSI, HDMI/DP, I3C, USB, PCIe; Machine‑learning / AI; FPGA. Compensation: $180,000.00 - $200,000.00 per year #J-18808-Ljbffr

A leading quantum computing company in Palo Alto is looking for a Principal Hardware Design Engineer to oversee PCB layouts and hardware designs for its innovative quantum computer systems. The ideal candidate will have over 12 years of experience and strong skills in circuit design, problem-solving, and communication. This position offers a competitive salary, ranging from $230,000 to $250,000 base pay, and the opportunity to work in a cutting-edge field. #J-18808-Ljbffr

At Array Labs, we are building the world's most advanced satellite radar constellation to create a high-resolution 3D digital twin of the Earth. Our mission is to provide "lidar-like" 3D data and imagery from space, serving critical applications for both commercial and defense customers. This is a deep tech challenge in the truest sense. We're solving complex problems that span hardware, software, and data-from designing satellite systems for the harshness of space to building the massive "data factory" that turns raw sensor data into beautiful 3D products. We are looking for first-principles engineers who want to build, deploy, and scale a one-of-a-kind, vertically-integrated system from the ground up. The hardware engineering team is responsible for the analysis and design of our satellite and ground-station electronics, which spans the range of radar, communications, power management and processing subsystems. As a lead engineer, you will own the design of hardware solutions that will be integrated into satellites and cutting-edge ground infrastructure. You will work cross-functionally with our antenna, RF, communications and radar engineers to rapidly move from clean-sheet designs to full operational deployment in space. In this role, you'll help shape the design of the world's first formation-flying radar imaging constellation, which will deliver a quantum-leap in humanity's ability to rapidly and comprehensively understand our ever-changing world. Responsibilities Develop advanced electronic platforms, from architecture to manufacturing Work closely with software, firmware, RF, antenna, digital, and mechanical design engineers to design and validate state-of-the-art spacecraft electronics Create requirements, perform system trades, select components, capture schematics, design complex electronic assemblies and manage manufacturing Lead prototyping, hardware bring-up, debug, manufacturing, and test campaigns. Rapidly iterate on and improve electronic designs based on laboratory, environmental and on-orbit testing Basic Qualifications B.S. in Electrical Engineering, or a related field. Experience in electronics design, fabrication, and test Excellent teamwork and communication skills Learns new concepts rapidly, completely, and in a self-directed manner High levels of self-motivation and personal accountability Ability to work in a fast-paced environment under significant time constraints Preferred Skills and Experience Bachelor's or Master's degree in electrical engineering, or a related field 4+ years of proven electrical engineering work experience with full-life cycle development (concept to production) of consumer electronics, power electronics, communications, automotive, aerospace, and/or robotics Solid background in high-speed board design, simulation, and validation techniques including PCB stack-up, PCB fabrication, floorplanning, component selection, placement and routing, simulation and measurement Solid background in electromagnetic theory and RF fundamentals such as s-parameters, transmission lines, and broadband impedance matching Hands-on experience designing high-performance platforms including compute (SoCs, FPGAs, MCUs),storage (DDR, SSDs),high-speed interfaces (PCIe, SPI, JESD204B),RF components (PAs, LNAs, switches) Proficiency with schematic capture and layout using CAD tools such as Altium Designer, Allegro, and ORCAD Experience with EMC requirements and EMI mitigation techniques Expertise in signal and power integrity simulation and measurement Expertise in EM and thermal simulation of printed circuit boards Experience with analysis and simulation tools such as LTSPICE, ADS and Microwave Office Experience with data analysis and programming in MATLAB or python Hands-on experience with test equipment such as oscilloscopes and network analyzers ITAR Requirements To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Equal Opportunity Employer Array Labs is an Equal Opportunity Employer. Employment decisions are made on the basis of merit, competence, and job qualifications and will not be influenced in any manner by gender, color, race, ethnicity, national origin, sexual orientation, religion, age, gender identity, veteran status, disability status, marital status, mental or physical disability or any other legally protected status. $U150,000 - $U300,000 a year Interview Process We will conduct three interviews via Zoom; the typical process takes around 2-4 weeks to complete from start to finish. Hiring and Compensation Strategy Our hiring and compensation strategy is simple: 1) find uncommonly good people 2) pay them uncommonly well You can anticipate competitive pay, with high flexibility between salary and equity-based compensation. Why you should join Array Labs Array Labs is launching a constellation of satellites to create the first high-resolution, real-time, three-dimensional model of Earth. Our next-generation satellite technology will offer image quality 60x greater than traditional techniques, profoundly expanding humanity's ability to understand and respond to events on a global scale. In forging an affordable, accessible, accurate representation of Earth, our work has the potential to transform the face of dozens of fields, including autonomy, telecommunications, disaster relief, gaming, climate science, defense and construction. #J-18808-Ljbffr

We are looking for a junior, motivated and talented problem solver. The ideal candidate will be responsible for testing and assembling electrical and mechanical components into devices. They will also help design and manufacture our product, organize the lab and work with suppliers as needed. They should be able to make quality assurance checks in order to keep the product standard high. Responsibilities Evaluate electrical products and systems by designing testing methods Organize lab Test finished products and system capabilities Keep necessary equipment operational Contribute to team efforts by accomplishing related results Qualifications Bachelor's degree in Electrical Engineering or related field Have knowledge of sensors, mechanical parts and electronic boards Can solder electrical components on PCB Strong problem solving, technical, math and science skills Strong written and verbal communication

A leading technology company in California is seeking an ASIC Design Engineer. The role focuses on implementing and delivering high-performance RTL designs, collaborating with various teams to analyze architectural trade-offs. Candidates should have a Bachelor's degree in Electrical Engineering or equivalent, with experience in micro-architecture and RTL development. The company offers a diverse work environment and a competitive salary range, as well as equity opportunities. #J-18808-Ljbffr

Milpitas, CA Benefits 401(k) 401(k) matching Responsibilities Ensure designs meet product Performance‑Power‑Area‑Schedule requirements. Tasks may include Architecture / micro‑Architecture; Logic Design; RTL integration and coding; Lint/CDC/DFT checks; Synthesis & supporting timing‑closure; Contribute to and support Verification; Supporting Firmware and FPGA teams; Silicon bring‑up. Ensure deadlines for project milestones are met while maintaining quality. Work effectively with internal and external (including customer and vendors) teams. Display a results‑focused attitude and accomplish Company/Team‑goals. Qualifications Bachelor's Degree in EE or similar degree. 5+ years of professional design experience, provided the work experience is solid micro‑architecture and front‑end design. Hands‑on ASIC front‑end design, ideally in design services environments (product backgrounds acceptable). Micro‑architecture at module/sub‑system/chip‑level; digital design of complex modules/sub‑systems, with solid understanding of clock‑domain crossings; integration of IPs/modules/sub‑systems designed by internal/external teams; experience using AMBA bus protocols; System Verilog experience; Lint and CDC execution and analysis; writing timing constraints and timing analysis; excellent debug skills; customer support. Technical document writing skill. Teamwork, dedication, collaborative, strong communications, and interpersonal skills. Ability to meet stringent deadlines and project timelines. SoC Architecture experience. Experience and domain‑knowledge in at least 2‑3 of these: CPU (preferably, ARM and/or RISC‑V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low‑power design and verification; high‑speed peripheral interfaces such as CSI, HDMI/DP, I3C, USB, PCIe; Machine‑learning / AI; FPGA. #J-18808-Ljbffr