Electrical engineer internship jobs in Santee, CA - 281 jobs

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. Must be a U.S. citizen and eligible to receive a U.S. Government security clearance We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands‑on experience in RTL‑to‑GDSII flow, with a strong focus on Floor‑planning, Clock Tree Synthesis, Place‑n‑Route (PnR), DRC and Timing closure. This role involves architecting and implementing robust, low‑skew, power‑efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals. This role requires full‑time onsite work in San Diego, CA (5 days per week). Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Key Responsibilities: Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry‑standard tools (e.g., Innovus, ICC2). Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing, congestion, and DRC issues. Optimize design for power, performance, and area (PPA). Conduct formal equivalence checks between RTL and netlist. Support physical verification including DRC, LVS, and antenna checks. Work closely with backend teams for tapeout preparation and signoff. Excellent scripting skills (TCL, Python, Perl) for reference flow automation. Execute full‑chip and block‑level physical verification including DRC, LVS, ERC, antenna, and density checks using industry‑standard tools (e.g., Calibre, Pegasus, ICV). Customize and optimize reference physical verification flows to align with project needs and foundry requirements. Perform GDS‑to‑GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness. Debug and resolve physical verification violations, working closely with layout, design, and CAD teams. Collaborate with foundries to ensure compliance with latest design rule manuals (DRMs) and tapeout checklists. Support signoff verification, including multi‑corner/multi‑mode analysis and ECO validation. Develop and maintain automation scripts for verification flows, reporting, and regression testing. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability. Ensure timely delivery of clean GDSII for tapeout, with full verification signoff. Perform full‑chip and block‑level static timing analysis (STA) using industry‑standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners. Collaborate with RTL, synthesis, and physical design teams to ensure timing‑aware design practices. Debug and resolve setup, hold, and transition violations across various PVT corners. Drive timing closure through iterative optimization and ECO implementation. Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability. Analyze clock tree timing, including skew, latency, and jitter impacts. Support signoff timing verification, including cross‑domain timing and false/multicycle path handling. Define and implement low‑power architecture using CLP methodology across RTL and physical design stages. Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications. Customize and optimize low‑power reference flows to meet project‑specific requirements. Collaborate with RTL, synthesis, and physical design teams to integrate power‑aware features such as power gating, retention, isolation, and level shifting. Perform power‑aware static checks, simulation, and formal verification to validate power intent. Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing. Support signoff verification including power‑aware LVS/DRC, STA, and EM/IR analysis. Ensure compliance with foundry low‑power guidelines and contribute to successful tapeout. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 4+ years of experience in physical design, with a focus on clock tree design and implementation. Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design. Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime). Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies. Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis. Familiarity with low‑power design techniques, including clock gating and multi‑voltage domains. Preferred Skills: Experience with custom clock tree architectures such as H‑tree, mesh, or spine‑based topologies. Knowledge of EM/IR analysis, thermal‑aware clocking, and reliability modeling. Exposure to high‑speed interface clocking (e.g., SerDes, DDR, PCIe). Understanding of package‑level clock planning and signal integrity. Principal Duties & Responsibilities: Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system‑level requirements. Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of complex process flow from high‑level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages. Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects. Level of Responsibility: • Works independently with minimal supervision. • Provides supervision/guidance to other team members. • Decision‑making is significant in nature and affects work beyond immediate work group. • Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. • Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). • Tasks do not have defined steps; planning, problem‑solving, and prioritization must occur to complete the tasks effectively. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑************************** or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Job Description: Electrical Engineer (Multiple Levels: Electrical Designer | Electrical Engineer | Senior Electrical Engineer) We are seeking skilled and motivated Electrical professionals across multiple experience levels to join our team in the building industry. This opportunity is open to candidates ranging from Electrical Designers to experienced and Senior Electrical Engineers specializing in building systems. The ideal candidate will possess expertise in electrical engineering principles with a focus on building systems and a strong understanding of how electrical systems integrate with multidisciplinary MEP designs. A solid working knowledge of California regulations, including the California Building Code and California Electrical Code, is essential for engineering-level roles. Proficiency in utilizing Revit and BIM (Building Information Modeling) software is a key component of this position. Responsibilities and level of responsibility will be aligned with the candidate's experience, skill set, and licensure. Responsibilities: Design and Planning: Assist with or lead the development of electrical design concepts, specifications, and calculations for various building types, including multifamily, commercial, retail, industrial, and life science projects, in accordance with applicable codes and standards. Create electrical layouts, schematic diagrams, single-line diagrams, and system drawings for power distribution, lighting, and low-voltage systems. Collaborate with architects, engineers, and project stakeholders to ensure coordinated and integrated electrical system designs. Support continuous improvement of electrical design efficiency, sustainability, and cost-effectiveness while maintaining safety and compliance.. System Analysis: Perform or support load calculations, voltage drop analysis, short-circuit calculations, lighting calculations, and coordination studies, as appropriate to experience level. Assist with evaluating energy-efficient technologies and sustainable design strategies for electrical systems. Technical Documentation: Prepare detailed electrical drawings, plans, and specifications for construction documentation using AutoCAD and Revit/BIM. Generate technical reports, project documentation, and compliance materials as required by project and regulatory standards. Project Management & Coordination: Support or lead coordination of electrical designs with mechanical, plumbing, architectural, and structural disciplines. Participate in project meetings and internal design reviews. Review and coordinate electrical drawings prior to transmittal to ensure completeness and accuracy. Assist with project scheduling, budgeting, and resource planning related to electrical tasks. Quality Assurance: Conduct reviews to ensure electrical designs comply with applicable codes, standards, and project requirements. Collaborate with internal quality assurance processes to verify performance and safety of electrical installations. Client Engagement (Mid- to Senior-Level): Communicate effectively with clients and project teams regarding electrical design questions. Support responses to RFIs, submittals, and design clarifications as needed. Professional Development: Stay current with industry trends, electrical codes, and emerging technologies. Identify opportunities for innovation and improvements in electrical system design. Requirements: Electrical Designer / Junior Level: Bachelor's degree in Electrical Engineering, Electrical Design, or a related field preferred, or equivalent professional experience. Proficiency in AutoCAD; Revit experience preferred. Basic understanding of electrical building systems and construction documentation. Strong attention to detail and ability to work collaboratively. Electrical Engineer: Bachelor's degree in Electrical Engineering or a related field. Experience in electrical design for building systems. Working knowledge of the California Building Code and California Electrical Code. Proficiency in AutoCAD and Revit/BIM. Strong analytical, organizational, and problem-solving skills. Senior Electrical Engineer: Extensive experience in electrical engineering within the building industry. Strong knowledge of California codes and jurisdictional requirements. Ability to lead projects, coordinate across disciplines, and mentor junior staff. Professional Engineering (PE) licensure in California preferred but not required. Familiarity with sustainable design practices and energy efficiency is a plus. Compensation & Benefits: The compensation range is dependent on the facts and circumstances of each case. The factors considered in making compensation decisions include skill sets, experience and training, licensure and certifications, and other business and organizational needs. We offer a competitive benefits package including: A competitive salary. Medical coverage reimbursement Personal time off (PTO) Paid company holiday. Flexibility with work schedule. Employee Assistance Program If you are a Electrical professional with a passion for building systems and a desire to grow within an MEP engineering firm, we invite you to apply and join the 120 Degreez team. Other Information: 120 Degreez is an equal opportunity employer that is committed to diversity and inclusion in the workplace. We prohibit discrimination and harassment of any kind based on race, color, sex, religion, sexual orientation, national origin, disability, genetic information, pregnancy, or any other protected characteristic as outlined by federal, state, or local laws.

Stantec's Buildings team is on a mission to become the world's leading integrated design practice. Our architects, engineers, interior designers, consultants, sustainability specialists, and technologists are passionate about the power of design. Our collaborative culture and our innovative, sustainable approach to projects help us create buildings that matter to our world. Together, we are enhancing the quality of life globally through design. Join us and design your place with Stantec. Your Opportunity As a Principal, Electrical Engineering, one must bring deep knowledge and thought leadership that is client-facing, strategic and transparent, and of technical excellence. A focus on experience and relationships in the A/E/C industry to contribute to the overall strategic and tactical leadership of the Stantec Buildings engineering team and leading the electrical engineering practice in the San Diego Area. This position is client-facing requiring leadership in strategic projects, while advancing the overall engineering practice as well as team growth and development. In addition, business development, contributions to project delivery standards and work processes, quality control, workload forecasting, financial performance accountability and collaboration with other disciplines is critical. The principal contributes to differentiating Stantec from other competing firms and thereby positions Stantec as innovators in the industry. Your Key Responsibilities Business Development/Strategy - approximately 25% of time Be a primary contributor to building Stantec's Sector Engineering practice in the San Diego Area. Be a Principal leader within the San Diego office. Partner with the other Principal leaders in the office to help develop and sustain strategic growth objectives and tactical plans to ensure the continued growth trajectory of the office and integrated practice. Interface regularly with additional architectural, mechanical engineering and electrical engineering leaders in US West and across North America to thrive and contribute within the integrated design practice Develop and execute strategic and tactical business and marketing plans for the engineering practice in San Diego that aligns with Business Center, Regional and National practice goals to advance the overall Buildings practice. Sustain and grow top line revenue helping to achieve growth objectives in the San Diego/Southern California and US West areas in collaboration with the Regional Business Leader, Business Center Practice Leaders, and Engineering leaders in US West to achieve key operational performance metrics. Develop and maintain industry relationships and visibility with current and prospective clients, sub-consultants, and partner firms in the local and regional A/E industry. Assist with the development of the annual business plan and budget for the business center and working with the leadership team to achieve key performance indicators. Develop presentation materials and present to clients and at strategic industry events. Represent the firm through published articles, public speaking engagements and attendance at industry and community events, meetings, and conferences. Develop project proposals. Assist the marketing department with the development of health sector engineering marketing materials and content. People and Practice Management - approximately 20% of time Hire, develop, grow and lead a team consisting of engineering project managers, engineer's designers, and production team members. In conjunction with other stakeholders, identify and forecast staff needs and assignments based on current and projected workload and SME requirements. Hold project team members accountable for technical excellence, delivery standards, and best practices. Responsible for managing the financial performance, quality control processes, and project delivery for Electrical Engineering projects. Ensure compliance with best practices, including Stantec PM Frameworks Project Involvement. Project Design and Delivery - approximately 40% of time Work with PM's and SMEs on key projects to develop and deliver client drawings, specifications, presentations, reports, and other deliverables. Successfully manage projects of significant scope, complexity, and revenue budget. Apply buildings engineering and project management knowledge while leading cross-functional resources to meet project requirements within established timeframes and budgets. Meet technical, contractual, schedule, budgetary and client service objectives for projects. Apply strong engineering skills, experience and knowledge to the design and oversight of the design for building projects. Manage and plan the production resources and workflow to produce the design documentation, drawings, and calculations required for engineering projects. Act as a QC and/or Independent Technical reviewer on Electrical Engineering projects. Technical Leadership - approximately 15% of time Maintain awareness of operational, technical, or regulatory changes within Electrical Engineering and AEC industry overall, disseminate such knowledge to team and firm, and integrate into existing processes and standards. Assist to maintain and update Health Sector Engineering specifications, technical documentation, and standards in collaboration with other technical resources within Stantec. Oversee Electrical Engineering Design delivery process and best practices and coordinate with other disciplines. Provide oversight for Electrical Engineering continuing education and development, including staff education and certification process & balance firm, studio and staff needs. Learning/Maintaining and Expanding Technical and Managerial Skills: Maintain current knowledge of technologies and trends impacting Stantec's core service offerings and markets and continually strengthens skills. Your Capabilities and Credentials Outstanding client service skills with ability to lead practice members in consistently delivering an exceptional standard of service to every client. Strong managerial skills with ability to hire, engage, develop, and retain top-tier talent. Strong business acumen with ability to identify, develop and map strategy, prepare, interpret, and manage budgets, and analyze business results. Business development skills with ability to identify and develop prospects, nurture key relationships, cross-sell services, negotiate, and engage business. Comprehensive understanding of building project components, project management and delivery systems; ability to continuously evaluate and refine processes to increase efficiency and client satisfaction. Ability to manage clients, projects, fee, scope, and teams to achieve budget, schedule and deliverable objectives while meeting key stakeholder critical success factors. Familiarity with, and ability to produce, project-related documents and documentation standards required of a Project Manager. Ability to integrate design elements with other disciplines to deliver a coordinated design. Strong knowledge of applicable codes and standards. A commanding knowledge of technical issues supporting delivered design services. Strong technical understanding and working knowledge of buildings systems for the following core markets: Healthcare, Higher Education, Science and Technology, Mission Critical Facilities, Commercial/Workspace. Strong knowledge of the Health Sector market is preferred. Deep understanding of and ability to apply sustainable design principles within projects. Outstanding consulting skills with ability to present a credible, engaging image in keeping with Stantec's high service standards. Excellent verbal and written communication skills and polished presentation and public speaking skills. Fundamental understanding of NFPA 70, 72, 99 101,110 and/or FGI Guidelines as they specifically apply to hospitals, ambulatory surgical centers, and medical office buildings. Deep knowledge preferred for fire alarm and detection systems as well as healthcare technology systems such as nurse call communications, synchronized clocks, and voice/data/video infrastructure systems. Experience to identify and manage items of risk that may occur on projects. Ability to identify and manage potential unanticipated scope. Passion to integrate design elements with other disciplines to deliver a coordinated design. Dedication to apply sustainable design principles within projects while maintaining the process driven requirements of the markets we focus on facilities. Successful history of collaboration with contractors in various alternative construction delivery processes such as Design assist, Design-Build, and IPD Possess a valid driver's license with a good driving record Education and Experience Bachelor's degree in engineering 15+ years related professional experience Professional Engineering license Project Management Professional certification a plus LEED AP Credential preferred Typical office environment working with computers and remaining sedentary for long periods of time. Field work may include exposure to the elements including inclement weather. This description is not a comprehensive listing of activities, duties or responsibilities that may be required of the employee and other duties, responsibilities and activities may be assigned or may be changed at any time with or without notice This description is not a comprehensive listing of activities, duties or responsibilities that may be required of the employee and other duties, responsibilities and activities may be assigned or may be changed at any time with or without notice. Stantec is a place where the best and brightest come to build on each other's talents, do exciting work, and make an impact on the world around us. Join us and redefine your personal best. About Stantec Stantec is a global leader in sustainable engineering, architecture, and environmental consulting. The diverse perspectives of our partners and interested parties drive us to think beyond what's previously been done on critical issues like climate change, digital transformation, and future-proofing our cities and infrastructure. We innovate at the intersection of community, creativity, and client relationships to advance communities everywhere, so that together we can redefine what's possible. Pay Range: • Locations in CO, HI, MD & Various CA, NJ Areas - Min Salary $ 137,300.00 - Max Salary $ 205,900.00 Pay Transparency: In compliance with pay transparency laws, pay ranges are provided for positions in locations where required. Please note, the final agreed upon compensation is based on individual education, qualifications, experience, and work location. At Stantec certain roles are bonus eligible. Benefits Summary: Regular full-time and part-time employees (working at least 20 hours per week) have access to medical, dental, and vision plans, a wellness program, health saving accounts, flexible spending accounts, 401(k) plan, employee stock purchase program, life and accidental death & dismemberment (AD&D) insurance, short-term/long-term disability plans, emergency travel benefits, tuition reimbursement, professional membership fee coverage and paid family leave. Regular full-time and part-time employees will receive ten paid holidays in each calendar year. In addition, employees will be eligible to accrue vacation between 10 and 20 days per year and eligible for paid sick leave (and if more generous, in accordance with state and local law). Temporary/casual employees have access to 401(k) plans, employee stock purchase program, and paid leave, in accordance with state and local law. The benefits information listed above may not apply to union positions because benefits for such positions are governed by applicable collective bargaining agreements Primary Location: United States | CA | San Diego Organization: BC-2045 Buildings-US California Engineering Employee Status: Regular Travel: Yes Schedule: Full time Job Posting: 16/06/2025 10:06:36 Req ID: REQ250000HO Stantec provides equal employment opportunities to all qualified employees and applicants for future and current employment and prohibit discrimination on the grounds of race, colour, religion, sex, national origin, age, marital status, genetic information, disability, sexual orientation, gender identity or gender expression. We prohibit discrimination in decisions concerning recruitment, hiring, referral, promotion, compensation, fringe benefits, job training, terminations or any other condition of employment. Stantec is in compliance with laws and regulations and ensures equitable opportunities in all aspects of employment. At Stantec we are committed to ensuring our recruitment process is accessible to all. If you require reasonable adjustments to be made during the recruitment process then please inform a member of our Talent Acquisition team. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. Must be a U.S. citizen and eligible to receive a U.S. Government security clearance We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands‑on experience in RTL‑to‑GDSII flow, with a strong focus on Floor‑planning, Clock Tree Synthesis, Place‑n‑Route (PnR), DRC and Timing closure. This role involves architecting and implementing robust, low‑skew, power‑efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals. This role requires full‑time onsite work in San Diego, CA (5 days per week). Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Key Responsibilities: Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry‑standard tools (e.g., Innovus, ICC2). Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing, congestion, and DRC issues. Optimize design for power, performance, and area (PPA). Conduct formal equivalence checks between RTL and netlist. Support physical verification including DRC, LVS, and antenna checks. Work closely with backend teams for tapeout preparation and signoff. Excellent scripting skills (TCL, Python, Perl) for reference flow automation. Execute full‑chip and block‑level physical verification including DRC, LVS, ERC, antenna, and density checks using industry‑standard tools (e.g., Calibre, Pegasus, ICV). Customize and optimize reference physical verification flows to align with project needs and foundry requirements. Perform GDS‑to‑GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness. Debug and resolve physical verification violations, working closely with layout, design, and CAD teams. Collaborate with foundries to ensure compliance with latest design rule manuals (DRMs) and tapeout checklists. Support signoff verification, including multi‑corner/multi‑mode analysis and ECO validation. Develop and maintain automation scripts for verification flows, reporting, and regression testing. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability. Ensure timely delivery of clean GDSII for tapeout, with full verification signoff. Perform full‑chip and block‑level static timing analysis (STA) using industry‑standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners. Collaborate with RTL, synthesis, and physical design teams to ensure timing‑aware design practices. Debug and resolve setup, hold, and transition violations across various PVT corners. Drive timing closure through iterative optimization and ECO implementation. Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability. Analyze clock tree timing, including skew, latency, and jitter impacts. Support signoff timing verification, including cross‑domain timing and false/multicycle path handling. Define and implement low‑power architecture using CLP methodology across RTL and physical design stages. Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications. Customize and optimize low‑power reference flows to meet project‑specific requirements. Collaborate with RTL, synthesis, and physical design teams to integrate power‑aware features such as power gating, retention, isolation, and level shifting. Perform power‑aware static checks, simulation, and formal verification to validate power intent. Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing. Support signoff verification including power‑aware LVS/DRC, STA, and EM/IR analysis. Ensure compliance with foundry low‑power guidelines and contribute to successful tapeout. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 4+ years of experience in physical design, with a focus on clock tree design and implementation. Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design. Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime). Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies. Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis. Familiarity with low‑power design techniques, including clock gating and multi‑voltage domains. Preferred Skills: Experience with custom clock tree architectures such as H‑tree, mesh, or spine‑based topologies. Knowledge of EM/IR analysis, thermal‑aware clocking, and reliability modeling. Exposure to high‑speed interface clocking (e.g., SerDes, DDR, PCIe). Understanding of package‑level clock planning and signal integrity. Principal Duties & Responsibilities: Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system‑level requirements. Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of complex process flow from high‑level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages. Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects. Level of Responsibility: • Works independently with minimal supervision. • Provides supervision/guidance to other team members. • Decision‑making is significant in nature and affects work beyond immediate work group. • Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. • Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). • Tasks do not have defined steps; planning, problem‑solving, and prioritization must occur to complete the tasks effectively. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑************************** or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Substation Electrical Designer job at E2 Consulting Engineers, Inc.. San Diego, CA. Substation Electrical Designer Location Hybrid work in San Diego, CA. About the Organization: E2 Consulting Engineers, Inc. (E2) is a professional services firm established in 1988 specializing in a full spectrum of engineering services including, project engineering and design, federal base operations and infrastructure support services, gas pipeline construction and inspection services, environmental consulting and remediation, and information technology services. At E2, we value safety, innovation and collaboration, and we are dedicated to excellence. Overview: Responsible for the design of deliverables associated with a substation design project supporting different electric utility clients. These deliverables include one-line & three-line diagrams, AC & DC elementary & logic diagrams, front & rear panel elevations and wiring, supervisory & control drawings, electrical vendor equipment wiring diagrams, complete cable schedule and bill of materials as well as electrical physical deliverables such as general arrangement drawings, electrical equipment plan & elevation drawings, above & below grade conduit & grounding drawings, relay house layout and complete bill of materials. The position will work under the direction of a senior engineer and will report directly to the Substation Engineering Manager or Lead Engineer. Responsibilities Perform substation electrical design activities including drawings, specifications, bill of materials, and cable schedules. Perform careful self-checking activities to ensure the quality of work before it is presented to senior design reviewers. Prepare computer assisted design and construction drawings of a complex nature with neatness and a minimum of errors. Ensure all designs conform to our client's and industry standards. Communicate and coordinate project activities with senior engineer and/or project manager. Utilize client and/or company information system to track and update design activities. Assist senior engineers during job site meetings to gather scope of work. Assist senior engineers in answering Request for Information (RFI) during project construction. Perform other duties as assigned. Qualifications Associate degree in engineering technology or equivalent substation experience. 5-8 years of experience working in substation design or similar with utility or consulting engineering firm. Proficient using Microsoft Office suite (e.g., Excel, Word, and Outlook). Strong analytical, problem-solving skills, and attention to detail. Experience with AutoCAD and/or MicroStation. Basic written and verbal communication skills. Preferred Experience with substation design and construction standards for Southern California Edison or SDG&E. Benefits E2 Consulting Engineers, Inc. offers an excellent benefits package including health, dental, vision, and life insurance, 401(k) with employer match, paid time off. Wage Data Per State Requirements: Salary range for this position is $65,000 - $110,000. The starting salary will be commensurate with skill, education, experience, and working environment. Work Environment This job operates in a professional office environment and uses standard office equipment such as computers and phones. Physical Demands The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions. Ability to sit/stand for up to 8 hours per day. Ability to move freely for up to 8 hours per day. Drug Free Workplace E2 Consulting Engineers, Inc. is a Drug Free Workplace. After accepting an offer of employment, applicants may be required to undergo background checks, drug testing, and/or fit-for-duty physical examination. Drug screens will include, but not be limited to, Amphetamines, Cocaine Metabolites, Marijuana Metabolites (THC), Opiates, and Phencyclidine (PCP). As a federal contractor, E2 cannot permit employees in certain positions to use medical marijuana, even if prescribed by an authorized physician. Solicitation Please no solicitation of any kind from agencies, staffing, or recruiting firms. EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. #J-18808-Ljbffr

Job Description: Candidate will be responsible for testing physical/MAC layers, protocol layers, and data applications implemented on various company Modem products, handsets and data cards. Candidate will work directly with Engineers in performing daily testing tasks and reporting test results. Must be able to follow directions, perform consistent and thorough testing, and provide accurate test status and reports. The effort will involve multimode operations of handset devices, gaining knowledge in the following technology areas: CDMA2000, 1xEV-DO, WCDMAGSM/GPRS, LTE Training will be provided to allow the employee to perform their job function. The position will require travel in North America, 75% of the time and an opportunity to relocate to critical markets for longer durations. Some overtime work may be required. Successful candidate must have strong communication skills, must be an effective team player and be able to work independently Min Qualifications Exposure to commercial field test and data analysis tools for wireless telephony product verification Handset test experience with UMTS/CDMA operators or with commercial handset OEMs Experience using QC tools like QXDM, QCAT, CAIT, etc. is very useful. Exposure in one or more of following areas: oUnderstanding of digital communications systems, RF propagation, CDMA, OFDM, telecommunications concepts oUnderstanding of Physical/MAC layers and Call Processing concepts in one or more of the following air interface standards CDMA2000, 1xEV-DO (Rev 0/A/B), GSM/ GPRS /EDGE / Rel99/ Rel5 / HSDPA/ HSUPA/HSPA+, LTE oUnderstanding of wire line and wireless data protocol stacks including RLP, PPP, IP, TCP, IPV6, MIPV6, etc. Understanding of software development and testing concepts for wireless handsets for various air interface standards ,Familiarity with IP telephony network , SIP, IMS, and IP telephony standards Pref Qualifications: Familiarity with air interface performance analysis, characterization and optimization oExposure to programming in C, Perl, shell scripting is a plus Comments for Suppliers: 0-4yrs exp onsite critical - San Diego

9 months + San Diego, CA -100% onsite Must Have Experience in Handset testing commercial OEM or Field / Lab Environment across 5G/4G/3G operators Experience in drive testing in field on-site and ability to debug / troubleshoot /analyzing basic device / OTA issues (camping, provisioning) between device and network Experience in testing, debugging and familiarity with Android OS Excellent written and verbal communication skills Has valid US Drivers License Nice To Have JOB DESCRIPTION Required Education: Bachelors Degree in Engineering or Electrical Engineering with 2 years work experience OR Masters Degree in Engineering or Electrical Engineering Required Skills: Experience in Handset testing commercial OEM / Lab Environment across 5G/4G/3G operators Experience in drive testing in field on-site and ability to debug / troubleshoot /analyzing basic device / OTA issues (camping, provisioning) between device and network Experience in testing, debugging and familiarity with Android OS Excellent written and verbal communication skills Has valid US Drivers License Experience using QC tools like QXDM, QCAT, PCAT etc Understanding of software development and testing concepts for wireless handset for various air interface standards - 5G (SA, NSA, mmW, NRDC), LTE Need to be in field for 8 hrs with Van/drive test as part of Field Engineer Position Preferred Skills/Education: Experience with Stability Testing Experience with air interface performance analysis, characterization and optimization Experience with test planning / test case development Understanding of Physical/MAC layers and Call Processing concepts Exposure to programming in C, Perl, Shell Scripting is a plus Apolis2024

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work - and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. Northrop Grumman Aeronautics Systems is looking for an experienced Electrical Test Engineer to support the Circuit Design organization in Rancho Bernardo, San Diego, CA. In this role, you will lead production line troubleshooting for various Circuit Card Assemblies (CCA). You'll work closely with design engineers to troubleshoot hardware and verify test software on schedule and that meets all requirements. In addition, one will have the opportunity and responsibility to support qualification testing, preparing test procedures and reports, and supporting hardware production manufacturing. Responsibilities Include: * Provide support in person and through documentation generation of findings and implemented solutions. * Good communication, computer, documentation, presentation, and interpersonal skills are required, as well as the ability to work both independently and as part of a team. * Understand new concepts quickly and apply them accurately throughout an evolving environment and organize work assignments to meet established timetables. * Debug, troubleshoot and verify test stations * Applies technical knowledge to analyze, investigate and resolve production line faults during acceptance testing * Performs functional testing and troubleshooting of equipment and systems utilizing standard engineering and scientific principles Basic Qualifications: * Must have a Bachelor's degree in Electrical Engineering, with at least 5 years of related professional / military engineering experience or a Master's degree with at least 3 years of related professional / military engineering experience * Must have previous experience with electronic schematics * Must have previous experience with automate testing for Printed Wiring Assemblies (PWA) and Weapon Replaceable Assemblies (WRA) Preferred Qualifications: * Bachelors' degree in Electrical Engineering, 9 years of engineering experience or 7 years of electronics design experience with a Master's degree * Experience with LabVIEW and TestStand work preferably on production test applications * Advanced degree in Electrical Engineering with a focus on mixed circuit design * Experience with automated test equipment Primary Level Salary Range: $114,000.00 - $171,000.00 The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions. Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business. The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates. Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit *********************************** U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.

Introduction ASML is one of the world's leading manufacturers of lithography systems that help enable Moore's Law and the creation of increasingly powerful and capable electronic devices. Our San Diego-based light source division, Cymer, is renowned for developing both deep ultraviolet (DUV) lithography light sources and next generation extreme ultraviolet (EUV) light sources. As the world's leading semiconductor equipment manufacturer, ASML enables chipmakers to produce cheaper, speedier chips - and to produce them faster - thereby enabling all the technology you use today. The systems we produce integrate several large and sophisticated machines, themselves each a feat of engineering innovation, precision, and speed. We are a multinational company with over 70 locations in 16 countries, headquartered in Veldhoven, the Netherlands. We have 18 office locations around the United States including main offices in Wilton, CT, Chandler, AZ, San Jose, CA and San Diego, CA (DUV laser and EUV light source creation). We are currently recruiting for internships located at our office in San Diego, CA. In the Cymer Light Source (CLS) division in San Diego, we design and manufacture Deep Ultraviolet (DUV) lasers, used directly in the chipmaking process. Far from a basic “consumer” laser, these machines are complex, powerful, and flexible. The lasers we make require: durable and high-speed precise motion-controlled optics to maintain wavelength to femtometer accuracy under high laser powers; advanced materials to endure the harsh Fluorine-rich environments and high powers; clever mechanical designs to allow high performance and fit all the parts within a confined space, but still allow easy manufacturing and servicing; very fast high power electronics and electrical designs to deliver short high voltage pulses at precise timing to control pulse energy within hundredths of a percent; gas flows at hurricane speeds to keep the laser discharge area clear; cutting edge controllers and algorithms to deliver stable and consistent performance and automate all operations; and advanced real-time electronics, firmware and software to control the laser and interact with other equipment. The laser needs to minimize use of expensive or rare resources like energy or Neon gas. It needs to actively control temperatures, pressures, gas concentrations, timing and voltages precisely to maintain good performance. It must react instantly to changing customer demands and environmental conditions. And it needs to do all of this, operating continuously and reliably for months while producing billions of perfect light pulses, without any human intervention or downtime. If you have a passion for technology and innovation you'll want to check us out. Be a part of Cymer / ASML. Be a part of progress. One Company, One Goal, Limitless Innovation. It's our people that make the difference. Job Mission We are looking for a talented engineering student with a strong and diverse background in electrical engineering to join our DUV EE controls team during the summer. This position will be a key contributor the characterization and testing of critical components and assemblies used in our DUV lasers. Your Assignment Develops test plans and fixtures for testing and characterization of the high voltage ceramic capacitors and related assemblies. Conducts performance and reliability characterization and testing over mechanical, environmental, and aging variables experienced by Cymer laser systems. Utilizes precision high voltage and current diagnostics and data acquisition equipment during performance testing and accelerated life testing Develops and implements programmable automated test scripts and data acquisition while using engineering and statistical analysis tools for data processing and analysis. Manage and monitor accelerated life testing shot accumulation, test conditions, and key performance indicators. Collaborates with pulsed power and laser discharge chamber teams on test planning, test execution, and data analysis. Collaborates with internal and external analytical services to provide optical, x-ray, and SEM analysis of sample components. Other responsibilities may be added as business conditions arise Your Profile Requires a minimum of three years progress toward Bachelor's Degree in Electrical or related field. Master's in progress candidate is strongly preferred. Experience At least 3 years of relevant academic or work related experience. Project leadership skills Experience with DoE (design of experiments) Strong background in analog circuit design; high power and voltage experience recommended Familiar with analog test equipment, LabVIEW, Python, and MatLab. Hands on experience with component-level and assembly hardware troubleshooting Experience with electronics test equipment - high-speed oscilloscopes, high speed voltage and current diagnostics, and high-speed data acquisition and process. Experience creating and executing detailed performance and life testing plans. Other information PHYSICAL DEMANDS AND WORK ENVIRONMENT The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions. While performing the duties of this job, the employee routinely is required to sit; walk; talk; hear; use hands to keyboard, finger, handle, and feel; stoop, kneel, crouch, twist, reach, and stretch. The employee is occasionally required to move around the campus. The employee may occasionally lift and/or move up to 50 pounds. Specific vision abilities required by this job include close vision, color vision, peripheral vision, depth perception, and ability to adjust focus. Can work under deadlines. The environment generally is moderate in temperature and noise level. Must be able to read and interpret data, information, and documents. Can observe and respond to people and situations and interact with others encountered in the course of work. Can learn and apply new information or skills. Work may include onsite technical support involving heavy lifting of equipment & modules. Position will require technical work activity in a clean-room production environment and/or laboratory setting. The environment generally is moderate in temperature and noise level. Occasionally may be exposed to loud noise bursts and may be exposed to toxic gases (fluorine). Must be able to work in small, confined spaces. The current base annual salary range for this role is currently $18.00 - $57.00. Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members. Our recruiters can share more information about our bonus program, benefits and equity during the hiring process. We are committed to leveraging the diverse backgrounds, perspectives, and experiences of our workforce to create opportunities for our people and the business. EOE This position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology. Inclusion and diversity ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions. Request an Accommodation ASML provides reasonable accommodations to applicants for ASML employment and ASML employees with disabilities. An accommodation is a change in work rules, facilities, or conditions which enable an individual with a disability to apply for a job, perform the essential functions of a job, and/or enjoy equal access to the benefits and privileges of employment. If you are in need of an accommodation to complete an application, participate in an interview, or otherwise participate in the employee pre-selection process, please send an email to USHR_Accommodation@asml.com to initiate the company's reasonable accommodation process. Please note: This email address is solely intended to provide a method for applicants to initiate ASML's process to request accommodation(s). Any recruitment questions should be directed to the designated Talent Acquisition member for the position.

We are looking for ambitious achievers to join our 2026 Kickstart Internship Program! Your work will support project teams providing solutions for water resources, water quality, wastewater and water treatment, and recycled water planning and implementation issues that our water environment, transportation, and industrial sector clients are facing. You will have opportunities to get involved in significant projects throughout the United States. These projects may involve field work, technical report preparation and calculations, pre-construction conditions documentation, design plans and specifications. What we can offer you Meaningful Projects and Work Mentorship Professional Development Networking and Collaboration A Day in the Life of an Electrical Engineering Intern: Getting involved in electrical systems design, load calculations, lighting design and calculations, developing design reports, construction documents and specifications, as well as construction oversight. Working on multiple, unique assignments simultaneously Preparing technical memoranda, contribute to preliminary and detailed design reports. Preparing utility coordination applications for local electric companies. Participating in water / wastewater electrical engineering design activities including preparation of design calculations, equipment sizing and selection, electrical room layouts, engineering specifications and cost estimates. Working collaboratively on multidisciplinary design teams and assist with coordination tasks. Office work may include task coordination, data compilation and interpretation, quality assurance/quality control reviews, cost estimates, report writing, proposal support, and cost estimate preparation. Strengthening AutoCad and/or Microstation skillsets to develop electrical construction documents including but not limited to, single line diagrams, equipment elevations, panelboard and luminaire schedules, conduit block diagrams, conduit/cable schedules and electrical plan drawings. Qualifications: Currently pursuing an undergraduate or graduate degree in Electrical Engineering CAD experience preferred Completion of a minimum of Sophomore (second-year) standing in an accredited engineering program Pay rate for this position is anticipated to be $20 to $25 per hour, and may vary based upon education, experience, qualifications, skills, licensure/certifications, seniority, geographic location, and performance. Intern Benefits Summary: As a Kickstart intern, you'll enjoy the benefits package designed to support you during your experience. Choose between quality medical coverage or a $150 monthly stipend if you have other coverage, plus receive $15 per month toward your cell phone costs. You'll also have the opportunity to participate in our 401(k) plan and accrue paid sick time throughout the program, ensuring that your well-being and future are always a priority. #LI-hybrid

At Coffman Engineers, we serve as both prime consultant and sub consultant on projects large and small, including commercial, retail, institutional, government, industrial, and project/construction management. Incorporated in 1979, we have employees in more than 23 locations serving clients across the United States and overseas. To meet client objectives and to integrate our many disciplines, we can create teams comprised of civil, structural, mechanical, electrical, fire protection, and corrosion control, as well as project/construction managers and professionals in a variety of specialty services. This ability has made us a leader in the engineering and construction communities, and has strengthened our reputation as being progressive, innovative, and a great place to work. Job Description We are seeking a dynamic and innovative Electrical Engineering Intern for our San Diego office for full time work over the summer months of 2026. This is a great opportunity to learn more about your electrical engineering in the AEC (Architecture, Engineering and Construction) industry! We design electrical building systems including power distribution systems, lighting and controls, receptacles, power for utilization equipment, and low-voltage systems for higher education, commercial and retail, healthcare, R&D Life Sciences and federal/government/military site and structures. We also design renewable systems such as photovoltaics (PV) and battery energy storage systems (BESS). The ideal candidate will be a student who wishes to focus on electrical/power systems for buildings, increase proficiency in Computer Aided Drafting software such as AutoCAD and Revit to produce electronic drawings, and work in a professional fast-paced environment. Qualifications Eligibility Requirements: Enrolled as a full-time student in an engineering program at a nationally recognized, accredited college. Two years of required courses completed towards an undergraduate electrical engineering degree. Prefer a candidate who has taken power engineering courses. Exceptional written and verbal communication skills Possess strong critical thinking, organizational, and analytical abilities (or demonstrate ability to develop such abilities). Expected Hourly Rate $25.00-$30.00, rate based on experience. This position is not eligible for sponsorship. Additional Information Why You Want To Work Here Coffman Engineers is a company that truly focuses on its employees. We support and encourage individually tailored professional and technical advancement as well as personal growth. We offer an excellent salary/benefits package, a desirable location, and a professional office environment with the opportunity to work with a collaborative team. Our offices provide several engineering discipline services, which work together collaboratively to provide complete engineering design packages. Coffman offers a flexible schedule and this position may be eligible for PTO, a fun office environment with a high-performing team and a fully stocked kitchen! We welcome the dedicated and the driven. Join us. Don't take our word for it. Check out what others are saying: ********************************************************************** Coffman at a Glance: 46 years in business 850+ employees serving clients throughout the U.S. and overseas from more than 23 locations Multi-discipline engineering services plus corrosion control, commissioning and project/construction management Zweig Group Hot Firm List, Zweig Group, 2021 Top 500 Design Firms, Engineering News-Record, 2022 Top Workplace (Small), The San Diego Union-Tribune, 2020, 2021, 2022, 2023, 2024 Best Places to Work (Large), San Diego Business Journal, 2021, 2022, 2023, 2024, 2025 “The List” for Engineering Firms, San Diego Business Journal, 2021, 2022, 2023, 2024, 2025 Applying You must apply online for this position. If you are unable to complete our online application process, or if you need assistance to do so, let us know so we can provide reasonable accommodation. If you are experiencing problems applying through our system, please try again using a different browser or an updated version of your current browser. If that doesn't work, please contact us directly. This position is direct with Coffman Engineers; we are an Equal Opportunity Employer. We do not discriminate on the basis of any status protected under federal, state, or local law. Follow Us! *************** Twitter: @CoffmanEngineer Instagram: @CoffmanEngineers LinkedIn: ************************************************** Facebook: @CoffmanEngineers

The application window is expected to close on: 02/28/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This is a hybrid role and will work out of our Carlsbad, CA or Allentown, PA office location. Meet the Team: The system hardware team in Cisco Client Optical Group is seeking a Senior PCB and Signal/Power Integrity Engineer for the design and analysis of high-speed PCB/substrate and power distribution networks. As a member of the hardware design team, you will help develop the next generations of Cisco optical module products, participating in the definition and design of current and next-generation ASICs, packages, PCBs and PCBAs. You will be working in a team of electrical and mechanical engineers, collaborating closely with system architects, ASIC engineers, package engineers, layout engineer and other SI/PI engineers in the creation of next-generation optical modules. Your Impact: High-speed link modeling and simulation, including high-speed I/O, IC package, chip-on-chip-on-substrate design and system interconnections. Modeling and analyzing power delivery networks. Electromagnetic modeling of complex 3-dimensional structures. Work with layout engineer on PCB placement and routing for best SI and PI performance. Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs and correct the issues on the layout. Write signal integrity design guidelines, PCB test plans, and test reports. Decide appropriate PCB material, stack-up, and work with vendors to address any DFM (Design for Manufacturability) issues. Support prototype function bring-up, validation, and troubleshooting. Work closely with other hardware team members including HW design, CAD, Mechanical, Power, EMC, and Diagnostics to deliver first-class products. Drive the definition, implementation, and continuous improvement of advanced SI/PI methodologies, simulation flows, and design processes. Lead comprehensive SI/PI/PCB design reviews, providing expert guidance and ensuring adherence to stringent performance and reliability targets. Minimum Qualifications: 5+ years of related experience with a Bachelor's Degree in EE, or 3+ years of experience with a Master's Degree. Experience applying EE fundamentals, EM theory, and coupling mechanisms in circuit or system design, analysis, troubleshooting through projects, coursework, or work experience. Demonstrated experience with simulation or analysis of transmission lines, channel modeling, and signal/power integrity via academic or professional projects. High-speed PCB design experience from concept to release. Practical experience configuring and interpreting measurements from VNA, TDR, and oscilloscopes, demonstrated in lab, research, or engineering roles. Preferred Qualifications: Working knowledge of tools such as: HFSS, Cadence Clarity 3Dlayout and workbench, Cadence PowerSI/PowerDC, Allegro PCB Editor, and Allegro Package Designer. Self-motivation, collaboration, strong communication, and a desire to innovate are important. Working experience with high-speed NRZ and PAM4 SerDes, as well as high-speed PCB/package development and PI analysis. Masters or PhD in Electrical Engineering Knowledge of optical transceiver module types, form factors, and requirements. Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada:The starting salary range posted for this position is $122,000.00 to $172,100.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $135,800.00 - $222,400.00 Non-Metro New York state & Washington state: $122,000.00 - $197,900.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

We are seeking a highly skilled RF, Analog, and Mixed Signal Engineer to join our engineering team. The ideal candidate will possess strong analytical abilities, a passion for innovation, and extensive experience in designing and implementing RF/mmW and/or analog/mixed-signal circuits. Description Our team is responsible for all aspects of silicon development for cellular transceivers, with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level. This highly visible role puts you at the center of a silicon design group with a critical impact on getting functional products to hundreds of millions of customers quickly! Responsibilities As an RF IC design engineer, you will be responsible for providing RF solutions for cellular transceiver chips. Responsibilities include: Working with platform architects, system, and digital design groups to define the requirements for RF and baseband blocks based on the system requirements. Collaborating with the technology team on process selection for the target device. Driving transistor-level feasibility studies of RF/mixed-signal circuit blocks and architectures. Designing various component blocks inside the RF transceiver, including LNA, upconverters/downconverters, baseband filters, VGAs, LO/PLL circuits, driver amplifiers/power amplifiers, linear RF switches, attenuators, low noise regulators, amplifiers, and biasing circuits. Working closely with the mask design team to implement layout views of designs. Minimum Qualifications BS and 3+ years of relevant industry experience required. Preferred Qualifications Direct experience designing and bringing into mass production highly integrated cellular RF transceivers in deep sub-micron RF CMOS technology. Ability to innovate and implement novel solutions for sophisticated engineering problems. Ability to collaborate with multi-functional teams to define system architecture and requirements. Familiarity with various RF transceiver architectures and their trade-offs; capability to collaborate with the digital design group for an optimum partition between the digital and analog domains. Deep understanding of RF CMOS implementation fundamentals and basic building blocks, including LNAs, mixers, VCOs and DCOs, PLLs, LO, and PAs. Design experience with digital TX or analog/digital/sampling PLL circuits is a bonus. Solid understanding of bandgaps, bias, opamps, LDOs, feedback, and compensation techniques. RF device modeling experience, including device noise parameters and inductor modeling. Insights into packaging effects, supply isolations, high-frequency ESD structures, and circuit layout for optimum RF performance. Very good knowledge of one or more of the following tools: Cadence/Virtuoso, Spectre, AMS, GoldenGate, AFS, ADS, EMX, layout parasitic extraction tools, SimVision, RelExpert. Bring-up and debugging skills, and experience in working with production test engineers to build test plans and design for testability. Ability to stay up to date with industry trends and new technologies to drive continuous improvement. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $139,500 and $258,100, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. ** Must be a U.S. citizen and eligible to receive a U.S. Government security clearance ** We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands‑on experience in RTL‑to‑GDSII flow, with a strong focus on floor‑planning, clock tree synthesis, place‑and‑route, DRC and timing closure. This role involves architecting and implementing robust, low‑skew, power‑efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals. This role requires full‑time onsite work in San Diego, CA (5 days per week). Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field. Key Responsibilities: Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry‑standard tools (e.g., Innovus, ICC2). Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing, congestion, and DRC issues. Optimize design for power, performance, and area (PPA). Conduct formal equivalence checks between RTL and netlist. Support physical verification including DRC, LVS, and antenna checks. Work closely with backend teams for tapeout preparation and signoff. Excellent scripting skills (TCL, Python, Perl) for reference flow automation. Execute full‑chip and block‑level physical verification including DRC, LVS, ERC, antenna, and density checks using industry‑standard tools (e.g., Calibre, Pegasus, ICV). Customize and optimize reference physical verification flows to align with project needs and foundry requirements. Perform GDS‑to‑GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness. Debug and resolve physical verification violations, working closely with layout, design, and CAD teams. Collaborate with foundries to ensure compliance with the latest design rule manuals (DRMs) and tapeout checklists. Support signoff verification, including multi‑corner/multi‑mode analysis and ECO validation. Develop and maintain automation scripts for verification flows, reporting, and regression testing. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability. Ensure timely delivery of clean GDSII for tapeout, with full verification signoff. Perform full‑chip and block‑level static timing analysis (STA) using industry‑standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners. Collaborate with RTL, synthesis, and physical design teams to ensure timing‑aware design practices. Debug and resolve setup, hold, and transition violations across various PVT corners. Drive timing closure through iterative optimization and ECO implementation. Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability. Analyze clock tree timing, including skew, latency, and jitter impacts. Support signoff timing verification, including cross‑domain timing and false/multicycle path handling. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing insights on timing risks and mitigation strategies. Define and implement low‑power architecture using CLP methodology across RTL and physical design stages. Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications. Customize and optimize low‑power reference flows to meet project‑specific requirements. Collaborate with RTL, synthesis, and physical design teams to integrate power‑aware features such as power gating, retention, isolation, and level shifting. Perform power‑aware static checks, simulation, and formal verification to validate power intent. Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing. Support signoff verification including power‑aware LVS/DRC, STA, and EM/IR analysis. Interface with EDA vendors to resolve tool issues and improve low‑power flow robustness. Participate in design reviews, providing insights on power architecture, risks, and mitigation strategies. Ensure compliance with foundry low‑power guidelines and contribute to successful tapeout. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 3+ years of experience in physical design, with a focus on clock tree design and implementation. Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design. Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime). Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies. Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis. Familiarity with low‑power design techniques, including clock gating and multi‑voltage domains. Preferred Skills: Experience with custom clock tree architectures such as H‑tree, mesh, or spine‑based topologies. Knowledge of EM/IR analysis, thermal‑aware clocking, and reliability modeling. Exposure to high‑speed interface clocking (e.g., SerDes, DDR, PCIe). Understanding of package‑level clock planning and signal integrity. Principal Duties & Responsibilities: Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates architectures, circuit specifications, logic designs, and/or system simulations based on system‑level requirements. Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of process flow from high‑level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package. Writes detailed technical documentation for EDA/IP/ASIC projects. Level of Responsibility: Works independently with minimal supervision. Decision‑making may affect work beyond immediate work group. Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). Tasks require multiple steps which can be performed in various orders; some planning, problem‑solving, and prioritization must occur to complete the tasks effectively. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits $115,600.00 - $173,400.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

A prominent engineering firm in San Diego is seeking a Principal in Electrical Engineering to lead strategic projects and develop client relationships. Responsibilities include managing engineering practices, driving business development, and overseeing project teams. Candidates should have extensive experience and a Bachelor's degree in engineering. This role offers competitive compensation and a collaborative work environment. #J-18808-Ljbffr

Job Description: Field Engineer: Candidate will be responsible for executing field tests on the latest test devices and software, troubleshooting issues found, collecting Key Performance Indicators. The effort will involve multimode operations, gaining knowledge in the following technology areas: CDMA2000, 1xEV-DO, WCDMAGSM/GPRS, LTE, and 5G. The position may require travel in North America 75% of the time and an opportunity to relocate to critical markets for longer durations. Candidate will be working with a multi-discipline team (Software Development, System Design, Customer Support, ASIC Design, RF Circuits and Hardware Design, etc.) to test and commercialize products. Successful candidate must have strong communication skills, must be an effective team player and be able to work independently. Job responsibilities include conducting drive tests, troubleshooting/analyzing problems, optimizing system performance and supporting the customers with product commercialization. All Qualcomm employees are expected to actively support diversity on their teams, and in the company. Min Reqs 0-3 years experience in Field Testing or System Optimization role. Exposure in one or more of following areas: Understanding of digital communications systems, RF propagation, CDMA, OFDM, telecommunications concepts Understanding of Physical/MAC layers and Call Processing concepts in one or more of the following air interface standards CDMA2000, 1xEV-DO (Rev 0/A/B), GSM/ GPRS /EDGE / Rel99/ Rel5 / HSDPA/ HSUPA/HSPA+, LTE,5G Understanding of wire line and wireless data protocol stacks including RLP, PPP, IP, TCP, IPV6, MIPV6, etc. Understanding of software development and testing concepts for wireless handsets for various air interface standards Familiarity with IP telephony network , SIP, IMS, and IP telephony standards Familiarity with air interface performance analysis, characterization and optimization Exposure to programming in C, Perl, shell scripting. Comments for Suppliers: 0-3 years of experience Previous experience within Mobile is strongly preferred Must be able to drive- drivers clearance required Communication is extremely important Position is onsite critical and travel to other markets is required. Denver, Vegas, Texas, etc. Wherever we need testing

At Coffman Engineers, we serve as both prime consultant and sub consultant on projects large and small, including commercial, retail, institutional, government, industrial, and project/construction management. Incorporated in 1979, we have employees in more than 23 locations serving clients across the United States and overseas. To meet client objectives and to integrate our many disciplines, we can create teams comprised of civil, structural, mechanical, electrical, fire protection, and corrosion control, as well as project/construction managers and professionals in a variety of specialty services. This ability has made us a leader in the engineering and construction communities, and has strengthened our reputation as being progressive, innovative, and a great place to work. Job Description We are seeking a dynamic and innovative Electrical Engineering Intern for our San Diego office for full time work over the summer months of 2026. This is a great opportunity to learn more about your electrical engineering in the AEC (Architecture, Engineering and Construction) industry! We design electrical building systems including power distribution systems, lighting and controls, receptacles, power for utilization equipment, and low-voltage systems for higher education, commercial and retail, healthcare, R&D Life Sciences and federal/government/military site and structures. We also design renewable systems such as photovoltaics (PV) and battery energy storage systems (BESS). The ideal candidate will be a student who wishes to focus on electrical/power systems for buildings, increase proficiency in Computer Aided Drafting software such as AutoCAD and Revit to produce electronic drawings, and work in a professional fast-paced environment. Qualifications Eligibility Requirements: Enrolled as a full-time student in an engineering program at a nationally recognized, accredited college. Two years of required courses completed towards an undergraduate electrical engineering degree. Prefer a candidate who has taken power engineering courses. Exceptional written and verbal communication skills Possess strong critical thinking, organizational, and analytical abilities (or demonstrate ability to develop such abilities). Expected Hourly Rate $25.00-$30.00, rate based on experience. This position is not eligible for sponsorship. Additional Information Why You Want To Work Here Coffman Engineers is a company that truly focuses on its employees. We support and encourage individually tailored professional and technical advancement as well as personal growth. We offer an excellent salary/benefits package, a desirable location, and a professional office environment with the opportunity to work with a collaborative team. Our offices provide several engineering discipline services, which work together collaboratively to provide complete engineering design packages. Coffman offers a flexible schedule and this position may be eligible for PTO, a fun office environment with a high-performing team and a fully stocked kitchen! We welcome the dedicated and the driven. Join us. Don't take our word for it. Check out what others are saying: ********************************************************************** Coffman at a Glance: 46 years in business 850+ employees serving clients throughout the U.S. and overseas from more than 23 locations Multi-discipline engineering services plus corrosion control, commissioning and project/construction management Zweig Group Hot Firm List, Zweig Group, 2021 Top 500 Design Firms, Engineering News-Record, 2022 Top Workplace (Small), The San Diego Union-Tribune, 2020, 2021, 2022, 2023, 2024 Best Places to Work (Large), San Diego Business Journal, 2021, 2022, 2023, 2024, 2025 “The List” for Engineering Firms, San Diego Business Journal, 2021, 2022, 2023, 2024, 2025 Applying You must apply online for this position. If you are unable to complete our online application process, or if you need assistance to do so, let us know so we can provide reasonable accommodation. If you are experiencing problems applying through our system, please try again using a different browser or an updated version of your current browser. If that doesn't work, please contact us directly. This position is direct with Coffman Engineers; we are an Equal Opportunity Employer. We do not discriminate on the basis of any status protected under federal, state, or local law. Follow Us! *************** Twitter: @CoffmanEngineer Instagram: @CoffmanEngineers LinkedIn: ************************************************** Facebook: @CoffmanEngineers

A leading technology company is seeking a highly skilled RF/Analog/Mixed Signal IC Design Engineer to join their innovative engineering team in San Diego. The role involves designing RF solutions for cellular transceivers and collaborating with various teams to ensure optimal product performance. The ideal candidate will have extensive experience in RF/mixed-signal circuit design, strong analytical skills, and the ability to innovate. This position offers a competitive salary and comprehensive benefits package including stock options and educational reimbursements. #J-18808-Ljbffr

A leading technology firm in San Diego seeks talented analog integrated circuit designers for the QCT Mixed-Signal IP design team. The role involves developing high-performance and low-power mixed-signal IPs for cutting-edge applications. Ideal candidates will possess a Master's or Bachelor's degree in engineering, with demonstrated experience in analog design and ASIC tools. This position offers competitive compensation and a comprehensive benefits package. #J-18808-Ljbffr