Engineer jobs in Milpitas, CA - 15,957 jobs

A global semiconductor company in San Jose is seeking a Principal Power Module Design Engineer. This role involves new product development in power electronics, requiring at least a master's or Ph.D. in Power Electronics and 5+ years of experience in related design. Applicants should possess strong skills in switching power converter design and analog circuit design. The position offers competitive compensation, a collaborative environment, and opportunities for professional growth. #J-18808-Ljbffr

Physical Design Engineer - New College Grad 2026 page is loaded## Physical Design Engineer - New College Grad 2026locations: US, CA, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR2009983We are now looking for a Physical Design Engineer!NVIDIA has continuously pioneered and reinvented itself over two decades through various avenues of computing: Graphics, High Performance Computing, Artificial Intelligence, Research, and more. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can solve, and that matter to the world. This is our life's work, to amplify human creativity, intelligence, and technology. Today, visual computing is becoming increasingly central to how people interact with technology, and there has never been a more exciting time to join our team. We are looking for a Physical Design Engineer who will be responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets, and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets.**What you will be doing:*** As a member of the team, you will participate in the efforts in establishing CAD and physical design methodologies (flow and tools development) as well as implementation.* Your day to day will include developing chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects.* This position requires you to work with EDA vendor (Synopsys, Cadence, Mentor, etc.) tool suites such as: ICC2,PrimeTime, dc\_shell, Innovus, SeaHawk.* You will interact with a diverse team engineers.**What we need to see:*** Completing an BSEE, MSEE or PhD (or equivalent experience).* Deep understanding of VLSI and Physical Design related basics & concepts.* Possess a deep understanding of static timing analysis, clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis.* Experience in scripting and programming using several of the following languages/tools: Perl, C, C++, TCL, Scheme, Skill, or Make.* Previous internship or project experience in physical design implementation With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a passion for technology, we want to hear from you!Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 96,000 USD - 161,000 USD for Level 1, and 108,000 USD - 184,000 USD for Level 2.You will also be eligible for equity and .Applications for this job will be accepted at least until December 19, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr

A global technology company is looking for a seasoned software engineer to enhance AI capabilities within their observability platform. Candidates should have a strong background in AI/ML systems, cloud computing, and robust technical leadership. This role is pivotal in driving innovation in data analysis and delivering scalable solutions. The ideal candidate will thrive in an agile environment and provide mentorship to junior engineers. Enjoy competitive salaries and benefits while contributing to impactful technology solutions. #J-18808-Ljbffr

An automotive giant is seeking a Staff ML Engineer for their ML Compute Platform to scale backend services and contribute to AI infrastructure. Responsibilities include designing software components, improving system efficiency, and leading initiatives. Candidates should have 7+ years of experience and expertise in languages like Go, C++, or Python, as well as a solid background in distributed systems. Join a team that's transforming mobility and tackling complex engineering challenges with AI applications. #J-18808-Ljbffr

A technology firm specializing in integrated task systems seeks a Machine Learning Researcher / ML-Ops Engineer to advance computer vision and sensor fusion capabilities. The role involves implementing machine learning pipelines and optimizing models for deployment. Candidates should have a strong Python background and experience in deep learning frameworks like PyTorch and TensorFlow. This position in Palo Alto, California, offers competitive compensation and a collaborative work environment. #J-18808-Ljbffr

Since its founding in 2015, 1X has been at the forefront of developing advanced humanoid robots designed for household use. Our mission is to create an abundant supply of labor via safe, intelligent humanoids. We strive for excellence in all we do, solving some of the hardest problems in robotics with the world's most talented individuals. Every part of our robots is designed and produced in-house-from motor coils to AI-reflecting our vertically integrated approach. At 1X, you'll own real projects, be recognized for your achievements, and rewarded based on merit. Why this job is exciting Join the NEXT team shaping the foundations of the future humanoid robot Tackle unsolved challenges like human-level walking, dexterous manipulation, and embodied perception Push the boundaries of research into practical, buildable solutions-fast Responsibilities Research, design, and prototype fundamental humanoid technologies including actuation systems, robotic joints, and structural components Model and simulate systems to evaluate performance and feasibility Design experiments and analyze results to validate hypotheses and inform engineering tradeoffs Build and iterate on physical prototypes using machining, rapid fabrication, and embedded systems Evaluate academic research and patents for technical inspiration and practical application Distill high-concept ideas into actionable engineering workstreams Collaborate closely with other domain experts to bridge theory and application Requirements Strong grasp of core engineering principles including math, mechanics, and materials Experience designing actuation systems-motors, drivetrains, joints, structures Background in Mechanical Engineering, Electrical Engineering, Physics, or similar Demonstrated ability to go full-stack in R&D: from concept to prototype to evaluation Skilled at assessing feasibility and filtering high-potential ideas from theoretical noise Nice-to-haves Passion for building, tinkering, or technical exploration-professional or personal Portfolio of personal or professional projects you've designed and built Experience developing novel systems from scratch-not just incremental improvements Interest in human biomechanics or the nervous system as it relates to robotics Strong communication skills and ability to present bold technical concepts Appreciation for historical inventors and scientific pioneers PhD in a relevant technical field Location Policy We believe the best work is done when collaborating and therefore require in-person presence in our office locations. Not sure if this is you? If you're excited about 1X and this role but not sure if you qualify, apply anyway! You may be the right candidate for this or other roles. 1X is an inclusive and equal-opportunity employer that values diversity. We consider all qualified applicants regardless of race, religion, gender, age, sexual orientation, disability, or any other protected class. If you have a disability or special need that requires accommodation, please let us know. We will do our best to accommodate your needs. We're excited to get to know you and the prospect of having you on board! #J-18808-Ljbffr

A tech innovation company in Mountain View, California, is seeking a Machine Learning Research Engineer. You'll design sophisticated robot learning algorithms to enhance dexterous manipulation in home environments. The role requires 3+ years in machine learning for robotics and proficiency with Python, particularly PyTorch. This is an opportunity to join a passionate team working at the forefront of robotics technology, ensuring personal robots are accessible for everyday households. #J-18808-Ljbffr

A leading tech company invites applications for a Machine Learning Engineer to advance AI research in California. The role focuses on Generative AI and requires a PhD or Master's degree, with a minimum of 3 publications in AI. The candidate will collaborate across teams and publish findings, contributing to networking solutions and AI innovations. This full-time position offers a competitive salary and benefits, fostering an inclusive workplace culture. #J-18808-Ljbffr

A leading technology firm in Santa Clara is seeking an Applied SciML Engineer with expertise in scientific machine learning and computational geometry. The ideal candidate will have a minimum of 3 years of deep learning experience and proficiency in PyTorch. This role focuses on building production ML systems for physical simulation data. Candidates should have a strong background in model development, optimization, and application to scientific datasets. #J-18808-Ljbffr

A leading technology company in Sunnyvale is seeking engineers to build ASIC/System on Chip (SoC) solutions for data center applications. The role involves emulation and prototyping, with responsibilities including delivering high-quality models and collaborating with various teams. The ideal candidate should have a bachelor's degree and over 6 years of experience in EDA tools and emulation technologies. Competitive compensation package includes annual salary ranging from $142,000 to $203,000. #J-18808-Ljbffr

At Serve Robotics, we're reimagining how things move in cities. Our personable sidewalk robot is our vision for the future. It's designed to take deliveries away from congested streets, make deliveries available to more people, and benefit local businesses. The Serve fleet has been delighting merchants, customers, and pedestrians along the way in Los Angeles, Miami, Dallas, Atlanta and Chicago while doing commercial deliveries. We're looking for talented individuals who will grow robotic deliveries from surprising novelty to efficient ubiquity. Who We Are We are tech industry veterans in software, hardware, and design who are pooling our skills to build the future we want to live in. We are solving real-world problems leveraging robotics, machine learning and computer vision, among other disciplines, with a mindful eye towards the end-to-end user experience. Our team is agile, diverse, and driven. We believe that the best way to solve complicated dynamic problems is collaboratively and respectfully. The Lead Engineer, RL Scaling & Procedural Scenario Generation is responsible for building scalable training pipelines and generating high-fidelity synthetic scenarios. This role designs procedural simulation environments, creates diverse long-tail edge cases, and optimizes RL systems to train robust foundational models. This role sits at the intersection of simulation, machine learning, distributed systems, and content generation and has a high impact on how quickly and safely agents learn in simulation. Responsibilities Develop RL algorithms that can help with terrain intelligence and social navigation behaviors. Design, build, and optimize large-scale RL training pipelines (distributed compute, GPU clusters, containerized workflows). Implement curriculum learning, domain randomization, and multi-agent RL strategies. Optimize RL model performance, sample efficiency, and stability across thousands to millions of simulation steps. Build automated tools for experiment orchestration, rollout collection, and metrics visualization. Develop procedural generation pipelines for synthetic environments, agents, and dynamic behaviors. Build tools to generate long-tail scenarios, sudden appearance of objects, traffic behaviors, rare events, and environmental variations. Create systems for configuration, validation, and scoring of generated scenarios. Collaborate with autonomy, ML, and safety teams to map real-world failures into repeatable synthetic simulation cases. Design APIs to connect RL agents, scenario generators, planners, and environment simulators. Debug and optimize simulation performance (real-time speed, determinism, reproducibility). Work with 3D assets, traffic models, mapping systems (e.g., Isaac Sim, CARLA, Unity, Gazebo). Partner with autonomy, data, and modeling teams to define training objectives and scenario requirements. Translate real-world logs and edge cases into parameterized procedural content. Document tools, frameworks, and workflows for internal users. Qualifications Master's degree in Robotics, AI, Computer Science, Mathematics, or a related field. 7+ years of professional experience with shipping transformer based AI models handling complex navigation or manipulation tasks in AV or robotics solutions at scale in the real world. 3+ years technical leadership/architecture experience Strong experience with Reinforcement Learning (PPO, SAC, A3C, DQN, multi-agent RL, or equivalents). Hands-on experience with distributed training frameworks (Ray RLlib, Accelerate, PyTorch Distributed, Kubernetes, or similar). Proficiency in Python and C++ for performance-critical simulation or graphics pipelines. Experience building or modifying simulation environments (Isaac Sim, Unity, Unreal, CARLA, Gazebo, MuJoCo or custom engines). Experience with procedural generation (noise functions, rule-based systems, agent scripts, behavior trees). Experience with GPU compute, containers, and cloud infrastructure. What Makes You Stand Out Background in generative AI (diffusion, LLMs) for scenario synthesis or environment creation. Experience with traffic simulation (SUMO) or sensor simulation (LiDAR, camera pipelines). Knowledge of CUDA, graphics engines, physics modeling, or rendering. * Please note: The base salary range listed in this job description reflects compensation for candidates based in the San Francisco Bay Area. We are also open to qualified talent working remotely across the: United States - Base salary range (U.S. - all locations): $190k - $230k USD Canada - Base salary range (Canada - all locations): $160k - $190k CAD #J-18808-Ljbffr

A leading technology company is seeking a Staff Machine Learning Engineer based in Mountain View, CA. In this pivotal role, you will develop and deploy advanced machine learning models to address challenges in today's complex electric grid. You will lead model building efforts, mentor junior engineers, and collaborate on cross-functional projects. Ideal candidates have over 10 years of experience in machine learning, strong Python skills, and familiarity with ML frameworks like PyTorch and TensorFlow. Join us and make a significant impact on the energy future. #J-18808-Ljbffr

A leading technology firm in California is looking for an experienced Staff Machine Learning Engineer. In this role, you will drive the technical direction of machine learning technology, design and build impactful solutions, and lead cross-team initiatives. The ideal candidate has extensive experience in machine learning and is skilled in collaboration and mentorship. This position offers competitive compensation with equity options and emphasizes a diverse and inclusive workplace. #J-18808-Ljbffr

A leading energy storage solutions company is seeking a factory manager for their new facility in California. This exciting role involves selecting equipment, hiring engineers, and scaling innovative sodium metal chloride battery technology. Successful candidates will have an engineering degree and over 10 years of management experience in manufacturing. The position offers $190k-$250K compensation and comprehensive benefits, including unlimited PTO and stock options. Join a mission-driven team dedicated to affordable and sustainable energy solutions. #J-18808-Ljbffr

Altera .# **Job Details:**### ## **Job Description:****About the Role:**As a Physical Design Engineer at Altera, you will play a critical role in the backend implementation flow - from RTL/netlist through GDSII/tape-out for FPGA/SoC devices. You will collaborate with architecture, logic design, DFT, CAD/EDA, and manufacturing teams to achieve performance, power, and area (PPA) goals, with a particular emphasis on programmable logic structures, block and full-chip integration, and the unique demands of FPGA technologies (e.g., configurable logic blocks, routing fabrics, I/O rings, on-chip power domains).**Key Responsibilities:*** Execute physical design implementation tasks (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist to GDSII.* Apply PPA optimization techniques (performance/timing closure, power reduction, area efficiency) across block-level and full-chip hierarchies.* Collaborate with front-end design, architecture, and CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets, and DFT insertions are met.* Develop and enhance physical design flows, methodologies, scripts, and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR, and reduce manual intervention.* Participate in timing, power, EM/IR integrity, signal/power noise, and DRC/LVS/ERC verification for sign-off readiness.* Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization.* Debug physical design issues and interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.**$127,400 - $184,400 USD**We use artificial intelligence to screen, assess, or select applicants for the position.### ## **Qualifications:****Minimum Qualifications:**Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 6+ years of experience in:* Hands-on digital/SoC physical design (synthesis through P&R and sign-off).* Industry-standard EDA tools (e.g., Synopsys IC Compiler/Fusion, Cadence Innovus/Encounter, PrimeTime, STAR-RCX, Calibre) for high-speed digital ASIC/SoC implementation.* Scripting/programming (TCL, Python, Perl, shell) for flow automation and productivity enhancement.* Physical design flow: floorplanning, CTS, placement, routing, power domain gating, clock domain crossing, multi-power domain design, timing closure, ECOs, and DRC/LVS/DFM resolution.* Power/IR analysis, signal/power integrity reporting, and corrective action planning.* Interfacing with front-end teams (RTL, architecture), CAD/EDA tool teams, and manufacturing/packaging teams.**Preferred Qualifications:*** Experience with advanced process nodes (7nm, 5nm or smaller) or FPGA/programmable logic device flows.* Familiarity with FPGA architecture: routing fabrics, programmable logic blocks (PLBs), on-chip networks, I/O rings, static/dynamic reconfiguration.* Expertise in low-power design methodologies, power grid design, power gating, multi-voltage domain implementation, and power sign-off flows.* Prior exposure to full-chip integration flows (block-to-chip convergence) and high-frequency (1 GHz+) timing closure.* Experience in high-volume manufacturing environments, including yield and DFM/DFY considerations.* Experience mentoring or leading small physical design sub-teams or owning major P&R blocks.### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr

A leading research lab in Sunnyvale is seeking a distributed ML infrastructure engineer to extend and scale training systems. The ideal candidate must have over 5 years of experience in ML systems with strong expertise in distributed training frameworks like DeepSpeed and FSDP. This role offers a competitive salary ranging from $150,000 to $450,000 annually along with comprehensive benefits and amenities. #J-18808-Ljbffr

A technology company is seeking a Platform Validation Engineer to ensure the reliability and performance of their GPU servers. This role involves developing test plans, debugging hardware and software interactions, and automating validation workflows. Candidates should have a Bachelor's or Master's degree in EE or CS with over 5 years of experience in GPU server platform validation. The position offers a hybrid work model at the Santa Clara headquarters. #J-18808-Ljbffr

About Us Rivian and Volkswagen Group Technologies is a joint venture between two industry leaders with a clear vision for automotive's next chapter. From operating systems to zonal controllers to cloud and connectivity solutions, we're addressing the challenges of electric vehicles through technology that will set the standards for software-defined vehicles around the world. The road to the future is uncharted. By combining our expertise across connectivity, AI, security and more, we'll map a new way forward. Working together, we'll create a future that's more connected, more intelligent, more sustainable for everyone. Role Summary As an engineer focusing on cellular and wireless integration for the Connected Systems Integration Team at R|V Tech, you will work alongside software developers, systems integrators, and system engineers to support features such as cellular, WiFi, Ethernet and GPS domains along with telematics, mobile app integration, and other Internet-dependent vehicle features, with a primary focus on cellular systems integration and bring-up. The cellular and wireless integration engineer will execute tests and integration of connectivity features and will also contribute to automation of these tests (in Python). The cellular and wireless integration engineer may also support other vehicle development activities which require connectivity support. These development activities may include drives in pre-production vehicles and will provide exposure to vehicle networks, cloud connectivity, and fleet management. The connectivity integration engineer may support time-critical test events and may be asked to support special investigations and projects. Responsibilities Your typical day looks like this: Attend meetings with development teams to understand new system designs and to align on test plans and expectations. Create design documentation and test plans for a new cellular feature implementation. Perform cellular testing using a specialized test chamber and test equipment; work with test equipment vendors to ensure compatibility and system integrity for automation. Perform complementary cellular testing on-vehicle using a prototype or fleet vehicle. Analyze logs from internal and external bugs to assess root cause of failure and create new work scope for dev teams. Core capabilities and behaviors should include: Strong fundamentals for test execution and documentation. The ability to correlate meaningful feedback from disparate data sets. Keen observation skills of wireless (WiFi, 5G, LTE, GPS, Bluetooth) behavior and performance. Deep understanding of telematics, end-to-end data routing and validation of data fidelity and frequency over different data links. Understanding of middleware and layered/encapsulated network schemes. Native Linux proficiency (command-line, tools, bring-up); embedded Linux a plus. Ability to identify and distinguish issues in hardware and/or software. Engage in discussions to test, bug fix, and optimize feature development based on data. Qualifications Bachelor's degree in either Computer Science, Computer Engineering, Electrical Engineering, Software Engineering, or Information Systems. Good understanding of 5GNR and LTE protocol stack. A working understanding of the OSI model and network protocols. Basic proficiency with scripting languages including Python and/or Shell. Basic proficiency with database manipulation and data presentation. Triage and diagnosis of complex connectivity issues to include root cause analysis, stability, and interoperability problems. A mindset geared towards collaboration and forward progress. Ability to thrive under pressure and time constraints. Availability to travel and/or support activities during off-peak hours as-needed. Pay Disclosure Salary Range/Hourly Rate for Palo Alto, California Based Applicants: $117,000 - $149,000 USD (actual compensation will be determined based on experience, location, and other factors permitted by law). Benefits Summary: Rivian and Volkswagen Group Technologies provides robust medical/Rx, dental and vision insurance packages for full-time and part-time employees, their spouse or domestic partner, and children up to age 26. Full Time Employee coverage is effective on the first day of employment. Part-Time employee coverage is effective the first of the month following 90 days of employment. Equal Opportunity Rivian and Volkswagen Group Technologies is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, sex, sexual orientation, gender, gender expression, gender identity, genetic information or characteristics, physical or mental disability, marital/domestic partner status, age, military/veteran status, medical condition, or any other characteristic protected by law. We are also committed to ensuring compliance with all applicable fair employment practice laws regarding citizenship and immigration status. Rivian and Volkswagen Group Technologies is committed to ensuring that our hiring process is accessible for persons with disabilities. If you have a disability or limitation, such as those covered by the Americans with Disabilities Act, that requires accommodations to assist you in the search and application process, please email us at candidateaccommodations@rivian.com. Candidate Data Privacy Rivian and VW Group Technologies (“Rivian and Volkswagen Group Technologies”) may collect, use and disclose your personal information or personal data (within the meaning of the applicable data protection laws) when you apply for employment and/or participate in our recruitment processes (“Candidate Personal Data”). This data includes contact, demographic, communications, educational, professional, employment, social media/website, network/device, recruiting system usage/interaction, security and preference information. Rivian and VW Group Technologies may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. Rivian and Volkswagen Group Technologies may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian and Volkswagen Group Technologies affiliates; and (iii) Rivian and Volkswagen Group Technologies' service providers, including providers of background checks, staffing services, and cloud services. Rivian and Volkswagen Group Technologies may transfer or store internationally your Candidate Personal Data, including to or in the United States, Canada, and the European Union and in the cloud, and this data may be subject to the laws and accessible to the courts, law enforcement and national security authorities of such jurisdictions. Please see our Candidate Data Privacy Notice (English) and Candidate Data Privacy Notice (Serbian) for more information. Please note that we are currently not accepting applications from third party application services. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking a Senior High-Speed Mixed-Signal Layout/Analog Engineer. In this role, you will collaborate with circuit designers, optimize performance for SERDES analog PHY, and utilize tools like Virtuoso and Calibre. Ideal candidates have a Bachelor's with extensive experience in RF/analog design. The position offers a competitive salary ranging from $180,950 to $289,050 USD and comprehensive benefits including medical, dental, and flexible work options. #J-18808-Ljbffr