Product Engineer jobs at Esri - 204 jobs

Senior Engineer, Product Applications page is loaded## Senior Engineer, Product Applicationslocations: US, CA, San Jose, Rio Roblestime type: Full timeposted on: Posted Todayjob requisition id: R257895**About Analog Devices**Analog Devices, Inc. (NASDAQ: ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at and on and .**Employer:** Analog Devices, Inc.**Job Title:** Senior Engineer, Product Applications**Job Requisition:**R257895 **Job Location:** San Jose, California**Job Type:** Full Time**Rate of Pay:** $164,115.00 - $187,680.00 per year**Duties:** Create and present training and education material for other ADI Engineers and customers on product design, application, and service information. Define, develop and support new products or technologies, which may include hardware reference designs or software. Drive, define and approve customer facing collateral, documentation and application notes. Design, lay-out, build, and test application boards to validate products, and develop demonstration systems to show-off industry-leading features to potential and existing customers. Provide technical support to customers to secure design-ins and sales for their assigned portion of the product portfolio. Support customer visits to qualify new opportunities or features, resolve customer issues and define new product ideas. Mentor Jr. Level Engineers. Recommend actions to resolve quality or performance issues. Perform system architecture analysis. Perform hardware, software, and system testing, debugging, and troubleshooting. Report design, reliability and maintenance problems or bugs to product team. Design models and/or use system modeling or test tools to facilitate development. Partial telecommute benefit (2 days/week work from home).Experience and skills may be gained in a graduate program.**Requirements:** Must have a Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering or closely related technical field (willing to accept a foreign educational equivalent) and two (2) years of experience as an Applications Engineer or related occupation performing hardware, software, and system testing, debugging, and troubleshooting in the development of power, mixed signal, or electronic products as part of a cross-functional project team.* Demonstrated understanding of analog circuitry, DC-DC converter topologies, and control theory.* Demonstrated Expertise (“DE”) using ADCs, DACs, amplifiers, analog and digital filters, I2C, SPI, microcontrollers, circuit design, or PCB layout; collaborating with firmware/API/GUI development teams to guide software integration; or testing PCBs to validate products and demonstrate IC performance.* DE designing, debugging evaluation kits, test boards, and reference designs, and automating bench testing of new ICs for device operation, including measurement collection and software authoring using oscilloscopes, power supplies, and DMMs.* DE creating customer facing collateral, documentation and application notes and facilitating resolution of customer issues.* DE either programming using C, C#, Visual Basic, Python, MATLAB, or LabView, or familiarity with circuit simulation tools such as SPICE.* Proficient in development of training materials for other engineers and customers on product design, application, and service information.**Contact:** Eligible for employee referral program. Apply online at and Reference Position Number: R257895 .*For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.**Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.**EEO is the Law: .*Job Req Type: ExperiencedRequired Travel: NoShift Type: 1st Shift/Days* Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.* This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.* This position includes medical, vision and dental coverage, 401k, paid vacation, **holidays, and sick time**, and other benefits. #J-18808-Ljbffr

A leading semiconductor company in San Jose seeks a Senior Engineer in Product Engineering to manage new product introductions and production support. Candidates should have a Master's degree in Electrical Engineering and two years of relevant experience. Responsibilities include interfacing with manufacturing, conducting failure analyses, and implementing process improvements. This role offers competitive pay and benefits, including healthcare coverage and a performance-based bonus. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking a Staff Power Module Design Engineer. You'll develop innovative power module products and collaborate with industry experts. The role requires a strong educational background in Power Electronics and significant experience in switching power converter design. This position offers competitive pay within a vibrant engineering team, fostering professional growth and mentorship opportunities. #J-18808-Ljbffr

Copy link Google Sunnyvale, CA, USAMidExperience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. Academic, educational, internship, or project experience with RTL coding, Verilog, or SystemVerilog. Preferred qualifications: Experience with scripting language (e.g., Python or Perl). Experience applying engineering best practices (e.g. code review, testing, refactoring). Experience interacting with software, architecture, and other cross-functional teams. Knowledge of processor design or accelerators. Knowledge of high-performance and low power design techniques. Knowledge of processor design, accelerators, or memory hierarchies. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As an RTL Design Engineer, you will be part of a team developing ASICs to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google. Responsibilities Understand the overall application of the chip, proposing and developing improvements in overall design. Design and document one or more blocks of an ASIC, including functionality and timing. Work closely with software teams on functionality, interfaces, and documentation. Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire. #J-18808-Ljbffr

A leading tech company in California is seeking a skilled UX Engineer to join their innovative team. In this role, you will focus on front-end development and collaborate with multi-disciplinary teams to create engaging and industry-leading products that impact millions. Candidates should have at least 8 years of relevant experience and a strong background in UX design and prototyping. This position offers a competitive salary ranging from $178,000 to $265,000, along with bonus and benefits. #J-18808-Ljbffr

A global semiconductor company in San Jose is seeking a Principal Power Module Design Engineer. This role involves new product development in power electronics, requiring at least a master's or Ph.D. in Power Electronics and 5+ years of experience in related design. Applicants should possess strong skills in switching power converter design and analog circuit design. The position offers competitive compensation, a collaborative environment, and opportunities for professional growth. #J-18808-Ljbffr

corporate_fare Google place Sunnyvale, CA, USA Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Apply link Copy link Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with physical design. Experience in physical design areas such as synthesis, place and route, Static Timing Analysis (STA), verification, or power analysis. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience in block/subchip level PnR for complex SoC. Experience with multiple-cycles of SoC in ASIC design. Experience with scripting languages such as Perl, Python, or Tcl. Experience with layout verification and design rules. Experience in IP integration (e.g., memories, IO's and Analog IP) with the knowledge of semiconductor device physics and transistor characteristics. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a System on a Chip (SoC) Physical Design Engineer, you will collaborate with Register-Transfer Level (RTL), Design for Testing (DFT), Floorplan, and full-chip Sign off teams. Additionally, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Participate in the Physical Design of blocks for complex Tensor Processing Unit (TPU) chips. Contribute to the design and closure of the subchip and individual blocks from Register-Transfer Level-to-Graphic Design System . Collaborate with RTL/Design and Product Development teams to achieve the best Power Performance Area (PPA) possible. This includes conducting feasibility studies for new micro-architectures as well as optimizing runs for best Quality of Results (QoR). Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr

Apply Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Qualifications PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. Academic, educational, internship, or project experience with physical design. Preferred qualifications Experience in scripting using Languages like Python, Tcl, Perl. Proficiency in fundamental SoC architecture and hardware description languages such as Verilog, facilitating effective collaboration with logic design teams to resolve timing issues. Knowledge of fundamental VLSI and physical design principles, including expertise in semiconductor device physics and transistor structures (e.g., finfet, Gate all around). Understanding of Static Timing Analysis(STA), Clock Domain Crossings (CDC), clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis. Understanding of standard cells, SRAMs, power, noise, and IR analysis. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As a Physical Design Engineer, you will collaborate with Register‑Transfer Level (RTL), Design for Testing (DFT), floorplan, and full‑chip sign off teams. Additionally, you will solve technical problems with innovative micro‑architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full‑time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Participate in the physical design of blocks for complex Tensor Processing Unit (TPU) chips. Contribute to the design and closure of the subchip and individual blocks from Register‑Transfer Level‑to‑Graphic Design System (RTL2GDSII). Collaborate with RTL/Design and Product Development teams to achieve the best Power Performance Area (PPA) possible. This includes conducting feasibility studies for new micro‑architectures as well as optimizing runs for best Quality of Results (QoR). Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr

Apply Bachelor's degree in Electrical Engineering or equivalent practical experience. 5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs. Experience with System on a Chip (SoC) cycles. Experience in high-performance, high-frequency, and low-power designs. Preferred qualifications: Master's degree in Electrical Engineering. Experience in coding with System Verilog and scripting with TCL. Experience with VLSI design in SoC or multiple-cycles of SoC in ASIC design. Experience with layout verification and design rules. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team developing SoCs used to accelerate Machine Learning (ML) computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Define and drive the implementation of physical design methodologies. Take ownership of one or more physical design partitions or top level. Manage timing and power consumption of the design. Contribute to design methodology, libraries, and code review. Define the physical design related rule sets for the functional design engineers. Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr

A leading tech company in San Francisco is seeking a Staff Software Engineer for their Google Cloud division. The role demands providing technical leadership and influencing a distributed team on high-impact projects. Candidates should possess a Master's or PhD in Engineering or Computer Science, along with 3 years of technical leadership experience. The position offers a competitive salary range of $197,000-$291,000, along with equity and benefits. Strong proficiency in software development and project management is essential. #J-18808-Ljbffr

A leading technology company in California seeks a Senior Staff Software Engineer to lead high-impact projects and manage distributed engineering teams. This role requires 8+ years of Java or C++ programming experience, strong design and architecture skills, and a background in technical leadership. The successful candidate will be responsible for designing, developing, and enhancing software solutions to meet critical needs. The position offers a base salary of $248,000-$349,000, including bonus, equity, and benefits. #J-18808-Ljbffr

A leading electronic design automation company in California seeks an experienced SoC/ASIC Digital Design Engineer with a strong focus on Design for Test (DFT) methodologies. The ideal candidate will have substantial expertise in scan chain insertion, compression scan technologies, and automatic test pattern generation (ATPG), along with strong problem-solving skills and the ability to work collaboratively in a cross-functional team environment. This is a fantastic opportunity to contribute to essential technology projects. #J-18808-Ljbffr

A leading technology company is searching for a skilled UX Engineer to innovate user experiences across its platforms. You will leverage your extensive front-end development and technical design expertise to create engaging prototypes and user interfaces, impacting millions globally. This position offers a competitive salary range of $224,000-$315,000 plus bonuses and benefits, making it an outstanding opportunity to drive user-centric design at scale. #J-18808-Ljbffr

A leading technology company is seeking a Senior Software Engineer specializing in AI/ML for YouTube. The role demands significant programming experience in Python and C++, along with expertise in machine learning infrastructure. This position offers a salary range of $166,000 to $244,000, inclusive of bonuses and equity. You will contribute to product development, troubleshoot issues, and collaborate across teams, all while working in a dynamic environment that values innovation and diversity. #J-18808-Ljbffr

A leading tech company is seeking a Senior Software Engineer for their AI/ML team in Mountain View, California. The role involves developing next-generation technologies and offers a competitive salary range between $166,000 and $244,000, along with bonuses and equity. Ideal candidates will have extensive experience in programming, particularly in Python or C++, and strong knowledge in machine learning infrastructure. Collaborating with teams on critical projects, the position also demands leadership qualities and a passion for tackling new challenges across the tech stack. #J-18808-Ljbffr

A leading tech company in California seeks a Senior Software Engineer for mobile (iOS) to work on innovative projects at YouTube. You will be responsible for developing and maintaining software solutions, mentoring peers, and tackling complex problems. The ideal candidate will possess strong skills in C++, Objective-C, and Swift, along with significant experience in iOS application development. This full-time position offers a competitive salary range of $166,000-$244,000, plus bonus and equity. #J-18808-Ljbffr

A leading technology company in Mountain View is seeking a Senior Software Engineer focused on AI/ML for YouTube. The role involves writing and testing code, designing recommendation systems, and collaborating with peers. Candidates should have a Bachelor's degree, extensive experience with Python and C++, and experience with machine learning infrastructure. A competitive salary of $166,000-$244,000 along with bonuses and benefits is offered. Join a team committed to innovation and diversity. #J-18808-Ljbffr

A leading global technology company in San Francisco is seeking a Software Engineer III for the Mobile (Android) team. You will design and implement features while collaborating with other teams to enhance Google Wallet's functionalities. The role requires at least 2 years of experience in software development, specifically in Java or Kotlin, as well as expertise in Android application development. The US base salary range for this full-time position is $141,000-$202,000, along with bonuses and benefits. #J-18808-Ljbffr

Are you passionate about enhancing web experiences and pushing browser capabilities? Join us as a Product Engineer and help shape the future of Esri's web offerings. In this role, you'll improve interactive maps and apps, support complex analyses, and enable smarter decision-making. You'll work closely with developers to align requirements, design solutions, manage issues, and create clear documentation while ensuring quality from concept to delivery. Be part of a fast-paced team that builds, tests, and supports the ArcGIS Maps SDK for JavaScript, ArcGIS Online, and ArcGIS Enterprise. Responsibilities Design, develop, test, document, release, and support the ArcGIS Maps SDK for JavaScript (including core API, web components, and libraries) to enhance product quality Collaborate with customers and stakeholders to gather feedback and guide future releases Define customer needs and translate them into product improvements and new designs Create thorough documentation, including API references, code samples, templates, and tutorials Troubleshoot and fix bugs from internal testing and customer reports Stay current with web and browser trends to ensure a modern user experience Commit to continuous learning and evolving with web technologies Dive deep into technical details to inform decisions and drive innovation Requirements 2+ years of experience with web development Experience with HTML, CSS, and JavaScript Experience with JavaScript frameworks, TypeScript and build tools Experience with frontend testing tools like Vitest, Storybook, and Playwright Strong problem-solving and analytical skills Strong presentation skills; ability to effectively communicate design concepts Effective time management and organizational skills Bachelor's in GIS, geography, engineering, computer science, math, or related fields Recommended Qualifications Expertise in online mapping, GIS, and data visualization Proficiency with Web Components Knowledge of accessibility, internationalization, and localization best practices Familiarity with Node.js, GitHub Actions, and DevOps workflows Master's in GIS, geography, engineering, computer science, math, or related fields #LI-Onsite #LI-OH1