InnoGrit jobs

Job DescriptionSalary: DOE Firmware Engineer(entry level) Are you passionate about development and project-based work? Do you like a significant challenge? We offer this and much, much more. Our teams work with cutting-edge NAND SSD controllers and storage systems We are searching for brilliant Software Developers (0-3 years experience) to join our Firmware Development Team at Bay Area site, San Jose, CA. New grad welcomed! We are looking for forward thinkers and critical players who learn, grow, and make your contributions. Firmware Developer technical skills: Good programming capability in C Experience or good understanding of embedded systems Experience or good understanding of PCIe/NAND/SMBus/UART/SPI protocols BS in Computer Science, or EE About Innogrit Corporation Innogrit is transforming data storage with its advanced PCIe Gen 3 and Gen 4 SSD (Solid State Drive) Processors. By delivering unprecedented reliability, performance, and energy efficiency, SSDs based on Innogrits technology unleash the full potential for next generation SSDs using the latest NAND flash memory.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* About Astera Labs Astera Labs (NASDAQ: ALAB) is a pioneering fabless semiconductor company headquartered in Silicon Valley, driving the evolution of AI and cloud infrastructure through purpose-built connectivity solutions. As a leader in rack-scale architecture, Astera Labs is enabling the shift to AI Infrastructure 2.0, where compute is optimized at the rack level to support the demands of next-generation workloads. Our portfolio includes high-performance silicon, software, and system-level solutions that address critical bottlenecks in data movement across compute, memory, and networking domains. Leveraging technologies such as PCIe , CXL , Ethernet, and UALink™, we deliver scalable, interoperable platforms that empower hyperscale data centers to deploy AI and cloud services with greater efficiency and flexibility. We are committed to open standards, software-defined architectures, and continuous innovation as we work to expand our product offerings and customer engagements. We foster a collaborative environment for professionals passionate about solving complex challenges and shaping the future of intelligent infrastructure. Role Overview Astera Labs is seeking a strategic and proactive Senior Principal Category Sourcing Manager to lead sourcing initiatives across Corporate Services & Operations, a category that spans a broad and dynamic range of enterprise needs. This includes sourcing for professional services (legal, finance, marketing, recruiting, and engineering consulting), IT infrastructure and equipment, corporate software tools, facilities and real estate services, and workplace operations. This role is foundational to enabling enterprise-wide operations and supporting business continuity, compliance, and employee productivity. You will be responsible for developing and executing category strategies, managing supplier relationships, and driving high-impact negotiations across a diverse set of internal stakeholders and external partners. You'll also play a key role in vendor consolidation, spend governance, and process optimization to support Astera Labs' rapid growth and evolving business needs. A Day in the Life In this role, you'll be at the center of enabling Astera Labs' enterprise operations. Your day is shaped by dynamic interactions across legal, finance, IT, and facilities teams, as you help translate business needs into sourcing strategies that drive efficiency, scalability, and value. You'll navigate a diverse landscape of suppliers-from strategic consulting firms and software providers to facilities and real estate partners-building relationships and shaping agreements that support both immediate needs and long-term growth. Whether you're refining a framework for professional services sourcing, evaluating new IT platforms, or exploring ways to streamline corporate spend, your work will influence how the company operates and scales. This role offers a unique blend of strategic ownership and cross-functional engagement, where your decisions directly impact business continuity, employee experience, and operational excellence. Key Responsibilities Develop and execute sourcing strategies for corporate categories including professional services, IT infrastructure, facilities, real estate, and enterprise software. Lead supplier selection, negotiation, and contract execution including NDAs, MSAs, SOWs, and licensing agreements. Partner with internal stakeholders to align sourcing initiatives with business needs and operational goals. Drive vendor consolidation and strategic partnerships to improve service levels and reduce cost. Streamline procurement processes for high-volume, low-value purchases and support spend governance improvements. Monitor supplier performance, compliance, and service-level agreements (SLAs). Analyze market trends, cost structures, and supplier capabilities to inform sourcing decisions. Collaborate with logistics and procurement operations teams to support freight rate negotiations and global sourcing initiatives. Basic Qualifications Bachelor's degree in Business, Supply Chain, Finance, or related field. 7+ years of experience in indirect sourcing, procurement, or supplier management across corporate categories. Proven experience negotiating contracts for professional services, IT infrastructure, facilities, and enterprise tools. Strong understanding of procurement operations, vendor management, and spend governance. Demonstrated ability to lead complex negotiations and manage supplier relationships across global teams. Preferred Qualifications Master's degree in Business, Supply Chain Management, or related discipline. Experience with sourcing frameworks for legal, consulting, and engineering services. Familiarity with corporate IT tools, SaaS licensing models, and facilities management. Strong analytical, financial modeling, and contract management skills. Excellent communication and stakeholder engagement across technical and business functions. Why Join Us? Be part of a high-growth, innovation-driven company at the forefront of AI and cloud infrastructure. Work with diverse teams and strategic partners across the enterprise. Enjoy a collaborative culture that values ownership, agility, and continuous improvement. Competitive compensation, equity, and benefits package. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Job Description: We are seeking an experienced and hands-on IC Packaging Technologist to lead and innovate in the development of high-performance, high-speed, and advanced IC package solutions. The ideal candidate will bring a proven track record of deep technical contributions in 2.5D/3D integration, chiplet technology, fan-out wafer-level-packaging (e.g., FOWLP/FoCoS/Info), and heterogeneous integration. The successful candidate will lead strategic roadmap execution and scale innovative package solutions into production through close collaboration with OSATs, foundries and key suppliers Basic Qualifications: M.S. or Ph.D. in Electrical Engineering, Materials Science, or related discipline. 10+ years of experience in IC packaging development and NPI for high-speed SerDes and high-performance SoCs, ASICs, or memory products Deep hands-on expertise with FCBGA, fc CSP, co-packaged optics (CPO), and 2.5D/3D integration technologies such as CoWoS, RDL and silicon interposers, and chiplet-based architectures (e.g., BoW, UCIe); along with experience in fan-out wafer-level packaging (FOWLP/WLFO). Strong understanding of packaging material selection, substrate stack-up, bump/RDL design, and DFM for advanced nodes Entrepreneurial, open-minded behavior and hands-on work ethic with the ability to prioritize a dynamic list of tasks. Required Experience: Led multiple end-to-end advanced packaging NPI programs, from concept definition, pathfinding, design, supplier engagement, process development, and successful transition to HVM. Experience in high-speed SerDes IC package development, including interfaces such as PCI Express (PCIe) Gen4/Gen5/Gen6, CXL (Compute Express Link), and other multi-gigabit transceiver protocols, as well as devices such as retimers, switches, and PHYs operating at data rates up to 224G/448G PAM4. Experience defining RDL and bump architectures to enable die-to-die chiplet integration using interconnect standards such as BoW (Bunch of Wires) and UCIe (Universal Chiplet Interconnect Express). Demonstrated ability to lead collaboration with foundries (e.g., TSMC), OSATs, and substrate suppliers for collaborative package technology development. Deep understanding of mechanical (e.g., warpage, CTE mismatch), thermal (e.g., heat dissipation, TIM), and electrical (e.g., parasitics, signal integrity) design trade-offs in advanced package development, with a proven ability to deliver robust and manufacturable packaging solutions. Deep understanding of the technology landscape, cost drivers, and market trends influencing IC packaging innovation. Demonstrated ability to operate cross-functionally across design, product/test engineering, operations, reliability, marketing, and customer-facing teams. Preferred Experience: SI/PI knowledge is a plus: SI/PI concepts, S-parameter extraction, and PDN optimization using HFSS, SIwave, or Ansys Designer Knowledge of EDA design tools is a plus: Cadence Allegro/APD, Altium, etc. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Contribute to micro-architecture designs for state-of-the-art high-speed low-power digital IPs. Implement design modules using hardware description language (HDL). Design schemes for multi-clock domain crossing and synchronization. Drive OVM/UVM design verification and support FPGA engineers for early prototyping. Execute RTL-to-GDS development flow, including synthesis, schematics design, and supervising custom layout. Check timing closure, and analyze the performance/power/area of designed IPs. Support IP integration to SoC, including soft-IP RTL integration and hard-IP GDS macro integration. Perform post-layout Hspice simulation to characterize the designed circuit. Assist with test program development, chip bring-up, validation, and production maturity. Job requirement Masters degree in Electrical Engineering/Computer Science. 6 months experience as an ASIC Design Engineer or Verification Design Engineer. Proficient with Verilog, SystemVerilog, and Python or Perl. Strong knowledge of micro-architecture design, function modeling, RTL coding, and SoC Integration. Good at multi-clock domain designs, timing analysis, and optimization. Experience in SystemVerilog OVM/UVM, synthesis, mixed-signal circuit schematics design, and layout design. Able to proactively take on responsibilities and competent to work in a start-up environment. About Innogrit Corporation Innogrit is transforming data storage with its advanced PCIe Gen 3 and Gen 4 SSD (Solid State Drive) Processors. By delivering unprecedented reliability, performance, and energy efficiency, SSDs based on Innogrits technology unleash the full potential for next generation SSDs using the latest NAND flash memory.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Are you passionate about driving business growth for the next generation of data infrastructure with hyperscale and AI platform providers - through customer intimacy, deal negotiation and commercial strategies? We are seeking a highly proficient and experienced business manager to join our team at Astera Labs. As a key member of our business management team, you will work closely with customers, sales, product marketing, operations and other internal cross-functional teams to accelerate revenue and execute on our deal pipeline for critical opportunities. With high visibility to the executive team and customers, this role requires strong leadership and communication skills, and a blend of commercial expertise and customer insight across our product portfolio. Based in San Jose, CA, this position requires an in-person presence with travel to customers. Key Responsibilities Lead customer deal pipeline: Work closely with sales and lighthouse customers secure strategic design-wins and progress pipeline towards design-in and conversion to contracts and purchase orders. Own commercial frameworks: Set, align and approve pricing and commercial terms for key deals and establish consistent pricing strategies and methodologies across products in partnership with product marketing teams. Facilitate customer and segment playbooks: Leverage commercial, market and product expertise to support strategy definition and partner with sales to develop playbooks for key customers, segments and regions - covering key elements such as customer insights, relationship mapping, competitive analysis, win/loss analysis solution positioning and negotiation plans. Support business process innovation: Work closely with business functions to enable the next phase of scale through identifying, prioritizing and executing key operational improvements such as new operating procedures, tools or organizational clarity. Qualifications Bachelor's degree in engineering, computer science or business/marketing 10+ years of experience in, product marketing, sourcing, supply chain, operations, sales or other customer-facing product roles within the semiconductor industry Strong strategic thinking and analytical skills, with the ability to translate customer pain points into innovative solutions (deals, partnerships, or product adoption) Proven track record of negotiating and influencing customers, leading to key agreements, contracts or purchase orders Excellent communication and presentation skills, with the ability to articulate complex technical concepts in a clear and compelling manner Broad understanding of high-speed protocols (PCIe is required; Ethernet, CXL, and other protocols are a plus) and system architectures used in cloud and AI infrastructure Results-oriented mindset with a focus on driving measurable impact and achieving business objectives Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment Willingness to travel as needed for customer meetings, industry events, and trade shows We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You'll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms. Basic qualifications Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Masters is preferred. ≥5 years' experience verifying and validating complex SoC for Server, Storage, and Networking applications. Knowledge of industry-standard simulators, revision control systems, and regression systems. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision. Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! Authorized to work in the US and start immediately. Required Experience Experience with full verification lifecycle based on System Verilog/UVM/C/C++. Proven ability to mix and deploy hybrid techniques as in both directed and constrained random. Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus. Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures. Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out. Preferred Experience Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc. Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Experience with directed test based methodologies, cache verification and formal methods. The base salary range is USD 147,000.00 - USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* About Astera Labs Astera Labs (NASDAQ: ALAB) is a pioneering fabless semiconductor company headquartered in Silicon Valley, driving the evolution of AI and cloud infrastructure through purpose-built connectivity solutions. As a leader in rack-scale architecture, Astera Labs is enabling the shift to AI Infrastructure 2.0, where compute is optimized at the rack level to support the demands of next-generation workloads. Our portfolio includes high-performance silicon, software, and system-level solutions that address critical bottlenecks in data movement across compute, memory, and networking domains. Leveraging technologies such as PCIe , CXL , Ethernet, and UALink™, we deliver scalable, interoperable platforms that empower hyperscale data centers to deploy AI and cloud services with greater efficiency and flexibility. We are committed to open standards, software-defined architectures, and continuous innovation as we work to expand our product offerings and customer engagements. We foster a collaborative environment for professionals passionate about solving complex challenges and shaping the future of intelligent infrastructure. Role Overview Astera Labs is seeking a hands-on and detail-oriented Logistics Operations Specialist to support daily shipping, receiving, and logistics coordination at our San Jose corporate site, while also contributing to global shipping operations. This role is essential to ensuring the smooth and timely movement of goods across corporate and customer locations. In addition to executing core logistics tasks, this role will support process improvement initiatives aimed at scaling logistics operations, improving accuracy, and enhancing service levels. The ideal candidate is proactive, organized, and eager to contribute to both tactical execution and operational efficiency. A Day in the Life Your day will involve coordinating inbound and outbound shipments, preparing documentation, and working with carriers to ensure timely delivery. You'll be the go-to person for receiving packages, staging materials, and resolving shipping issues. Alongside your daily tasks, you'll help identify opportunities to improve workflows-whether it's refining documentation practices, streamlining vendor coordination, or supporting system upgrades. You'll collaborate with internal teams and external partners to keep logistics running smoothly, while contributing ideas and feedback that help the team scale with the company's growth. Key Responsibilities Execute daily shipping and receiving operations at the San Jose corporate site. Prepare and process shipping documentation including labels, packing slips, and bills of lading. Coordinate with carriers and vendors to ensure timely and accurate deliveries. Support global logistics operations including international shipments and customs documentation. Identify and contribute to process improvement initiatives across logistics workflows. Collaborate with internal teams to fulfill material requests and troubleshoot shipping issues. Assist in implementing logistics systems and tools to improve operational efficiency. Basic Qualifications Associate degree or technical certification with 4+ years of experience in logistics, shipping/receiving, or warehouse operations. Familiarity with shipping platforms (e.g., FedEx, UPS, DHL) and basic documentation. Ability to lift and move packages and materials as needed. Strong attention to detail and organizational skills. Effective communication and teamwork across departments. Preferred Qualifications Bachelor's degree in Logistics, Supply Chain Management, or a related field. Experience with international shipping and customs documentation. Familiarity with logistics systems such as Oracle or similar platforms. Experience supporting logistics process improvements or system implementations. Why Join Us? Be part of a fast-growing, innovation-driven company supporting the future of AI and cloud infrastructure. Work in a hands-on role that directly supports global operations and product movement. Enjoy a collaborative culture that values precision, ownership, and continuous improvement. Competitive compensation and benefits package. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Job Description: As an Astera Labs New Product Introduction (NPI) / Electrical Product (EPE) Engineer, you will be part of a Hardware Engineering team that designs and manufactures products featuring Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server, and network OEMs. In this role, you will be responsible for NPI-taking products from the design stage to volume manufacturing. You will work closely with designers, manufacturing teams, suppliers, and contract manufacturers to ensure that hardware product test flows are properly introduced, released to manufacturing, and supported past production. This role will also require engagement in activities such as Bill of Materials (BOM) management, Design for Manufacturability (DFM), validation, and process documentation. Additionally, the EPE is expected to drive continuous improvements in manufacturing test flow, product yield, and cost efficiency. While your focus will be on NPI/EPE, you will have the opportunity (and be expected-depending on your experience) to contribute to adjacent areas such as test engineering, validation, and quality. Being part of a growing manufacturing team, we welcome the diverse experience you bring. Key Responsibilities Own manufacturing NPI/EPE activities, ensuring successful product transition from design to volume manufacturing. Manage PCBA BOM structuring and risk assessment to improve manufacturability and minimize changes late in the cycle. Lead BOM release through ECO and PLM tools, ensuring alignment with cross-functional teams. Analyze end-to-end manufacturing capacity and work with operations teams for future planning. Collaborate with cross-functional partners on developing Contract Manufacturer (CM) capabilities to prototype, launch, and transition products to high-volume production. Identify and mitigate contract manufacturer gaps in capabilities, process readiness, and documentation. Work with factory and engineering teams to troubleshoot failures, perform root cause analysis, and implement corrective actions. Participate in and help define key manufacturing processes, including NPI, product engineering, validation, and quality control. Drive improvements in SMT process flow, quality control, and inline inspections. Develop clear, precise manufacturing instructions, rework, and deviation documentation. Work cross-functionally to understand and resolve issues throughout product lifecycle with emphasis in hardware design and manufacturing. Basic Qualifications 5+ years of experience in NPI/EPE roles. Strong academic and technical background in electrical engineering or electronic manufacturing. Bachelor's in EE or equivalent experience required. Minimum of 5 years' experience in test engineering or electronics manufacturing. Entrepreneurial, open-minded behavior with a strong "customer-first" mindset. Ability to travel to CMs as needed to support production ramp-up and troubleshooting. Required Experience Strong understanding of high-tech manufacturing processes, NPI activities, and product development lifecycle. Experience working with off-shore contract manufacturers. Track record of successfully launching complex electronic products. Demonstrated ability to analyze and optimize manufacturing test data to improve yields and efficiency. Experience with DFM, Design for Testability (DFT), and Design for Assembly (DFA) methodologies. Bill of Material (BOM) structuring and risk management experience with PLM tools (e.g., Arena, Agile). Strong debugging experience for hardware design and production failures. Root cause analysis of contract manufacturing issues. Experience implementing process documentation and manufacturing best practices. Preferred Experience Familiarity with optical/electrical networking module manufacturing and testing (e.g., SFP+, QSFP, OSFP), data center class products such as servers, network switches, modular chassis, and/or PCIe add-in cards SMT process improvement and quality control methodologies. Data analysis and reporting using Python. Ability to assess and close Contract Manufacturing gaps in capability. Proficiency with EE design tools, including schematic capture and PCB layout (Cadence, Altium, etc.). Technical writing experience for generating clear and precise manufacturing documentation. Exposure to ASIC/silicon development and hardware validation processes. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* About Astera Labs Global leader in purpose-built connectivity solutions for AI and cloud infrastructure Pioneering software-defined architecture that is scalable and customizable PCIe , CXL , and Ethernet semiconductor-based solutions to solve data, memory, and networking bottlenecks Trusted relationships with hyperscalers and the data center ecosystem Are you passionate about driving new architectures with the world's leading AI platform providers and hyperscalers in order to drive the successful adoption of semiconductor-based solutions for AI and cloud infrastructure? Are you passionate about driving strategic growth through impactful corporate development initiatives in the AI and cloud infrastructure space? We are seeking a Senior Manager of Corporate Development to lead and support strategic transactions including acquisitions, strategic partnerships, and investments. This role will report to the Head of Corporate Development and work closely with cross-functional teams including engineering, product management, and business and executive leadership to identify and evaluate opportunities that align with Astera Labs' long-term growth strategy. You will be responsible for conducting market research, opportunity sizing, competitive analysis, and build/buy/partner evaluations. You will also lead financial modeling, valuation analysis, and develop executive presentations to support strategic decision-making. Key Responsibilities Define and continually enhance the company's strategy to acquire new business opportunities at both a high level and in-depth with a specific focus on our leading hyperscaler customers and AI platform partners Lead and support corporate development transactions through all phases of the transaction lifecycle. Research adjacent and new market opportunities, including opportunity and market sizing, target landscaping, and competitive analysis. Partner with business and engineering teams to evaluate opportunities to address strategic gaps and conduct build/buy/partner analysis. Conduct detailed financial analyses including valuation and pro forma modeling to assess deal alignment and investment needs. Develop presentation materials to provide recommendations to the executive team and board. Collaborate with PMO and broader cross-functional teams to drive diligence and validate key assumptions and value drivers. Support post-merger integration to help ensure long term value capture. Qualifications Bachelor's degree in Electrical Engineering, Computer Science, Business Administration, Economics, or related field; MBA preferred 10+ years of experience in strategy, corporate development, investment banking, private equity, venture capital, or related roles within the semiconductor or high-tech industry or financial services. Experience leading strategic transactions and working with executive leadership. Strong analytical skills with experience in valuation, financial modeling, and strategic analysis. Excellent communication and presentation skills with the ability to convey complex concepts clearly. Proven ability to collaborate effectively within an organization and drive cross-functional initiatives. Results-oriented mindset with a focus on achieving business objectives. Willingness to travel as needed for customer meetings, company training, industry events, and conferences. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Role Overview As a Distinguished Product Quality Engineer, you will be responsible for ensuring the quality and reliability of Astera Labs' advanced high-speed (SerDes PAM4 and optical-integrated) semiconductor products across their lifecycle - from design through high-volume semiconductor manufacturing. You will be the primary quality interface for integrated circuit (IC) NPI-related activities, including assessing test coverage, design quality risks, and other NPI quality considerations. This NPI role will also lead the development and implementation of IC diagnostic test strategies, collaborate in defining diagnostic coverage metrics, and work with internal engineering teams to enable robust debug methodologies across leading-edge process technologies (16nm to Key Responsibilities Driving Product Quality Engineering: Work with operations, firmware, and other internal engineering teams to drive product quality improvements both as part of NPI activities and volume manufacturing. This role will participate in various NPI engineering reviews to ensure exit criteria are met, new product issues and learnings are addressed, and production issues are driven to root cause. Work with the operations engineering teams to build data systems and infrastructure to eliminate outliers, predict quality trends, and identify product quality opportunities that will improve customer outcomes. Develop signature analysis techniques to identify systemic root causes by leveraging advanced AI and/or ML techniques where appropriate. Leading NPI Quality-Related Validation & Issue Debugging: Lead the debugging of complex hardware, firmware, and software issues as part of quality team activities during NPI and high-volume production, leveraging diagnostic hooks and advanced debug tools. Develop and maintain automated diagnostic tools to scale and drive reuse across multiple product families. Partner with operations engineering to improve diagnostic efficiency, reduce overkill/retest, and improve product yield and quality. Integrate diagnostics into silicon lifecycle management, firmware release, and reliability tracking to proactively detect degradation or field reliability risks. Interoperability & System-Level Support: Work with field, firmware, and internal engineering teams to ensure interoperability, diagnostic transparency, and robust field debug capability. Diagnostic Test Development: Define and drive the deployment of diagnostic test plans, fixtures, tools, and methodologies needed for fault isolation of customer returns in PCIe, CXL, UCIe, Ethernet, and other high-speed switching products. Fan out the most successful tools for broader application in high-volume manufacturing and troubleshooting of NPI (New Products) qualification failures or field application issues. Embedded Silicon Agent Champion: Drive the external selection or internal development of embedded silicon agents to monitor temperature, voltage, noise, process, timing, etc., at the block level on-chip. Work with design teams on implementation. Collaborate with validation and design teams to debug these features in the lab during the post-silicon phase. Partner with firmware teams to leverage these features for real-time adaptive behavior. Partner with software teams to process the data and create accessible and actionable diagnostic conclusions. Design DFT Review: Work with design, operations engineering, and system validation teams to drive early Design-for-Testability (DFT) and diagnostic capabilities with design and product engineering teams. Coordinate block-by-block-level reviews to ensure no gaps in coverage and that all prior lessons learned are applied. Advanced Packaging Diagnostics: Develop diagnostic methodologies for MCM, 3DIC, and optical interconnect packages, including die-to-die and heterogeneous integration interfaces needed to diagnose, isolate, and ensure high-quality products. Skills and Experience Deep experience with digital and SerDes high-speed protocols (PCIe Gen5/Gen6, CXL, UCIe, Ethernet/SerDes) and system-level validation methodologies. Direct and deep experience working with embedded silicon diagnostic agents. Experience working with engineering teams creating product characterization and test plans, test programs, and collaborating with the greater engineering community to obtain and analyze data across process, voltage, and temperature to evaluate semiconductor products. Hands-on experience with lab debug tools (protocol analyzers, oscilloscopes, BERTs, error injection frameworks). Proficiency in scripting and software development (Python, C/C++, Java, or similar) for diagnostic automation and data analysis. Proven ability to analyze complex test data, identify root causes, and implement systemic solutions. Familiarity with semiconductor test flows (ATE, system-level test, characterization, production validation). Experience with advanced packaging technologies (MCM, 3DIC, optical) and their diagnostic/test challenges. Strong communication skills for collaborating across design, product, test, and customer teams. Demonstrated ability to influence cross-functional decisions and drive quality improvements at the organizational level. Preferred Qualifications Minimum of 5 years of experience leading a high-caliber product engineering team. Minimum of 10 years within a product or diagnostics engineering team with successful deployment of semiconductor devices into production. Strong academic/technical background in electrical engineering; Bachelor's required, Master's preferred. Experience with diagnostic firmware and test development methodologies. Knowledge of advanced techniques for anomaly detection in diagnostic/test data. Track record of leadership in new product introduction (NPI) for complex, high-speed semiconductor products. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Position Summary As a key member of the Sales team, you will be entrusted with strategic ownership of hyperscale customer accounts. This role is ideal for a results-driven professional who excels in dynamic environments and is motivated to expand their impact within a high-performing organization. You will drive revenue growth, build deep customer relationships, and act as a catalyst for scaling team success-taking initiative, anticipating needs, and executing with precision. In addition to delivering on current revenue goals, you will be responsible for proactively creating and building a robust pipeline of opportunities, ensuring we are well-positioned to capture future revenue targets and sustain long-term growth. Success in this role means not only achieving ambitious targets but also proactively expanding responsibilities and influence across the organization. Responsibilities Take ownership of hyperscale customer accounts, driving strategic engagement and growth. Proactively identify opportunities to scale processes, expand responsibilities, and support the sales team's vision for organizational growth. Operate with agility and a sense of urgency, consistently delivering results in fast-paced situations. Serve as a trusted partner to both customers and internal stakeholders, representing the highest standards of professionalism. Demonstrate exceptional accountability, initiative, and follow-through on complex projects. Collaborate cross-functionally to ensure seamless execution and alignment with company goals. Mentor and inspire peers, fostering a culture of achievement and continuous improvement. Traits & Competencies Relentless drive for results and continuous improvement. Strategic thinker with the ability to anticipate challenges and opportunities. High emotional intelligence and adaptability. Strong sense of ownership and accountability. Ability to thrive in ambiguity and rapidly changing environments. Exceptional communication and influence skills. Entrepreneurial mindset with a bias for action. Qualifications Bachelor's degree (Engineering preferred); Master's degree is a plus 5-8 years' experience in semiconductor or datacenter/connectivity sales or field roles Proven track record of winning complex SoC/silicon design wins Strong network within cloud service providers and OEMs Exceptional leadership, communication, and project management skills Entrepreneurial mindset with a customer-first attitude Preferred Qualifications Experience selling [specific products or services, e.g., SaaS, hardware, software]. Knowledge of the Silicon Valley tech ecosystem and key players. Experience using CRM software (e.g., Salesforce). We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Overview: Astera Labs Inc. is a fabless semiconductor company that develops purpose-built connectivity solutions to remove performance bottlenecks in compute-intensive workloads such as artificial intelligence and machine learning. To support our rapid growth, we are hiring a Lead IC Package Designer with extensive experience in complex ASIC package design using Cadence APD. Background in SI/PI is a plus. Job Description: As an Astera Labs Lead Package Design Engineer, you will take ownership of package design and layout for Astera Labs' portfolio of connectivity products deployed by the world's leading cloud service providers and server/networking OEMs. You will be responsible for driving package substrate design from definition to tape-out, including performance optimization, design for manufacturing, and sign-off verification. You will also provide technical guidance within the package design team: mentoring junior designers, guiding best practices in APD, reviewing design work for quality and consistency, and working closely with SI/PI, product engineering, and hardware teams to ensure first-pass success. You will also help shape design flows, champion productivity improvements, and represent package design expertise in cross-functional discussions. Basic Qualifications: BS/MS in Engineering (Electrical, Mechanical, Materials Science, Physics, or related field). 8+ years of experience in Cadence APD/SiP with a track record of independently designing and releasing FCBGA/FCCSP packages from concept to tape-out. Proven experience leading package design efforts, reviewing and mentoring other designers, and setting technical directions. Deep understanding of BGA substrate technologies, stackups, design rules, and assembly processes. Familiarity with package reliability, SI/PI, and design sign-off methodologies. Entrepreneurial, open-minded, and hands-on work ethic with the ability to drive multiple priorities in a dynamic environment. Strong collaboration and communication skills to work effectively across functions and influence outcomes. Required Experience: Expert proficiency in Cadence APD/SiP (this is a must have). Able to design large-body BGAs from concept through tape-out with minimal guidance. Strong knowledge of package BOM integration, layer stackup, padstacks, constraint setup (physical and electrical), SMT component design, and optimization based on SI/PI feedback. Experience running and interpreting DRC/DRV/LVS/DFM checks, generating documentation, and releasing Gerbers/artwork. Ability to conduct feasibility studies such as fan-out, mock-ups, and layer/package size reduction. Understanding of package manufacturing flow, supply chain considerations, reliability, and risk management. Technical leadership in driving new APD design flows, methodologies, and automation (working with vendors or through scripting). Preferred Experience: Multi-chip, interposer, 2.5D or heterogeneous package design experience is a plus. Proficiency in scripting languages for design and reporting automation is a plus. The base salary range is $175,750.00 USD - $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Job Description: As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products. You will be working on projects from conception to the final production stage at contract manufacturer. The role requires a strong and broad software background and good understanding of hardware design and manufacturing practices. At the same time we welcome candidates with deep experience in smaller areas with the desire to learn. Depending on your experience, you may be focusing on design/validation or automation/manufacturing. Key Responsibilities Design, implement & test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation. Design, implement & test manufacturing tests to validate mass production of digital boards used in data center networking product Bring-up newly manufactured boards and develop the first level of software. Isolate and perform root-cause analysis of reported failures Support new platform software and hardware features Coordinate with the hardware engineering team on bring-up schedules and feature delivery Participate proactively in design discussions, design review, and project management Work independently as well as in team roles, mentor younger team members Basic Qualifications/Required Experience Bachelor's in CS/CE or equivalent experience. 8+ years of Experience in subset of diagnostic, hardware bring-up, test or manufacturing automation Knowledge of modern software development Proficiency in Python Preferred experience Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing Ability to read schematic/layout System debug experience Embedded programming and good knowledge of OS internals (Linux/Unix) Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming. Experience with DDR5 The base salary range is $203,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Job Summary As a Customer Program Manager (CPM) within the Customer Experience Organization at Astera Labs, you'll play a pivotal role in driving the successful execution of strategic customer programs. Leveraging your technical expertise, business acumen, and exceptional organizational and communication skills, you'll lead engineering and operational activities for design-in, qualification, and release-to-manufacturing (RTM) of our products at key customers. You will mobilize cross-functional “tiger teams” to swiftly resolve production issues and ensure seamless product delivery. This high-impact role is directly tied to achieving critical revenue milestones and customer success. Key Responsibilities Develop a deep understanding of customer success criteria and implement actionable execution plans to meet them Own program planning activities including scheduling, budgeting, risk assessment, resource allocation, and tracking of internal and customer-facing deliverables Act as the single point of contact for program execution, representing the customer's voice within Astera Labs and aligning internal teams with customer objectives Manage delivery of design collateral, firmware, SDK, engineering samples (ES), customer samples (CS), and NPI volume ramp to meet key customer milestones such as EVT, DVT, PVT, Integration Testing, and GA Facilitate regular customer and internal meetings to ensure alignment, transparency, and timely resolution of issues (e.g., Field Failures, RMAs) Drive continuous improvement by capturing customer feedback and ensuring expectations are not just met-but exceeded Maintain technical depth and leadership capabilities to proactively address program and product challenges Job Requirements Bachelors' or Masters' Degree in Electronics/Electrical/Computer Engineering 10+ years of relevant experience in a semiconductor or electronics product company 5+years of experience as a Program Manager, PMP certification is a plus Hands-on experience with optical, PCI-E, switching, memory or data communication products Experience managing customer relationships and communications Working knowledge of hyperscaler/datacenter product development workflows Program management and analytical skills, ability to organize information for internal and external consumption. Proficiency in Microsoft Office tools Excel, Word, PowerPoint, and Outlook; experience with Microsoft Project and other project management tools Ability to lead by influence in a matrixed organization and energize cross-functional teams Decisive and calm under pressure, especially when navigating ambiguity or high-stress situations Able to take timely decisions with limited or incomplete information Willingness to travel to Astera Labs' sites as well as customer locations as required We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. Job Type: Full time (40 hours per week) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Job Description Astera Labs is seeking a Digital Design Engineer to join our ASIC IP & Methodology team. In this role, you will contribute to the front-end design and development of high-performance digital IP blocks, including RTL design, synthesis, and verification. You will gain hands-on ownership of block-level design, integration, and debug, while working closely with senior architects and methodology experts to advance your skills. This position is ideal for engineers who want to expand into full-chip ownership and methodology, while immediately contributing to next-generation connectivity products for AI, Cloud, and Data Center markets. Key Responsibilities Develop micro-architecture and RTL implementation for digital IP blocks. Perform synthesis, lint, CDC, and static timing analysis. Own block-level design and verification (simulation, UVM-based flows). Integrate IP blocks into larger ASIC systems and collaborate across teams to ensure timing and functionality. Support silicon bring-up and debug of first silicon. Contribute to design methodology improvements, automation, and best practices. Work closely with senior architects to grow toward full-chip design ownership. Basic Qualifications: B.S. in Electrical or Computer Engineering (M.S. preferred). 5 years of ASIC or SoC design experience in Server, Storage, Networking, or related domains. Proficiency in RTL design, synthesis, and timing closure. Familiarity with high-speed protocols (PCIe Gen3+, Ethernet, DDR, NVMe, USB, etc.). Hands-on experience with EDA toolchains (Synopsys, Cadence). Exposure to DFT concepts (scan insertion, testability). Familiarity with UVM-based DV and block-level verification. Experience with deep sub-micron CMOS nodes (≤28nm). Preferred Qualifications Prior involvement in silicon bring-up and debug. Scripting experience (Python, Perl, TCL, or equivalent). Understanding of system-level integration (SoC/ASIC). Background in PCIe or Ethernet switch/retimer products. Strong team-oriented mindset, with a drive to learn and take on increasing ownership. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* At Astera Labs, we seek motivated Senior Principal Signal and Power Integrity Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. This position will be onsite. Basic Qualifications Strong academic/technical background in electrical engineering; Bachelor's is required; Master's preferred. 10+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications. 10+ years of hands-on high-speed SI/PI design, simulation, and measurement experience. Have a proven track record with defining hardware system constraints and high-speed technology roadmaps. Cross-functional design mentality with the silicon design community to develop systems. Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment. Proven track record solving problems independently, preferably as a tech lead. Entrepreneurial, open-minded behavior, and can-do attitude. Authorized to work in the US and start immediately. Required Experience Familiar with SI and PI design challenges for PCIe Gen5/6 and/or 200/400G Ethernet PCB and interconnects 2D and 3D simulation experience with Cadence/Ansys/ADS/etc. toolsets EM modeling of connector structures High-speed SERDES channel simulation, and equalization Expertise in multi-level and NRZ signaling, COM, BER, jitter analysis Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc. Working knowledge of PCB fabrication limits and trade-offs PI experience a strong plus. Familiar with industry-standard such as PCISIG, and IEEE802.3, especially Electrical sections. Working knowledge of key, high-speed design blocks such as PLLs, DFE, Tx EQ Proficiency in using high-speed lab equipment such as BERT, Oscilloscope, and VNA Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment. Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $203,000 USD - $230,000 USD for Principal level, and $237,500 USD - $250,000 USD for Senior Principal level. The actual level is to be determined by the years of experience and interview outcome. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure? We are seeking a highly technical and experienced product manager to join our team at Astera Labs. As a key member of our product management team, you will work closely with customers, product marketing, engineering and other internal cross-functional teams to define and deliver competitive silicon, hardware and software solutions. This is a unique opportunity to play a pivotal role in the success of our Aries PCIe Retimer portfolio. We are scaling our Aries product management team to support our worldwide customers, offering ample opportunities for growth and advancement within the product team. Based in San Jose, this position requires an in-person presence with travel to customers. Key Responsibilities Own product definition: Define detailed product requirements and prioritize features, enhancements, and bug fixes based on business goals and customer feedback. Lead product planning: Work closely with product marketing to translate product strategy into executable product plans and collaborate with Astera Labs cross-functional teams to drive products from ideation to launch. Lead customer technical engagement: Work closely with lighthouse customers to translate their needs to competitive product requirements and secure new design wins throughout the product lifecycle. Support go-to-market: Leverage technical and product expertise to support product marketing and corporate marketing teams on go-to-market planning and execution, sales enablement, competitive analysis, and product positioning. Qualifications Deep understanding of high-speed protocols (PCIe is required; Ethernet, CXL, and other protocols are a plus) and system architectures used in cloud and AI infrastructure 10+ years of experience in product management, applications engineering or other technical product roles within the semiconductor industry Proven track record of defining and launching successful semiconductor products Strong strategic thinking and analytical skills, with the ability to translate customer pain points into competitive products Excellent communication skills with the ability to articulate complex technical concepts in a clear and compelling manner Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment Experience working with customers and partners to understand their needs and drive product definition Willingness to travel as needed for customer meetings, industry events, and trade shows If you are passionate about driving innovation and shaping the future of data center connectivity through world-class products, we encourage you to apply. Join Astera Labs in unleashing the potential of cloud and AI infrastructure! We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Job Description: We are seeking an experienced and hands-on Lead Product Engineer to lead and develop next generation high-speed, high performance and low power semiconductor products in advanced process node. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives. Basic Qualifications: Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation). Experience in working with PCIe Gen3 and above. Have gone through at least one cycle of full product development life cycle. Strong academic/technical background in electrical or computer engineering; Bachelor's is required; MS preferred. Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT. Digital and analog circuit level understanding for DUT. Excellent team player with great communication skills. Professional attitude with the ability to prioritize a dynamic list of multiple tasks. Required Experience: Hands on experience with using the Advantest 93k ATE platform with specific skills updating ATE test programs for wafer sort and final test solutions. Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), etc. and/or memory interfaces such as (LP) DDR5/4. Detailed mindset monitoring device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs. Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions. Energetic work mindset meeting the demands of shipping quality parts to Astera Labs' customers through the manufacturing stage of development. Preferred Experience: Working with silicon validation teams to ensure device performance meets production requirements. Firmware development in C/C++, scripting in Python, or other equivalent programming experience. Hands on experience in product/package qualification. The base salary range is USD 175,750.00 - USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* As a Senior Hardware Electrical Validation Engineer you will join the Hardware Electrical Validation team, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others. The ideal candidate for this role demonstrates expertise in the field, possesses relevant experience, and "do what it takes" - able and willing to assist and contribute wherever necessary to solve problems. Key Responsibilities Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out. Develop comprehensive hardware electrical validation plans using correct test methods and processes. Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board. Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc. Rework components on the PCBAs to unblock debugging activities. Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams. Support hardware activities in auxiliary teams - Post-Silicon Electrical Validation, Product Apps, System Validation, FAEs, etc. Support the new designs using knowledge of existing products to de-risk new features and requirements. Self-informed of new industry test standards and equipment to introduce modern testing methodologies. Specify test equipment, develop test fixtures, help improve hardware lab functions. Required Skills Demonstrated strong skills in electrical engineering, circuit analysis and debug Bachelor degree in EE with 3+ years of experience in hardware test or design Strong understanding of electronic circuits and comprehensive testing Ability to produce test description from a schematic design, and execute and document results Demonstrated knowledge of the full hardware product lifecycle from Project Kick-off to RTM Lab equipment for hardware test - oscilloscopes, e-loads, VNA, TDR, environmental chambers, etc. Automating lab equipment to optimize test processes, Python preferred Preferred Skills PLM, Arena or equivalent Measurements of high-speed interfaces - PCIe, DDR, 25/50G/100G SERDES, etc. EMI/EMC compliance Technical writing skills - ECOs, Bug Reports, Rework WIs, MCOs, etc. Understanding of the ASIC/silicon product development process Base salary range is $147,000 USD-$195,000 USD, and will be determined based on the candidate's capabilities and employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.