InnoGrit jobs in San Jose, CA - 40 jobs

Contribute to micro-architecture designs for state-of-the-art high-speed low-power digital IPs. Implement design modules using hardware description language (HDL). Design schemes for multi-clock domain crossing and synchronization. Drive OVM/UVM design verification and support FPGA engineers for early prototyping. Execute RTL-to-GDS development flow, including synthesis, schematics design, and supervising custom layout. Check timing closure, and analyze the performance/power/area of designed IPs. Support IP integration to SoC, including soft-IP RTL integration and hard-IP GDS macro integration. Perform post-layout Hspice simulation to characterize the designed circuit. Assist with test program development, chip bring-up, validation, and production maturity. Job requirement Masters degree in Electrical Engineering/Computer Science. 6 months experience as an ASIC Design Engineer or Verification Design Engineer. Proficient with Verilog, SystemVerilog, and Python or Perl. Strong knowledge of micro-architecture design, function modeling, RTL coding, and SoC Integration. Good at multi-clock domain designs, timing analysis, and optimization. Experience in SystemVerilog OVM/UVM, synthesis, mixed-signal circuit schematics design, and layout design. Able to proactively take on responsibilities and competent to work in a start-up environment. About Innogrit Corporation Innogrit is transforming data storage with its advanced PCIe Gen 3 and Gen 4 SSD (Solid State Drive) Processors. By delivering unprecedented reliability, performance, and energy efficiency, SSDs based on Innogrits technology unleash the full potential for next generation SSDs using the latest NAND flash memory.

Technical Lead Design Verification Engineer San Jose, CA Astera Labs (NASDAQ: ALAB)provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ****************** . We are looking fora Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You'll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms. Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Masters is preferred. ≥5 years' experience verifying and validating complex SoC for Server, Storage, and Networking applications. Knowledge of industry-standard simulators, revision control systems, and regression systems. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision. Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! Authorized to work in the US and start immediately. Required Experience Experience with full verification lifecycle based on System Verilog/UVM/C/C++. Proven ability to mix and deploy hybrid techniques as in both directed and constrained random. Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus. Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures. Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out. Preferred Experience Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc. Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Experience with directed test based methodologies, cache verification and formal methods. The base salary range is USD 147,000.00 - USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. Apply for this job * indicates a required field First Name * Last Name * Preferred First Name Email * Phone Resume/CV Enter manually Accepted file types: pdf, doc, docx, txt, rtf Enter manually Accepted file types: pdf, doc, docx, txt, rtf LinkedIn Profile Website How many years of full-time experience do you have relevant to the role? Select... Are you open to relocation and if so, to what location(s)? * I have reviewed and consented to the privacy policies. Select... #J-18808-Ljbffr

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Job Description: We are seeking an experienced and hands-on IC Packaging Technologist to lead and innovate in the development of high-performance, high-speed, and advanced IC package solutions. The ideal candidate will bring a proven track record of deep technical contributions in 2.5D/3D integration, chiplet technology, fan-out wafer-level-packaging (e.g., FOWLP/FoCoS/Info), and heterogeneous integration. The successful candidate will lead strategic roadmap execution and scale innovative package solutions into production through close collaboration with OSATs, foundries and key suppliers Basic Qualifications: M.S. or Ph.D. in Electrical Engineering, Materials Science, or related discipline. 10+ years of experience in IC packaging development and NPI for high-speed SerDes and high-performance SoCs, ASICs, or memory products Deep hands-on expertise with FCBGA, fc CSP, co-packaged optics (CPO), and 2.5D/3D integration technologies such as CoWoS, RDL and silicon interposers, and chiplet-based architectures (e.g., BoW, UCIe); along with experience in fan-out wafer-level packaging (FOWLP/WLFO). Strong understanding of packaging material selection, substrate stack-up, bump/RDL design, and DFM for advanced nodes Entrepreneurial, open-minded behavior and hands-on work ethic with the ability to prioritize a dynamic list of tasks. Required Experience: Led multiple end-to-end advanced packaging NPI programs, from concept definition, pathfinding, design, supplier engagement, process development, and successful transition to HVM. Experience in high-speed SerDes IC package development, including interfaces such as PCI Express (PCIe) Gen4/Gen5/Gen6, CXL (Compute Express Link), and other multi-gigabit transceiver protocols, as well as devices such as retimers, switches, and PHYs operating at data rates up to 224G/448G PAM4. Experience defining RDL and bump architectures to enable die-to-die chiplet integration using interconnect standards such as BoW (Bunch of Wires) and UCIe (Universal Chiplet Interconnect Express). Demonstrated ability to lead collaboration with foundries (e.g., TSMC), OSATs, and substrate suppliers for collaborative package technology development. Deep understanding of mechanical (e.g., warpage, CTE mismatch), thermal (e.g., heat dissipation, TIM), and electrical (e.g., parasitics, signal integrity) design trade-offs in advanced package development, with a proven ability to deliver robust and manufacturable packaging solutions. Deep understanding of the technology landscape, cost drivers, and market trends influencing IC packaging innovation. Demonstrated ability to operate cross-functionally across design, product/test engineering, operations, reliability, marketing, and customer-facing teams. Preferred Experience: SI/PI knowledge is a plus: SI/PI concepts, S-parameter extraction, and PDN optimization using HFSS, SIwave, or Ansys Designer Knowledge of EDA design tools is a plus: Cadence Allegro/APD, Altium, etc. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Position Summary As a key member of the Sales team, you will be entrusted with strategic ownership of hyperscale customer accounts. This role is ideal for a results-driven professional who excels in dynamic environments and is motivated to expand their impact within a high-performing organization. You will drive revenue growth, build deep customer relationships, and act as a catalyst for scaling team success-taking initiative, anticipating needs, and executing with precision. In addition to delivering on current revenue goals, you will be responsible for proactively creating and building a robust pipeline of opportunities, ensuring we are well-positioned to capture future revenue targets and sustain long-term growth. Success in this role means not only achieving ambitious targets but also proactively expanding responsibilities and influence across the organization. Responsibilities Take ownership of hyperscale customer accounts, driving strategic engagement and growth. Proactively identify opportunities to scale processes, expand responsibilities, and support the sales team's vision for organizational growth. Operate with agility and a sense of urgency, consistently delivering results in fast-paced situations. Serve as a trusted partner to both customers and internal stakeholders, representing the highest standards of professionalism. Demonstrate exceptional accountability, initiative, and follow-through on complex projects. Collaborate cross-functionally to ensure seamless execution and alignment with company goals. Mentor and inspire peers, fostering a culture of achievement and continuous improvement. Traits & Competencies Relentless drive for results and continuous improvement. Strategic thinker with the ability to anticipate challenges and opportunities. High emotional intelligence and adaptability. Strong sense of ownership and accountability. Ability to thrive in ambiguity and rapidly changing environments. Exceptional communication and influence skills. Entrepreneurial mindset with a bias for action. Qualifications Bachelor's degree (Engineering preferred); Master's degree is a plus 8-15 years' experience in semiconductor or datacenter/connectivity sales or field roles Proven track record of winning complex SoC/silicon design wins Strong network within cloud service providers and OEMs Exceptional leadership, communication, and project management skills Entrepreneurial mindset with a customer-first attitude Preferred Qualifications Experience selling [specific products or services, e.g., SaaS, hardware, software]. Knowledge of the Silicon Valley tech ecosystem and key players. Experience using CRM software (e.g., Salesforce). We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at ******************* Are you passionate about driving business growth for the next generation of data infrastructure with hyperscale and AI platform providers - through customer intimacy, deal negotiation and commercial strategies? We are seeking a highly proficient and experienced business manager to join our team at Astera Labs. As a key member of our business management team, you will work closely with customers, sales, product marketing, operations and other internal cross-functional teams to accelerate revenue and execute on our deal pipeline for critical opportunities. With high visibility to the executive team and customers, this role requires strong leadership and communication skills, and a blend of commercial expertise and customer insight across our product portfolio. Based in San Jose, CA, this position requires an in-person presence with travel to customers. Key Responsibilities Lead customer deal pipeline: Work closely with sales and lighthouse customers secure strategic design-wins and progress pipeline towards design-in and conversion to contracts and purchase orders. Own commercial frameworks: Set, align and approve pricing and commercial terms for key deals and establish consistent pricing strategies and methodologies across products in partnership with product marketing teams. Facilitate customer and segment playbooks: Leverage commercial, market and product expertise to support strategy definition and partner with sales to develop playbooks for key customers, segments and regions - covering key elements such as customer insights, relationship mapping, competitive analysis, win/loss analysis solution positioning and negotiation plans. Support business process innovation: Work closely with business functions to enable the next phase of scale through identifying, prioritizing and executing key operational improvements such as new operating procedures, tools or organizational clarity. Qualifications Bachelor's degree in engineering, computer science or business/marketing 10+ years of experience in, product marketing, sourcing, supply chain, operations, sales or other customer-facing product roles within the semiconductor industry Strong strategic thinking and analytical skills, with the ability to translate customer pain points into innovative solutions (deals, partnerships, or product adoption) Proven track record of negotiating and influencing customers, leading to key agreements, contracts or purchase orders Excellent communication and presentation skills, with the ability to articulate complex technical concepts in a clear and compelling manner Broad understanding of high-speed protocols (PCIe is required; Ethernet, CXL, and other protocols are a plus) and system architectures used in cloud and AI infrastructure Results-oriented mindset with a focus on driving measurable impact and achieving business objectives Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment Willingness to travel as needed for customer meetings, industry events, and trade shows We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at ******************* Role Overview Astera Labs is seeking an IT Support Technician to join our growing IT team in San Jose, California. As we scale our AI infrastructure connectivity solutions and expand our global footprint, this role is critical to ensuring our employees have seamless access to the technology and tools they need to innovate and succeed. You will be the frontline technical resource for our San Jose office, providing hands-on support for hardware, software, and productivity tools while delivering exceptional customer service. This role offers the opportunity to work in a fast-paced, high-growth environment where your technical expertise and problem-solving skills will directly impact employee productivity and satisfaction. You'll partner closely with the IT team to support onboarding, troubleshoot complex issues, manage hardware inventory, and ensure our workforce has the connectivity and computing resources necessary to drive breakthrough innovations in cloud and AI infrastructure. Key Responsibilities End-User Hardware Support & Troubleshooting Fulfill hardware requests including monitors, headsets, keyboards, mice, and various peripherals Troubleshoot laptop issues including performance problems, audio/visual concerns, system updates, and application installations Support Microsoft Office productivity applications and resolve user technical issues Upgrade user devices when laptops reach end of life and ensure smooth transitions Employee Onboarding & Offboarding Set up workstations prior to new employee start dates with monitors, keyboards, mice, and necessary peripherals Facilitate onboarding sessions to get new hires' machines running on day one, including Autopilot setup and MS Authenticator configuration Assist employees with accessing corporate Teams and Outlook on laptops and mobile devices Wipe, retire, and prepare laptops for re-use at the end of the offboarding cycle Helpdesk & Ticket Management Serve as the first line of contact for walk-up technical support across various IT issues Monitor open tickets continuously and assign to appropriate team members Triage and escalate tickets that require specialized support to the corresponding IT team member Perform password resets and basic account management tasks Support enterprise office suite issues including OneDrive and Outlook troubleshooting Asset & Inventory Management Maintain accurate and continuous records of all hardware assets in IT inventory Assist with inventory consolidation across monitors, laptops, and other equipment Track hardware lifecycle and proactively identify equipment requiring replacement or upgrade Basic Qualifications Bachelor's degree in Information Technology, Computer Science, or related field 2+ years of experience in IT support, desktop support, or helpdesk roles Strong knowledge of Windows and Mac operating systems Experience with Microsoft 365 suite, including Teams, Outlook, OneDrive, and Authenticator Hands-on experience with hardware troubleshooting and end-user device support Excellent customer service skills with ability to communicate technical concepts to non-technical users Strong organizational skills and attention to detail for inventory and ticket management Preferred Qualifications CompTIA A+, Network+, or other relevant IT certifications Experience with Jira Service Management or similar ticketing systems Familiarity with Microsoft Intune, Autopilot, and endpoint management tools Previous experience supporting a fast-paced technology or semiconductor company Knowledge of networking fundamentals and basic troubleshooting Ability to work independently and manage multiple priorities in a dynamic environment *This is a contractor role and will be paid on an hourly rate based on experience. * We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at ******************* Are you passionate about pushing the boundaries of high-speed, low-power analog technology? Do you thrive when driving-from idea conception to mass production-innovative analog solutions to complex connectivity challenges? We are seeking a creative, Senior Principal Analog Circuit Designer to contribute to Astera's development of data center connectivity solutions. In this role, you will be responsible for leading the architecture, design, development, and optimization of advanced analog circuits for high-performance systems. You will leverage your expertise in analog process technology, mixed-signal circuit design, system architecture, and hardware-software co-design. As a senior technical leader, you will work on innovative projects, influence product features and roadmaps, collaborate with cross-functional teams, and mentor junior engineers while playing a key role in advancing the company's analog design capabilities. Key Responsibilities: Lead the design of complex analog circuits including amplifiers, voltage references, and other mixed-signal blocks. Drive architectural decisions and perform detailed analog circuit design, optimization, and analysis to meet performance, power, area, and cost targets. Conduct simulations and validation of circuit designs to ensure high-performance metrics are met. Collaborate with cross-functional teams (layout, testing, process, and systems) to ensure the successful integration and delivery of analog circuit designs. Provide technical leadership in design reviews and contribute to project planning and resource allocation. Mentor and provide guidance to junior and mid-level analog circuit designers, fostering growth and development within the team. Lead or participate in the development of cutting-edge analog design methodologies, tools, and best practices. Work closely with customers to understand requirements, provide technical solutions, and ensure the successful deployment of designs in real-world applications. Conduct performance trade-off analysis and optimize designs for low power, low noise, and high-speed applications. Work with the test and validation teams to develop test plans and perform post-silicon validation. Support the transition of designs to production and work closely with manufacturing teams to resolve any issues that arise during tape-out and fabrication. Qualifications: Master's or PhD degree in Electrical Engineering, Electronics Engineering, or a related field. 10+ years of experience in analog circuit design, with a proven track record of leading complex analog and mixed-signal designs. Expertise in designing and optimizing analog building blocks Strong experience with circuit simulation tools Deep understanding of analog circuit performance characteristics, noise analysis, and layout considerations. Proficiency in hands-on prototyping, debugging, and validation of designs, both in simulation and in hardware. Strong knowledge of semiconductor fabrication processes (e.g., CMOS, BiCMOS, SOI) and process variations. Excellent problem-solving skills and ability to design innovative solutions to complex technical challenges. Strong communication and collaboration skills, with experience working in multi-disciplinary teams. Experience mentoring and leading teams of engineers, fostering a collaborative and high-performance environment. Proven ability to manage complex design projects, balancing technical and schedule constraints. Familiarity with advanced analog design topics such as power management, RF, high-speed circuits, and precision analog systems. Preferred Skills: Expertise in ultra-high-speed serial communications from 100 Gbps PAM4, to 200 Gbps PAM4 and beyond Expertise in highly-integrated systems such as multi-chip modules, optical engines, advanced packaging and silicon interposer technology Experience with data center communications protocols: PCI-Express, Ethernet, UALink, CXL, etc. Experience managing product- and new-market-exploration internally We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* About Astera Labs Astera Labs (NASDAQ: ALAB) is a pioneering fabless semiconductor company headquartered in Silicon Valley, driving the evolution of AI and cloud infrastructure through purpose-built connectivity solutions. As a leader in rack-scale architecture, Astera Labs is enabling the shift to AI Infrastructure 2.0, where compute is optimized at the rack level to support the demands of next-generation workloads. Our portfolio includes high-performance silicon, software, and system-level solutions that address critical bottlenecks in data movement across compute, memory, and networking domains. Leveraging technologies such as PCIe , CXL , Ethernet, and UALink™, we deliver scalable, interoperable platforms that empower hyperscale data centers to deploy AI and cloud services with greater efficiency and flexibility. We are committed to open standards, software-defined architectures, and continuous innovation as we work to expand our product offerings and customer engagements. We foster a collaborative environment for professionals passionate about solving complex challenges and shaping the future of intelligent infrastructure. Role Overview Astera Labs is seeking a strategic and proactive Senior Principal Category Sourcing Manager to lead sourcing initiatives across Corporate Services & Operations, a category that spans a broad and dynamic range of enterprise needs. This includes sourcing for professional services (legal, finance, marketing, recruiting, and engineering consulting), IT infrastructure and equipment, corporate software tools, facilities and real estate services, and workplace operations. This role is foundational to enabling enterprise-wide operations and supporting business continuity, compliance, and employee productivity. You will be responsible for developing and executing category strategies, managing supplier relationships, and driving high-impact negotiations across a diverse set of internal stakeholders and external partners. You'll also play a key role in vendor consolidation, spend governance, and process optimization to support Astera Labs' rapid growth and evolving business needs. A Day in the Life In this role, you'll be at the center of enabling Astera Labs' enterprise operations. Your day is shaped by dynamic interactions across legal, finance, IT, and facilities teams, as you help translate business needs into sourcing strategies that drive efficiency, scalability, and value. You'll navigate a diverse landscape of suppliers-from strategic consulting firms and software providers to facilities and real estate partners-building relationships and shaping agreements that support both immediate needs and long-term growth. Whether you're refining a framework for professional services sourcing, evaluating new IT platforms, or exploring ways to streamline corporate spend, your work will influence how the company operates and scales. This role offers a unique blend of strategic ownership and cross-functional engagement, where your decisions directly impact business continuity, employee experience, and operational excellence. Key Responsibilities Develop and execute sourcing strategies for corporate categories including professional services, IT infrastructure, facilities, real estate, and enterprise software. Lead supplier selection, negotiation, and contract execution including NDAs, MSAs, SOWs, and licensing agreements. Partner with internal stakeholders to align sourcing initiatives with business needs and operational goals. Drive vendor consolidation and strategic partnerships to improve service levels and reduce cost. Streamline procurement processes for high-volume, low-value purchases and support spend governance improvements. Monitor supplier performance, compliance, and service-level agreements (SLAs). Analyze market trends, cost structures, and supplier capabilities to inform sourcing decisions. Collaborate with logistics and procurement operations teams to support freight rate negotiations and global sourcing initiatives. Basic Qualifications Bachelor's degree in Business, Supply Chain, Finance, or related field. 7+ years of experience in indirect sourcing, procurement, or supplier management across corporate categories. Proven experience negotiating contracts for professional services, IT infrastructure, facilities, and enterprise tools. Strong understanding of procurement operations, vendor management, and spend governance. Demonstrated ability to lead complex negotiations and manage supplier relationships across global teams. Preferred Qualifications Master's degree in Business, Supply Chain Management, or related discipline. Experience with sourcing frameworks for legal, consulting, and engineering services. Familiarity with corporate IT tools, SaaS licensing models, and facilities management. Strong analytical, financial modeling, and contract management skills. Excellent communication and stakeholder engagement across technical and business functions. Why Join Us? Be part of a high-growth, innovation-driven company at the forefront of AI and cloud infrastructure. Work with diverse teams and strategic partners across the enterprise. Enjoy a collaborative culture that values ownership, agility, and continuous improvement. Competitive compensation, equity, and benefits package. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at ******************* About Astera Labs Astera Labs (NASDAQ: ALAB) is a pioneering fabless semiconductor company headquartered in Silicon Valley, driving the evolution of AI and cloud infrastructure through purpose-built connectivity solutions. As a leader in rack-scale architecture, Astera Labs is enabling the shift to AI Infrastructure 2.0, where compute is optimized at the rack level to support the demands of next-generation workloads. Our portfolio includes high-performance silicon, software, and system-level solutions that address critical bottlenecks in data movement across compute, memory, and networking domains. Leveraging technologies such as PCIe , CXL , Ethernet, and UALink™, we deliver scalable, interoperable platforms that empower hyperscale data centers to deploy AI and cloud services with greater efficiency and flexibility. We are committed to open standards, software-defined architectures, and continuous innovation as we work to expand our product offerings and customer engagements. We foster a collaborative environment for professionals passionate about solving complex challenges and shaping the future of intelligent infrastructure. Role Overview Astera Labs is seeking a hands-on and detail-oriented Logistics Operations Specialist with experience working for a semiconductor company to support daily shipping, receiving, and logistics coordination at our San Jose corporate site, while also contributing to global shipping operations. This role is essential to ensuring the smooth and timely movement of goods across corporate and customer locations. In addition to executing core logistics tasks, this role will support import and export compliance, tariff mitigation strategies, and direct materials logistics planning. The ideal candidate is proactive, organized, and eager to contribute to both tactical execution and operational efficiency. A Day in the Life Your day will involve coordinating inbound and outbound shipments, preparing documentation, and working with carriers to ensure timely delivery. You'll be the go-to person for receiving packages, staging materials, and resolving shipping issues. Alongside your daily tasks, you'll help identify opportunities to improve workflows-whether it's refining documentation practices, streamlining vendor coordination, or supporting system upgrades. You'll collaborate with internal teams and external partners to keep logistics running smoothly, while contributing ideas and feedback that help the team scale with the company's growth. Key Responsibilities Execute daily shipping and receiving operations at the San Jose corporate site. Prepare and process shipping documentation including labels, packing slips, and bills of lading. Coordinate with carriers and vendors to ensure timely and accurate deliveries. Support global logistics operations including international shipments and customs documentation. Ensure compliance with import/export regulations and maintain accurate records for audits. Develop and implement tariff mitigation strategies to optimize cost efficiency. Contribute to direct materials logistics strategy, including planning and coordination with suppliers. Identify and contribute to process improvement initiatives across logistics workflows. Collaborate with internal teams to fulfill material requests and troubleshoot shipping issues. Assist in implementing logistics systems and tools to improve operational efficiency. Basic Qualifications Bachelor's degree in Logistics, Supply Chain Management, Business, or a related field. 7+ years of experience in logistics, shipping/receiving, or warehouse operations, with experience in a semiconductor company. Familiarity with shipping platforms (e.g., FedEx, UPS, DHL) and basic documentation. Strong understanding of import/export compliance and international shipping regulations. Proven track record in tariff mitigation and direct materials logistics planning. Ability to lift and move packages and materials as needed. Strong attention to detail and organizational skills. Effective communication and teamwork across departments. Preferred Qualifications Experience with logistics systems such as Oracle or similar platforms. Experience supporting logistics process improvements or system implementations. Why Join Us? Be part of a fast-growing, innovation-driven company supporting the future of AI and cloud infrastructure. Work in a hands-on role that directly supports global operations and product movement. Enjoy a collaborative culture that values precision, ownership, and continuous improvement. Competitive compensation and benefits package. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Role Overview As a Distinguished Product Quality Engineer, you will be responsible for ensuring the quality and reliability of Astera Labs' advanced high-speed (SerDes PAM4 and optical-integrated) semiconductor products across their lifecycle - from design through high-volume semiconductor manufacturing. You will be the primary quality interface for integrated circuit (IC) NPI-related activities, including assessing test coverage, design quality risks, and other NPI quality considerations. This NPI role will also lead the development and implementation of IC diagnostic test strategies, collaborate in defining diagnostic coverage metrics, and work with internal engineering teams to enable robust debug methodologies across leading-edge process technologies (16nm to Key Responsibilities Driving Product Quality Engineering: Work with operations, firmware, and other internal engineering teams to drive product quality improvements both as part of NPI activities and volume manufacturing. This role will participate in various NPI engineering reviews to ensure exit criteria are met, new product issues and learnings are addressed, and production issues are driven to root cause. Work with the operations engineering teams to build data systems and infrastructure to eliminate outliers, predict quality trends, and identify product quality opportunities that will improve customer outcomes. Develop signature analysis techniques to identify systemic root causes by leveraging advanced AI and/or ML techniques where appropriate. Leading NPI Quality-Related Validation & Issue Debugging: Lead the debugging of complex hardware, firmware, and software issues as part of quality team activities during NPI and high-volume production, leveraging diagnostic hooks and advanced debug tools. Develop and maintain automated diagnostic tools to scale and drive reuse across multiple product families. Partner with operations engineering to improve diagnostic efficiency, reduce overkill/retest, and improve product yield and quality. Integrate diagnostics into silicon lifecycle management, firmware release, and reliability tracking to proactively detect degradation or field reliability risks. Interoperability & System-Level Support: Work with field, firmware, and internal engineering teams to ensure interoperability, diagnostic transparency, and robust field debug capability. Diagnostic Test Development: Define and drive the deployment of diagnostic test plans, fixtures, tools, and methodologies needed for fault isolation of customer returns in PCIe, CXL, UCIe, Ethernet, and other high-speed switching products. Fan out the most successful tools for broader application in high-volume manufacturing and troubleshooting of NPI (New Products) qualification failures or field application issues. Embedded Silicon Agent Champion: Drive the external selection or internal development of embedded silicon agents to monitor temperature, voltage, noise, process, timing, etc., at the block level on-chip. Work with design teams on implementation. Collaborate with validation and design teams to debug these features in the lab during the post-silicon phase. Partner with firmware teams to leverage these features for real-time adaptive behavior. Partner with software teams to process the data and create accessible and actionable diagnostic conclusions. Design DFT Review: Work with design, operations engineering, and system validation teams to drive early Design-for-Testability (DFT) and diagnostic capabilities with design and product engineering teams. Coordinate block-by-block-level reviews to ensure no gaps in coverage and that all prior lessons learned are applied. Advanced Packaging Diagnostics: Develop diagnostic methodologies for MCM, 3DIC, and optical interconnect packages, including die-to-die and heterogeneous integration interfaces needed to diagnose, isolate, and ensure high-quality products. Skills and Experience Deep experience with digital and SerDes high-speed protocols (PCIe Gen5/Gen6, CXL, UCIe, Ethernet/SerDes) and system-level validation methodologies. Direct and deep experience working with embedded silicon diagnostic agents. Experience working with engineering teams creating product characterization and test plans, test programs, and collaborating with the greater engineering community to obtain and analyze data across process, voltage, and temperature to evaluate semiconductor products. Hands-on experience with lab debug tools (protocol analyzers, oscilloscopes, BERTs, error injection frameworks). Proficiency in scripting and software development (Python, C/C++, Java, or similar) for diagnostic automation and data analysis. Proven ability to analyze complex test data, identify root causes, and implement systemic solutions. Familiarity with semiconductor test flows (ATE, system-level test, characterization, production validation). Experience with advanced packaging technologies (MCM, 3DIC, optical) and their diagnostic/test challenges. Strong communication skills for collaborating across design, product, test, and customer teams. Demonstrated ability to influence cross-functional decisions and drive quality improvements at the organizational level. Preferred Qualifications Minimum of 5 years of experience leading a high-caliber product engineering team. Minimum of 10 years within a product or diagnostics engineering team with successful deployment of semiconductor devices into production. Strong academic/technical background in electrical engineering; Bachelor's required, Master's preferred. Experience with diagnostic firmware and test development methodologies. Knowledge of advanced techniques for anomaly detection in diagnostic/test data. Track record of leadership in new product introduction (NPI) for complex, high-speed semiconductor products. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at ******************* Job Description: As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products. You will be working on projects from conception to the final production stage at contract manufacturer. The role requires a strong and broad software background and good understanding of hardware design and manufacturing practices. At the same time we welcome candidates with deep experience in smaller areas with the desire to learn. Depending on your experience, you may be focusing on design/validation or automation/manufacturing. Key Responsibilities Design, implement & test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation. Design, implement & test manufacturing tests to validate mass production of digital boards used in data center networking product Bring-up newly manufactured boards and develop the first level of software. Isolate and perform root-cause analysis of reported failures Support new platform software and hardware features Coordinate with the hardware engineering team on bring-up schedules and feature delivery Participate proactively in design discussions, design review, and project management Work independently as well as in team roles, mentor younger team members Basic Qualifications/Required Experience Bachelor's in CS/CE or equivalent experience. 8+ years of Experience in subset of diagnostic, hardware bring-up, test or manufacturing automation Knowledge of modern software development Proficiency in Python, C/C++ Preferred experience Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing Ability to read schematic/layout System debug experience Embedded programming and good knowledge of OS internals (Linux/Unix) Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming. Experience with DDR5 The base salary range is $203,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at ******************* Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure? We are seeking a highly technical and experienced product manager to join our team at Astera Labs. As a key member of our product management team, you will work closely with customers, product marketing and other cross-functional teams to define and deliver competitive silicon, hardware and software solutions. With high visibility to the executive team and customers, this role requires strong leadership and communication skills, and a blend of technical expertise and market insight within your product domain. This is a unique opportunity to play a pivotal role in the success of our Scorpio Smart Fabric Switch portfolio. We are scaling our product team to support our worldwide customers, offering ample opportunities for growth and advancement within the product team. Based in San Jose, CA or Vancouver, BC, this position requires an in-person presence with travel to customers. Key Responsibilities Own product definition: Define detailed product requirements and prioritize features, enhancements, and bug fixes based on business goals and customer feedback. Lead customer technical engagement: Work closely with lighthouse customers to translate their needs to competitive product requirements and secure new design-wins throughout the product lifecycle. Support go-to-market: Leverage technical and product expertise to support product marketing and corporate marketing teams on go-to-market planning and execution, sales enablement, competitive analysis, and product positioning. Lead product planning: Work closely with product marketing to translate product strategy into executable product plans and collaborate with Astera Labs cross-functional teams to drive products from ideation to launch. Qualifications Bachelor's degree in engineering or compute science 5-10 years of experience in product management, technical product marketing, applications or other customer-facing product roles within the semiconductor industry Proven track record of defining and launching successful semiconductor products (switch products are a plus) Deep understanding of high-speed protocols (PCIe/CXL and/or UALink are required; Ethernet and other protocols are a plus) and system architectures used in cloud and AI infrastructure Strong strategic thinking and analytical skills, with the ability to translate customer pain points into competitive products Excellent communication and presentation skills, with the ability to articulate complex technical concepts in a clear and compelling manner Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment Results-oriented mindset with a focus on driving measurable impact and achieving business objectives Experience working with customers and partners to understand their needs and drive product definition Willingness to travel as needed for customer meetings, industry events, and trade shows If you are passionate about driving innovation and shaping the future of data center connectivity through world-class products, we encourage you to apply. Join Astera Labs in unleashing the potential of cloud and AI infrastructure! Compensation will be based on leveling and experience. Base Salary Range $210,000 - $255,000 We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Overview: Astera Labs Inc. is a fabless semiconductor company that develops purpose-built connectivity solutions to remove performance bottlenecks in compute-intensive workloads such as artificial intelligence and machine learning. To support our rapid growth, we are hiring a Lead IC Package Designer with extensive experience in complex ASIC package design using Cadence APD. Background in SI/PI is a plus. Job Description: As an Astera Labs Lead Package Design Engineer, you will take ownership of package design and layout for Astera Labs' portfolio of connectivity products deployed by the world's leading cloud service providers and server/networking OEMs. You will be responsible for driving package substrate design from definition to tape-out, including performance optimization, design for manufacturing, and sign-off verification. You will also provide technical guidance within the package design team: mentoring junior designers, guiding best practices in APD, reviewing design work for quality and consistency, and working closely with SI/PI, product engineering, and hardware teams to ensure first-pass success. You will also help shape design flows, champion productivity improvements, and represent package design expertise in cross-functional discussions. Basic Qualifications: BS/MS in Engineering (Electrical, Mechanical, Materials Science, Physics, or related field). 8+ years of experience in Cadence APD/SiP with a track record of independently designing and releasing FCBGA/FCCSP packages from concept to tape-out. Proven experience leading package design efforts, reviewing and mentoring other designers, and setting technical directions. Deep understanding of BGA substrate technologies, stackups, design rules, and assembly processes. Familiarity with package reliability, SI/PI, and design sign-off methodologies. Entrepreneurial, open-minded, and hands-on work ethic with the ability to drive multiple priorities in a dynamic environment. Strong collaboration and communication skills to work effectively across functions and influence outcomes. Required Experience: Expert proficiency in Cadence APD/SiP (this is a must have). Able to design large-body BGAs from concept through tape-out with minimal guidance. Strong knowledge of package BOM integration, layer stackup, padstacks, constraint setup (physical and electrical), SMT component design, and optimization based on SI/PI feedback. Experience running and interpreting DRC/DRV/LVS/DFM checks, generating documentation, and releasing Gerbers/artwork. Ability to conduct feasibility studies such as fan-out, mock-ups, and layer/package size reduction. Understanding of package manufacturing flow, supply chain considerations, reliability, and risk management. Technical leadership in driving new APD design flows, methodologies, and automation (working with vendors or through scripting). Preferred Experience: Multi-chip, interposer, 2.5D or heterogeneous package design experience is a plus. Proficiency in scripting languages for design and reporting automation is a plus. The base salary range is $175,750.00 USD - $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

.Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Job Description: As an Analog/Mixed-Signal IC Design Engineer NCG, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role Basic Qualifications: Pursuing a Master's or PhD degree in EE is preferred Desired Experience: Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits Solid track-record for implementation of analog circuits high-speed data transmission. Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis. Knowledge of TIA design and drivers for optical applications is highly desirable Experience in RFIC design for wireless or wireline communication systems is highly desirable. Strong technical independent contributor with a proven ability to drive results. Excellent teamwork, presentation, and documentation skills. Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines. Strong experience in lab chip bring-up and debugging efforts. Relevant research publications and/or patents in analog or RF IC design. Familiarity in programming/scripting languages such as Python, Matlab, or C. Experience with PCB design. Familiarity with Verilog RTL or DSP design concepts. Knowledge of optical transceivers. Expertise in ESD protection techniques and IC packaging methodologies. The base salary range is $150,000.00 USD - $200,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

.Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Job Description: As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products. You will be working on project from conception to the final production stage at contract manufacturer. The role requires strong and broad software background and good understanding of hardware design and manufacturing practices. At the same time we welcome candidates with deep experience in smaller areas and desire to learn. Depending on your experience you may be focusing on design/validation or automation/manufacturing. Key Responsibilities Design, implement & test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation Design, implement & test manufacturing tests to validate mass production of digital boards used in data center networking product Bring-up newly manufactured boards and the port the first level of software Isolate and perform root-cause analysis of reported failures Support new platform software and hardware features Coordinate with the hardware engineering team on bring-up schedules and feature delivery Participate proactively in design discussions, design review, and project management Basic Qualifications/Required Experience Bachelor's in CS/CE or equivalent experience. Experience in subset of diag, hardware bring-up, test or manufacturing automation Knowledge of modern software development Proficiency in Python and C Preferred experience Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming. Ability to read schematic/layout System debug experience Embedded programming and good knowledge of OS internals (Linux/Unix) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at ******************* Overview: As a Senior Principal Validation Engineer, you will join a cutting-edge mixed-signal design team and lead the end-to-end post‑silicon validation and characterization effort. You will own the development and execution of comprehensive validation plans, design and implement test methodologies, and drive hands‑on lab work to verify silicon against specification and performance targets. You will collaborate closely with design, firmware, and system teams to translate architectural goals into measurable test strategies, build automated test frameworks, and analyze complex analog and digital interactions. Your work will include defining test requirements, creating characterization flows, debugging silicon anomalies, and delivering clear, data‑driven recommendations that influence product direction. This role requires deep technical expertise in mixed‑signal systems, strong problem‑solving skills, and the ability to mentor engineers across disciplines. You will be expected to champion best practices for validation, optimize test coverage and throughput, and ensure that products meet reliability, yield, and performance objectives before production. Key Responsibilities: Design, develop, and execute validation plans. Own end‑to‑end post‑silicon characterization and validation strategies, translating product requirements into measurable test objectives, pass/fail criteria, and schedules. Drive design reviews and specification alignment. Participate in architecture and design‑spec reviews to ensure testability, trace requirements to verification plans, and influence design tradeoffs to meet performance and reliability targets. Lead hands‑on test execution and bring‑up. Perform silicon bring‑up, functional and parametric testing, interop checks, and performance benchmarking; rapidly iterate on test flows to accelerate time‑to‑data. Build and maintain automation frameworks. Develop scalable test automation, data capture, and analysis pipelines to increase throughput, reproducibility, and coverage across mixed‑signal test benches. Debug and optimize system performance. Diagnose complex failures and performance bottlenecks across analog, digital, firmware, and protocol layers; propose and validate corrective actions to improve stability, yield, and power/performance tradeoffs. Root‑cause cross‑domain failures. Trace issues to circuit, package, firmware, or protocol interactions using lab measurements, waveform analysis, and system‑level tests; coordinate with design, package, and firmware teams to implement fixes. Collaborate with cross‑functional teams. Work closely with mixed‑signal design, firmware, system engineering, and manufacturing to deliver detailed results, root‑cause analyses, optimization recommendations, and formal validation/compliance reports. Document findings and improve methodologies. Produce clear debug reports, formal characterization summaries, and recommendations for design/process/test improvements; contribute to failure analysis (FA) best practices and knowledge base. Develop test software and platform integrations. Write robust Python test scripts and control interfaces to configure, monitor, and collect status from multiple DSP and hardware platforms, improving firmware stability and automating regression suites. Measure and communicate impact. Define key validation metrics, track coverage and defect trends, and present data‑driven conclusions to stakeholders to influence product direction and release decisions. Basic Qualifications Education - Bachelor of Science in Electrical Engineering required; Master's degree preferred to demonstrate advanced technical depth and specialization. Experience - At least ten years of hands‑on experience in mixed‑signal, high‑speed lab environments, executing characterization and validation with industry instruments such as protocol analyzers, BERTs, real‑time oscilloscopes, sampling scopes, TDRs, and VNAs. Software Skills - Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction. Retimer Expertise - Practical experience bringing up and debugging retimers, including equalization tuning, pass‑through operation, clocking strategies, and reset and link sequencing. High‑Speed Signaling Knowledge - Deep understanding of NRZ and PAM4 architectures and the ability to investigate jitter sources, CDR and PLL behavior, equalization techniques such as DFE, CTLE, and FFE, as well as crosstalk and power integrity issues. Post‑Silicon Validation - Proven track record in post‑silicon validation and bring‑up of high‑speed PHYs or retimers, with experience developing characterization flows and validating silicon against specifications. Circuit Block Familiarity - Solid working knowledge of key high‑speed building blocks including PLLs, CTLE, DFE, transmitter equalization, and PAM4 signaling fundamentals. Analytical Problem Solving - Exceptional troubleshooting skills with the ability to isolate and narrow complex, multi‑layer failures across analog, digital, firmware, and package domains. Communication - Excellent written and verbal communication skills for clear documentation of findings, presentation of root cause analyses, and collaboration with cross‑functional teams. Preferred Experience: Mixed‑signal system testing and validation - Demonstrated experience in end‑to‑end mixed‑signal system testing, characterization, validation, and compliance activities, including developing test plans, executing characterization flows, and producing formal compliance reports. Signal integrity instrumentation and techniques - Hands‑on proficiency with signal integrity test equipment and methodologies, including BERTs, VNAs, oscilloscopes, sampling scopes, TDRs, and advanced probing techniques for channel and package analysis. Ethernet standards familiarity - Working knowledge of IEEE 802.3 family standards and practical experience validating Ethernet PHYs, link training, autonegotiation, and compliance testing across relevant speeds and media types. Serial protocol expertise - Practical understanding of common serial interfaces such as I2C, I3C, SPI, UART, and other control/status buses used for device bring‑up, firmware interaction, and system integration. Cross‑discipline collaboration - Proven ability to translate SI/PI simulation results into testable lab plans, collaborate with design and firmware teams to close the loop on issues, and document findings that drive design or process improvements. Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly. The base salary range is USD 205,00 - USD 255,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

.Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Job Summary: As an Astera Labs Hardware Electrical Engineering Intern you will be part of a Hardware Design Group, assisting and designing devices featuring Astera Labs' portfolio of connectivity ASICs. In this role you will be given significant responsibility for hardware design support. Mainly, assisting designers with the development and bring-up of major hardware projects, and directly developing hardware sub-projects. Job Responsibilities: Assist hardware designers with hardware development Assist with bring-up Assist with design reviews Electronic measurements and analysis Develop hardware for testing Schematic entry and printed circuit board (PCB) layout Circuit design Assist with validation BOM management Required Skills: Basic Qualifications Pursuing a bachelor's with honors in electrical engineering Strong background in electrical engineering Self-starting, strong initiative, and can-do attitude. Required Experience Strong understanding of circuit design and analysis Strong understanding of microelectronics Strong understanding of electronics test Strong debugging skills Microsoft Office proficiency Experience with PCB layout Experience with schematic entry Experience with oscilloscopes and electronics lab equipment We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at ******************* As a Principal Hardware Electrical Validation Engineer you will join the Hardware Electrical Validation team at Astera Labs, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others. Note: This role is not post-silicon electrical validation; it is electrical validation of PCBAs and related hardware products. Key Responsibilities: Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out. Develop comprehensive hardware electrical validation plans using correct test methods and processes. Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board. Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc. Rework components on the PCBAs to unblock debugging activities. Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams. Support hardware activities in auxiliary teams - Post-Silicon Electrical Validation, Product Apps, System Validation, FAEs, etc. Support the new designs using knowledge of existing products to de-risk new features and requirements. Self-informed of new industry test standards and equipment to introduce modern testing methodologies. Specify test equipment, develop test fixtures, help improve hardware lab functions. Required Skills: Demonstrated strong skills in electronic circuit analysis, comprehensive testing and debug Bachelor degree in EE with 10+ years of experience in hardware test or design Define/refine hardware test methodologies and identify appropriate test equipment Expert understanding of design and test for power regulators, PDNs, Bode, clock gens Ability to produce test description from a schematic design, and execute and document results Demonstrated knowledge of the full hardware product lifecycle from Project Kick-off to RTM Lab equipment for hardware test - oscilloscopes, e-loads, VNA, TDR, environmental chambers, etc. Automating lab equipment to optimize test processes, Python preferred Preferred Skills: Measurements of high-speed interfaces - PCIe, DDR, 25/50G/100G SERDES, etc. EMI/EMC compliance Technical writing skills - ECOs, Bug Reports, Rework WIs, MCOs, etc. PLM, Arena or equivalent Understanding of the ASIC/silicon product development process Base salary range is $185,000 USD-$230,000 USD, and will be determined based on the candidate's capabilities and employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Job DescriptionSalary: DOE Firmware Engineer(entry level) Are you passionate about development and project-based work? Do you like a significant challenge? We offer this and much, much more. Our teams work with cutting-edge NAND SSD controllers and storage systems We are searching for brilliant Software Developers (0-3 years experience) to join our Firmware Development Team at Bay Area site, San Jose, CA. New grad welcomed! We are looking for forward thinkers and critical players who learn, grow, and make your contributions. Firmware Developer technical skills: Good programming capability in C Experience or good understanding of embedded systems Experience or good understanding of PCIe/NAND/SMBus/UART/SPI protocols BS in Computer Science, or EE About Innogrit Corporation Innogrit is transforming data storage with its advanced PCIe Gen 3 and Gen 4 SSD (Solid State Drive) Processors. By delivering unprecedented reliability, performance, and energy efficiency, SSDs based on Innogrits technology unleash the full potential for next generation SSDs using the latest NAND flash memory.