Design Development Engineer jobs at Intel - 520 jobs

Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world - like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. You'll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. Visit our Careers website to learn more. At Applied Materials, we care about the health and wellbeing of our employees. We're committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Aid in the establishment and management of packaging suppliers and related processes and procedures. Develop test plans and perform laboratory testing on products, packages, and packaging materials. Support the Product Life Cycle (PLC) process by defining Design For Transportability (DFT) requirements and influencing product design. Develop and maintain global packaging standards and specifications for Applied Materials and its Supply Base. Provide advanced training and support to Packaging Engineer III. Duties will vary according to the project in progress and/or the specific goals of the department in which the incumbent works. Demonstrates depth and/or breadth of expertise in own specialized discipline or field May lead functional teams or projects with moderate resource requirements, risk, and/or complexity Impacts the achievement of customer, operational, project or service objectives; work is guided by functional policies At Applied Materials' CTO office, we are developing optical interconnect solutions for the next generation hyperscale computing and AI/ML. You will be working with a highly capable international team to develop advanced photonics packaging solution. You will lead optomechanical design, optical sub-assembly design, micro optics, fixture and tooling development. Those fixtures and tooling are expected to achieve micron level assembly accuracy. You are also expected to design / develop multi-fiber optical connectors and work with external vendors to develop connector eco-system. You are also expected to be familiar with various materials used in photonics industry, including but not limited to: glass, epoxy, silicon and other related materials. You daily activities includes working with 3D solid models, drawings, and documentation utilizing GD&T principles; assessing designs against environmental requirements; With a product focus, the individual will actively partner with other engineering disciplines and operations personnel to develop solutions that adhere to DFT and DFM requirements. D in optics, or mechanical engineering is desired. Industrial experience in optical communication industries is required. You should have expert level knowledge on optomechanical design, Solidworks or ProE, GD&T and ASME 14.5. Understanding of FEA for stress and thermal analysis, ideally understand the use of Ansys Mechanical and Icepak simulation tools Appreciation for Structured Problem Solving Full time Travel: Relocation Eligible: The salary offered to a selected candidate will be based on multiple factors including location, hire grade, job-related knowledge, skills, experience, and with consideration of internal equity of our current team members. In addition to a comprehensive benefits package, candidates may be eligible for other forms of compensation such as participation in a bonus and a stock award program, as applicable. For all sales roles, the posted salary range is the Target Total Cash (TTC) range for the role, which is the sum of base salary and target bonus amount at 100% goal achievement. Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law. In addition, Applied endeavors to make our careers site accessible to all users. If you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_****************, or by calling our HR Direct Help Line at ************, option 1, and following the prompts to speak to an HR Advisor. This contact is for accommodation requests only and cannot be used to inquire about the status of applications.

A leading technology company is seeking a Physical IC Design Engineer in San Jose, California. The role involves executing various physical design tasks and requires a bachelor's degree in Electrical or Electronics Engineering with over 12 years of relevant experience. Strong scripting skills and expertise in EDA tools are essential. The position offers a competitive salary range of $141,300 - $226,000 along with comprehensive benefits including health insurance, 401(K) matching and more. #J-18808-Ljbffr

A leading technology company in San Jose is looking for a Physical IC Design Engineer to drive next-gen AI and ML ecosystems. The role requires 8+ years of experience and a Bachelor's degree in Electrical or Electronics Engineering. Responsibilities include execution of Physical Design, Synthesis, and collaborating with IC Design engineers. This position has a salary range of $120,000 - $192,000 and offers a comprehensive benefits package including health plans, 401(K) matching, and paid leave. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking a Physical IC Design Engineer to drive next-generation AI and ML ecosystems through PCIe Switch Products. This role requires a strong background in Physical Design, including execution of design, verification, and timing closure. The ideal candidate must have a Bachelor's degree in Electrical or Electronics Engineering and at least 8 years of experience. The position offers a competitive salary range of $120,000 to $192,000, along with comprehensive benefits. #J-18808-Ljbffr

A leading technology firm located in San Jose is seeking a Physical IC Design Engineer to drive innovation in Artificial Intelligence and Machine Learning through their products. This position focuses on executing the physical design and verification of chip architectures. Candidates should possess a Bachelor's degree in Electrical Engineering or Electronics Engineering and have over 8 years of relevant experience. The role offers a competitive salary ranging from $120,000 to $192,000, plus various benefits including medical and retirement plans. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking an experienced Physical IC Design Engineer to join their Data Center Solutions Group. You will drive advancements in AI/ML ecosystems and manage data centers. The ideal candidate will have over 12 years of experience in physical design and proficiency in TCL/PERL scripting. A Bachelor's degree in Electrical or Electronics Engineering is required. This position offers a competitive salary and comprehensive benefits package, including health insurance and 401(k) matching. #J-18808-Ljbffr

A leading technology firm in San Jose is seeking a Physical Design Engineer to focus on the implementation and optimization of IC layouts for advanced technologies. The ideal candidate has extensive experience in physical layout, strong scripting skills in TCL and Python, and a solid background in electrical engineering. This role offers a competitive salary, bonus potential, and comprehensive benefits. #J-18808-Ljbffr

Physical Design Engineer - New College Grad 2026 page is loaded## Physical Design Engineer - New College Grad 2026locations: US, CA, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR2009983We are now looking for a Physical Design Engineer!NVIDIA has continuously pioneered and reinvented itself over two decades through various avenues of computing: Graphics, High Performance Computing, Artificial Intelligence, Research, and more. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can solve, and that matter to the world. This is our life's work, to amplify human creativity, intelligence, and technology. Today, visual computing is becoming increasingly central to how people interact with technology, and there has never been a more exciting time to join our team. We are looking for a Physical Design Engineer who will be responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets, and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets.**What you will be doing:*** As a member of the team, you will participate in the efforts in establishing CAD and physical design methodologies (flow and tools development) as well as implementation.* Your day to day will include developing chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects.* This position requires you to work with EDA vendor (Synopsys, Cadence, Mentor, etc.) tool suites such as: ICC2,PrimeTime, dc\_shell, Innovus, SeaHawk.* You will interact with a diverse team engineers.**What we need to see:*** Completing an BSEE, MSEE or PhD (or equivalent experience).* Deep understanding of VLSI and Physical Design related basics & concepts.* Possess a deep understanding of static timing analysis, clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis.* Experience in scripting and programming using several of the following languages/tools: Perl, C, C++, TCL, Scheme, Skill, or Make.* Previous internship or project experience in physical design implementation With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a passion for technology, we want to hear from you!Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 96,000 USD - 161,000 USD for Level 1, and 108,000 USD - 184,000 USD for Level 2.You will also be eligible for equity and .Applications for this job will be accepted at least until December 19, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr

A leading technology company in San Jose is seeking a candidate for a role focused on designing and building AI-driven workflows for security operations. Candidates should have a strong background in security operations, extensive Python development experience, and familiarity with security data tools. You'll collaborate closely with various teams to enhance detection and response strategies. The position offers competitive compensation ranging from $291,500 to $369,100, alongside a rich suite of benefits. #J-18808-Ljbffr

A leading technology company in San Jose is seeking an experienced engineer to join their analog/mixed signal IP design team. This role involves designing next generation I/O interfaces, with a strong emphasis on mixed signal design and leading technical projects. The ideal candidate will possess a degree in Electrical Engineering and have hands-on experience with high speed designs and communication tools. This position offers competitive benefits and is not eligible for visa sponsorship. #J-18808-Ljbffr

A leading semiconductor company in Santa Clara is looking for an FPGA Hardware Validation Engineer to create and implement validation platforms while collaborating with design and firmware teams. Candidates should have extensive experience in FPGA prototyping and strong problem-solving skills, along with a BS in Electrical or Computer Engineering. The role involves complex architecture designs and debugging hardware/firmware issues. Join a culture of innovation driven by collaboration and inclusivity. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. The Role This role is an exciting opportunity in SBIO team to create FPGA hardware validation platforms and debugging complex issues involving both hardware and software. Collaborate with design and firmware teams to define validation plans and execute on FPGA prototyping platforms. This role requires a proven track record of successfully bringing complex FPGA designs from concept through production quality, with strong debugging and problem-solving capabilities. The Person Strong analytical and problem solving skills with a pronounced attention to detail Strong communication, mentoring and leadership skills Self-driven, Methodical and attention to detail in troubleshooting and problem-solving Can work well with cross functional teams Excellent verbal and written communication skills Responsibility Design, develop, and implement complex FPGA architectures using Xilinx devices (UltraScale, UltraScale+, Versal, etc.) Create RTL designs using Verilog/SystemVerilog for high-performance applications Perform FPGA prototype design, implementation, and bring‑up activities Create comprehensive design documentation, specifications, and technical reports Perform timing analysis, closure, and optimization using Vivado tools Conduct board-level bring‑up and system integration testing Debug complex hardware/firmware issues using logic analyzers, oscilloscopes, and other test equipment Validate FPGA designs against specifications and performance requirements Independently troubleshoot and resolve challenging technical issues Work closely with hardware, software, and systems engineering teams Participate in design reviews and technical discussions Communicate project status, risks, and technical challenges to stakeholders Preferred Skill Set & Experience Extensive experience in field of FPGA hardware prototyping Have worked with prototyping platforms such as Xilinx reference boards, Synopsys HAPS platforms etc Experience with Xilinx Versal ACAP or UltraScale+ devices Knowledge of FPGA synthesis tools and methodologies Familiarity with Python/TCL scripting for design automation Knowledge of FPGA-based system architecture and hardware/software co‑design Familiarity with board design and hardware debugging tools (logic analyzers, oscilloscopes, protocol analyzers) Fluent in System Verilog and a familiarity with simulation and debug Familiarity with industry standard high-speed protocols such as USB and PCIE is a plus EDUCATION BS (or higher) degree in Electrical or Computer Engineering desired LOCATION Santa Clara, CA This role is not eligible for visa sponsorship. #LI‑SC3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE We are seeking a Senior Member of Technical Staff (SMTS) SoC Architect to join our SoC Architecture team. In this role, you will define and drive architecture for critical SoC functions across roadmap and custom devices. You will focus on chip pervasive components, while ensuring seamless integration with processor subsystems, interconnect, AI accelerators, and memory systems. THE PERSON You are passionate about complex SoC architecture and thrive in cross-functional environments. You have deep technical expertise, strong analytical skills, and the ability to balance performance, power, and area trade-offs. You communicate effectively across teams and are comfortable influencing architecture decisions for next-generation silicon. KEY RESPONSIBILITIES Define and develop SoC architecture for CPF components, including Analog IPs, clocking/reset, and silicon monitors. Collaborate with processor, interconnect, AI, and memory subsystem architects to ensure cohesive system-level design. Specify architecture requirements, conduct early-stage analysis, and create detailed specifications. Drive PPA optimization and ensure scalability across roadmap and custom devices. Partner with design, verification, and physical implementation teams to ensure functional correctness and timing closure. Analyze trade-offs for performance, power, reliability, and manufacturability. Influence strategies for security, safety, and reliability across CPF domains. Strong communication and leadership skills to influence cross-functional teams. PREFERRED EXPERIENCE Strong background in SoC architecture, including processor subsystems, interconnect, memory systems, and AI accelerators. Expertise in Analog IPs (IOs, PLLs, eFuses, monitors), clocking/reset architecture, and silicon lifecycle management. Familiarity with SoC on-chip protocols (e.g., AXI) and system-level QoS. Experience with low-power design techniques, boot/reset flows, and power management. Knowledge of design methodologies, advanced process technologies, and associated challenges. Proficiency in modeling and automation using Python, SystemC, or similar languages. ACADEMIC & EXPERIENCE REQUIREMENTS BS or MS or PhD in Electrical/Computer Engineering or related field. Proven track record in delivering architecture for high-performance, low-power SoCs. LOCATION: San Jose, California Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A global technology company is looking for a seasoned software engineer to enhance AI capabilities within their observability platform. Candidates should have a strong background in AI/ML systems, cloud computing, and robust technical leadership. This role is pivotal in driving innovation in data analysis and delivering scalable solutions. The ideal candidate will thrive in an agile environment and provide mentorship to junior engineers. Enjoy competitive salaries and benefits while contributing to impactful technology solutions. #J-18808-Ljbffr

A leading technology company in San Jose is seeking a skilled engineer to develop applications based on generative AI models such as GPT-4. This role involves collaborating with cross-functional teams to optimize performance and ensure reliability, as well as engaging in cutting-edge AI developments. The ideal candidate will have a Bachelor's or Master's degree in a relevant field and deep knowledge of machine learning methodologies. Competitive compensation, benefits, and opportunities for growth will be offered. #J-18808-Ljbffr

A leading technology company in San Jose is looking for a recent graduate or PhD candidate for an AI/ML development role. The position requires backend development skills in Go or Python and understanding of LLM infrastructure. Candidates should be ready to collaborate with cross-functional teams, optimizing models for real-world deployment. This role offers competitive salary ranges based on location, benefiting from Cisco's extensive employee perks and growth opportunities. #J-18808-Ljbffr

A leading technology firm in San Francisco is looking for an innovative engineer to develop generative AI applications. This role requires a PhD in a relevant field and backend development experience, preferably in Go or Python. You will work with cutting-edge technologies and collaborate with world-class teams to create and implement AI solutions. Cisco offers a competitive salary and a collaborative work environment that fosters growth and innovation. #J-18808-Ljbffr

A leading technology company in San Francisco is seeking a professional to develop AI/ML solutions. You will work closely with various teams to implement and optimize applications based on large language models. The ideal candidate has a Bachelor's or Master's degree in a relevant field and a strong understanding of machine learning algorithms. Join us to contribute to innovative projects and collaborate in a dynamic environment. #J-18808-Ljbffr

Foundry Services** Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. **Position Overview** The Aerospace, Defense & Government (ADG) Memory Design Application Engineer provides specialized technical support to Intel Foundry Services customers on memory compiler generation and integration challenges. This critical role ensures successful customer tape-outs by resolving complex memory IP integration issues, driving quality improvements in memory collaterals, and delivering comprehensive technical guidance on memory design methodologies for advanced semiconductor applications. **Key Responsibilities** **Memory IP Technical Support & Integration** + Provide comprehensive technical support to Intel Foundry Services customers on memory compiler generation and integration issues + Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, Memory IP providers, and EDA vendors on foundational IP integration issue resolution + Drive resolution of customer issues related to memory IP collaterals, ensuring seamless integration and optimal performance **Technical Content Development & Training** + Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams + Drive quality improvements in design kits, Memory IP collaterals, and documentation to remove barriers to successful customer design tape-outs + Develop best practice guidelines for memory integration across advanced process technologies and customer applications **Memory Design Methodology & Problem Solving** + Lead debugging and problem-solving activities in collaborative team environments + Provide technical expertise on memory compiler design, generation, and optimization + Support customers through complex memory design challenges and advanced integration requirements + Drive methodology improvements to enhance memory design productivity and reliability **Customer Engagement & Technical Excellence** + Deliver customer-facing technical support with focus on memory design and integration solutions + Ensure maximum customer satisfaction through expert guidance on memory IP implementation + Support aerospace, defense, and government customers with specialized memory requirements and security considerations **Core Competencies** + Self-driven and results-oriented with capability to effectively manage multiple complex tasks + Effective communicator with strong interpersonal and leadership capabilities, fostering collaboration across cross-functional teams and providing constructive feedback **Qualifications:** The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates **Minimum Qualifications** + US Citizenship required + Ability to obtain a US Government Security Clearance + Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study + 3+ years of experience with Memory design or Memory Compiler development and implementation **Preferred Qualifications:** + Active US Government Security Clearance with a minimum of Secret level + Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study + Proficient in common memory types, including SRAM, Register Files (RF), and ROM, with a solid understanding of CMOS digital circuit design principles + Knowledgeable in both behavioral and physical modeling of memory architectures, supporting accurate simulation and verification + Hands-on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and anti FUSE and MBIST + Experience with IP development is a strong plus + Proficient in scripting languages like Perl/Tcl/Python, and power-aware RTL and UPF flow is a plus + Experience in ASIC or SoC development **What We Offer** + Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications + Direct customer engagement and technical leadership in advanced memory design + Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio + Competitive compensation + Professional development in memory design methodologies and foundry services + Direct impact on national security through advanced memory semiconductor solutions **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Arizona, Phoenix **Additional Locations:** US, California, Santa Clara, US, Oregon, Hillsboro **Business group:** The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.