Design Verification Engineer jobs at Intel - 237 jobs

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work - and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. Northrop Grumman Defense Systems is seeking Principal/Sr. Principal Electrical Engineer. This position is located in Roy, UT and supports the Sentinel program. Job Description: Researches, develops, designs, and tests electrical components, equipment, systems, and networks. Designs electrical equipment, facilities, components, products, and systems for commercial, industrial, and domestic purposes. The selected candidate will be a contributing team member and mentor as required: Support Air Force ICBM Ground Electrical Sustainment in multiple Air Force working groups (primarily Power, Battery and Umbilical), potentially covering different engineering disciplines, according to weapon system priorities. Find, review, and develop new ideas to test and maintain aging weapon system equipment. Present rationale for needed changes and the chosen engineering approach to internal specialty engineering boards and Air Force customers. Document weapon system changes according to government and commercial standards and Air Force processes. Work and advocate changes/corrections throughout the review cycle. Support Air Force in troubleshooting and maintenance efforts on-site at missile wings and depots as required, but not typical for temporary assignments. Perform analysis of systems and historical maintenance data to provide inputs to Air Force priorities and risks. Research systems and subsystems to complete/supplement existing documentation. Prepare, review, and present materials for systems and subsystems to train individuals at or below your technical level. Support mechanical engineering working groups as required with electrical engineering specific content. Basic Qualifications: Bachelor's Degree in Electrical Engineering or an equivalent STEM related discipline (Science, Technology, Engineering or Mathematics) from an accredited university with 5 years of relevant experience, 3 years of relevant experience with a Master's degree, or 1 years of relevant experience with a PhD Can be filled one level higher, Bachelor's Degree in Electrical Engineering and 8 years of relevant experience, 6 years of relevant experience with a Master's degree, or 4 years of relevant experience with a PhD Experience in full lifecycle of electrical system development and deployment - design, test, production phases (1 year minimum) US Citizenship with an Active Secret Clearance or higher (awarded within the past 6 years) with the ability to receive a Special Access Program (SAP) certification. Proven technical writing capability and experience communicating technical and programmatic data in presentations, reviews, papers, etc. (3 years minimum) Intermediate to advanced experience and knowledge of basic Microsoft Office Products (Excel, Word, Powerpoint, Outlook, Teams, OneNote) (5 years minimum) Experience or knowledge of system engineering (1 year minimum) Experience and knowledge with using and reading engineering drawings (3 years minimum) Proven organizational skills (organized) (3 years minimum) Self motivated Works well individually and in a team environment Preferred Qualifications: Knowledge and experience with Electric Motors (AC and DC) Knowledge and design experience with Commercial Power Systems and Components, including National Electrical Code (NEC) experience Knowledge and design experience with Control Systems (PLC, sensors, transducers and similar) Knowledge and design experience with Batteries (Lead Acid, Lithium Chemistries and similar) Software programming (VBA, C, C++, Python or similar) Intermediate to advanced experience and knowledge of extended Microsoft Office Products (Visio, Project, Access) Knowledge and experience using CAD software (AutoCAD, NX, Creo, Solidworks or similar) Knowledge and experience with Cable and Wire Harness design and assembly Minuteman III Weapon System Knowledge and Experience As a full-time employee of Northrop Grumman Defense Systems, you are eligible for our robust benefits package including: - Medical, Dental & Vision coverage - 401k - Educational Assistance - Life Insurance - Employee Assistance Programs & Work/Life Solutions - Paid Time Off - Health & Wellness Resources - Employee Discounts This position's standard work schedule is a 9/80. The 9/80 schedule allows employees who work a nine-hour day Monday through Thursday to take every other Friday off. This role may offer a competitive relocation assistance package. Primary Level Salary Range: $98,400.00 - $147,600.00Secondary Level Salary Range: $122,800.00 - $184,200.00The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit *********************************** U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.

NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position offers you an outstanding opportunity to influence performance of the next generation GPU and SoC, allowing you to have real impact in a multifaceted, technology-focused company with product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence! We have crafted a team of highly motivated people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What you will be doing: Work as part of Global Circuits Team to develop various innovative IPs for hardware security, clocking, voltage regulation and silicon correlation. Own the unit and sub-system level verification of various IPs, create functional test plans, and verify using advanced verification tools, flows and methodologies. Build and reform world class verification infrastructure and methodologies to meet the unique demands of custom designed IPs. Engage in design specification development by participating in discussions on architecture, intent, and implementation of the various IPs. Enable system level integration by working with partner teams for test development & debug and delivering Verification IPs. What we need to see: BSEE (or equivalent experience) with 8+ years' experience in unit level or sub-system level verification or MS preferred in Electrical, Computer Engineering with 6+ years' experience in unit level or sub-system level verification. Proficiency with Object Oriented Programming, System Verilog, Verilog, UVM, SVA and Functional Coverage. Strong skills with VCS or equivalent simulation tools like Questa is required. Strong debugging and analytical skills are required. Have a continuous improvement mentality and passionate about delivering bug-free first silicon. Strong interpersonal skills and ability to work with on-site and remote teams is a plus. Ways to stand out from the crowd: Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies is a huge plus. Strong knowledge or work experience in Mixed signal and custom designed IPs solutions. Good understanding of behavioral real number modeling and low level digital or mixed signal design concepts. Strong knowledge or work experience in co-simulation environments such as VCS-XA or equivalent tools, Gate Level Simulation or Formal Equivalence domains. Proficiency in scripting language, such as, Perl, Tcl, Make files and automation methods/algorithms a certain plus. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until December 20, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position offers you an outstanding opportunity to influence performance of the next generation GPU and SoC, allowing you to have real impact in a multifaceted, technology-focused company with product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence! We have crafted a team of highly motivated people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What you will be doing: Work as part of Global Circuits Team to develop various innovative IPs for hardware security, clocking, voltage regulation and silicon correlation. Own the unit and sub-system level verification of various IPs, create functional test plans, and verify using advanced verification tools, flows and methodologies. Build and reform world class verification infrastructure and methodologies to meet the unique demands of custom designed IPs. Engage in design specification development by participating in discussions on architecture, intent, and implementation of the various IPs. Enable system level integration by working with partner teams for test development & debug and delivering Verification IPs. What we need to see: BSEE (or equivalent experience) with 8+ years' experience in unit level or sub-system level verification or MS preferred in Electrical, Computer Engineering with 6+ years' experience in unit level or sub-system level verification. Proficiency with Object Oriented Programming, System Verilog, Verilog, UVM, SVA and Functional Coverage. Strong skills with VCS or equivalent simulation tools like Questa is required. Strong debugging and analytical skills are required. Have a continuous improvement mentality and passionate about delivering bug-free first silicon. Strong interpersonal skills and ability to work with on-site and remote teams is a plus. Ways to stand out from the crowd: Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies is a huge plus. Strong knowledge or work experience in Mixed signal and custom designed IPs solutions. Good understanding of behavioral real number modeling and low level digital or mixed signal design concepts. Strong knowledge or work experience in co-simulation environments such as VCS-XA or equivalent tools, Gate Level Simulation or Formal Equivalence domains. Proficiency in scripting language, such as, Perl, Tcl, Make files and automation methods/algorithms a certain plus. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until December 20, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a agile team working with the best in the industry, focused on developing ASIC solutions for Meta's data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. Minimum Qualifications * Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience * 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification * 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies * Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Preferred Qualifications * Experience with revision control systems like Mercurial(Hg), Git or SVN * Experience with verification of ARM/RISC-V based sub-systems or SoCs * Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation * Experience in development of UVM based verification environments from scratch * Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle * Experience with IP or integration verification of high-speed interfaces like PCIe, RoCE, Ethernet, DDR, HBM * Experience with micro-architectural performance verification * Experience verifying GPU/CPU designs * Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs * Experience working across and building relationships with cross-functional design, model and emulation teams * Track record of 'first-pass success' in ASIC development cycles Responsibilities * Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification * Develop functional tests based on verification test plan * Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage * Debug, root-cause and resolve functional failures in the design, partnering with the Design team * Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality * Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today-beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form.

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a agile team working with the best in the industry, focused on developing ASIC solutions for Meta's data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer, Design Verification Responsibilities: 1. Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification 2. Develop functional tests based on verification test plan 3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage 4. Debug, root-cause and resolve functional failures in the design, partnering with the Design team 5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality 6. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry **Minimum Qualifications:** Minimum Qualifications: 7. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8. 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies 10. Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments **Preferred Qualifications:** Preferred Qualifications: 11. Experience with revision control systems like Mercurial(Hg), Git or SVN 12. Experience with verification of ARM/RISC-V based sub-systems or SoCs 13. Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation 14. Experience in development of UVM based verification environments from scratch 15. Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle 16. Experience with IP or integration verification of high-speed interfaces like PCIe, RoCE, Ethernet, DDR, HBM 17. Experience with micro-architectural performance verification 18. Experience verifying GPU/CPU designs 19. Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs 20. Experience working across and building relationships with cross-functional design, model and emulation teams 21. Track record of 'first-pass success' in ASIC development cycles **Public Compensation:** $146,000/year to $209,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

Reality Labs focuses on delivering Meta's vision through AI-first devices that leverage our wearable technologies. The compute performance and power efficiency requirements require custom silicon. We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable Meta's Wearable devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification 2. Develop functional tests based on verification test plan 3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage 4. Debug, root-cause and resolve functional failures in the design, partnering with the Design team 5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality 6. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry **Minimum Qualifications:** Minimum Qualifications: 7. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8. 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies 10. Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments **Preferred Qualifications:** Preferred Qualifications: 11. Experience with revision control systems like Mercurial(Hg), Git or SVN 12. Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle 13. Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch 14. Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation 15. Prior working knowledge of Audio/image/Video processing compute intensive cores **Public Compensation:** $146,000/year to $209,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

The Validation Team mandate is to ensure hardware and product requirements are met across our device portfolio. As a critical team within the Wearables devices organization that focuses on end-to-end systems validation from new product introduction, new technology introduction, product launch and post-launch testing. As a Design Verification Engineer, you will require working closely with a wide range of cross functional partners. Some of those partners include the product design and architecture teams, reliability teams and the broader core technology teams covering product architecture, sensors and display. This role will require driving unification of key validation metrics across those teams as well as developing testing and validation plans to quantify those metrics.You will be managing, developing test solutions and driving execution of mechanical tests for next generation of Wearables. You will work on overall product system validation targeting user KPI and performance of subsystems. You will work with cross-functional teams to define test plans, drive test execution and data collection. **Required Skills:** Mechanical Design Verification Engineer Responsibilities: 1. Define mechanical verification and validation methodologies for each of the different systems by working with researchers, architects and product design teams 2. Perform core function for verification of thermal, vibration, mechanical stress testing, etc 3. Define and track detailed test plans for the different modules and top-level systems 4. Define, architect, design and drive implementation of scalable test infrastructure and custom mechanical test fixtures 5. Keep track of coverage metrics and bugs encountered and resolutions 6. Own execution, interpretation and reporting of mechanical system-level verification and validation work 7. Drive FMEA, failure analysis, tolerance analysis, gauge R&R, and the GD&T activities supporting product scalability in close collaboration with process, manufacturing and REL teams 8. Perform analysis on large datasets to summarize results and clearly communicate test plans results 9. Manage external vendors for test fixture development, execution and data collection and review vendor test reports and ensure compliance with requirements 10. Travel up to 10% **Minimum Qualifications:** Minimum Qualifications: 11. 6+ years of mechanical systems verification and validation for consumer electronics or equivalent experience 12. Bachelors degree in Mechanical Engineering or equivalent experience 13. Experience with definition of verification and validation requirements 14. Experience with definition, architecture, design, and driving implementation of motion control systems and test automation 15. Experience with thermal, vibration and mechanical stress verification 16. Solid modeling software experience (Nx/SolidWorks/Creo) 17. Experience executing tests on industry standard test equipment (e.g. Instron, Thermal Chambers, DAQs, etc) 18. Experience working in cross-functional teams and consistently driving projects forward and finding opportunities to increase impact **Preferred Qualifications:** Preferred Qualifications: 19. Masters degree in Mechanical Engineering 20. C#, Python, and/or LabVIEW development experience 21. Experience in parametric MCAD design and surfacing in NX software 22. Experience with component and assembly-level tolerance analysis 23. Familiarity with design challenges introduced by optical components packaged within mechanical systems 24. Experience in the fabrication and rework of mechanical components using basic machine tools (Drill Press, Manual Milling Machine, CNC, etc) 25. Basic familiarity with Finite Element Analysis (FEA) and Computational Fluid Dynamics (CFD) simulation methods **Public Compensation:** $144,000/year to $204,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD/Xilinx programmable devices. THE PERSON: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: * Collaborate with architects, hardware and firmware engineers to understand the new features to be verified * Take ownership of block level verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes * Review functional and code coverage metrics to meet the coverage requirements * Develop and improve existing verification flows and environments PREFERRED EXPERIENCE: * Strong understanding of computer architecture and logic design * Knowledge of Verilog, system Verilog and UVM is a must * Familiarity with common security protocols and algorithms, including hashing, digital signatures, and encryption standards like AES and SHA. * Strong understanding of computer architecture and logic design * Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification * Working knowledge of C/C++ and Assembly programming languages * Exposure to scripting (python preferred) for post-processing and automation * Experience with gate level simulation, power and reset verification ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Graphic Memory Controller(GMC) is an IP that delivers into all SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for a design verification engineer in the Dram Controller IP at AMD's Santa Clara, CA Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. This is a highly visible position in a growing team. Leadership opportunity is available. We are seeking a highly skilled Formal Verification Expert to join our talented team as a Staff Engineer and technical lead. This role is crucial to ensuring IP quality through rigorous formal verification processes. THE PERSON: The successful candidate will play a key role in developing verification strategies, leading formal verification team, and collaborating across departments to ensure the highest quality standards. KEY RESPONSIBILITIES: * Lead formal verification team to ensure IP quality and project execution. * Develop and implement comprehensive formal verification plans, including constraint/assertion property development, model development, inconclusive issue resolve and sign off, etc.. * Collaborate with IP architects, hardware designer, verification engineers, and other stakeholders to design efficient formal verification strategies. * Mentor and guide junior engineers in formal verification techniques and best practices. * Communicate results and progress effectively to cross-functional teams, providing insights and actionable recommendations. * Drive continuous improvement in formal verification processes and contribute to the advancement of the organization's verification capabilities. PREFERRED EXPERIENCE: * Proven experience in formal verification and simulation, model checking, and theorem proving applied to complex IP or systems. * Proficiency in formal verification tools such as VC-Formal or JasperGoal * Strong understanding of hardware description languages (e.g., VHDL, Verilog) and/or programming languages (e.g., System verilog, C, C++, Python). ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Santa Clara, CA This role is not eligible for visa sponsorship #LI-SL3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are seeking a seasoned Lead Design Verification Engineer with expertise in verifying networking chip. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead verification teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: We are seeking an experienced and hands-on Lead Design Verification Engineer to drive the verification strategy, methodology, and execution for our next-generation high-performance networking chip. The ideal candidate will have deep expertise in SoC/ASIC verification, strong knowledge of networking protocols and architectures, and a proven ability to lead verification teams in a fast-paced environment. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: * Ownership of verification strategy for one or more major IP blocks or subsystems within a complex networking ASIC. * Architect and implement testbenches using UVM/SystemVerilog, ensuring maximum coverage and quality. * Develop and maintain test plans, coverage models, and scoreboards to ensure comprehensive verification of all design features. * Lead and mentor a team of DV engineers - drive reviews, define milestones, and ensure high-quality deliverables. * Collaborate closely with design, architecture, and software teams to define verification requirements and debug issues across the full chip. * Develop and maintain automation and regression infrastructure, including CI/CD integration. * Drive coverage closure and signoff for IP and SoC-level verification. * Contribute to methodology improvements, verification IP reuse, and best practices across the DV organization. * Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements * Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: * Proven line management experience, including hiring, mentoring, and performance management of DV engineers. * Demonstrated ability to build and lead high-performing verification teams, setting goals and driving execution across projects. * Experience with chip-level verification for networking ASICs, switches, or routers. * Familiarity with traffic generators, packet-level verification, and network protocol stacks. * Knowledge of SystemC, C testbenches, or hardware/software co-verification. * Exposure to emulation or FPGA prototyping environments (e.g., Palladium, Veloce). * Prior experience leading cross-site or multi-IP verification efforts. * Strong communication, collaboration, and leadership skills with the ability to influence technical direction across disciplines. ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in related discipline preferred LOCATION: Santa Clara, CA This role is not eligible for VISA sponsorship #LI-BW1 #LI-hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. You will participate in design verification methodology definition as well as contribute to design verification infrastructure that facilitates maximum re-use of components, improves productivity, and guarantees to the maximum extent possible, bug-free designs. THE PERSON: You have a passion for digital design and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems KEY RESPONSIBILITIES: * Collaborate with architects, hardware and firmware engineers to understand the features to be verified * Take ownership of different verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL simulations and work with HW and FW development teams to verify fixes * Review functional and code coverage metrics to meet the coverage requirements * Develop and improve existing verification flows and environments * Provide technical support to other teams PREFERRED EXPERIENCE: * Proficient in IP level ASIC verification * Experience identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills * Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE) * Working knowledge of Formal Verification methods and apps ( FPV, CC, Sequence equivalence, etc.) * Proficient in debugging firmware and RTL code using simulation tools * Proficient in using UVM testbenches and working in Linux and Windows environments * Experienced with Verilog, System Verilog, C, and C++ * Developing UVM based verification frameworks and testbenches, processes and flows * Automating workflows in a distributed compute environment. * Good understanding and hands-on experience in the UVM concepts and SystemVerilog language * Good to have : prior experience with USB / PCIE / UFS Controllers. ACADEMIC CREDENTIALS: * Bachelors or Masters degree in Computer Engineering/Electrical Engineering LOCATION: Santa Clara, Folsom, CA Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements. The engineer will be responsible for a variety of advanced verification tasks such as: verification environment development using modern verification techniques (System Verilog and UVM); designing verification components such as UVM agents, and behavioral models; implementing coverage and assertions using System Verilog; and developing random & directed test cases against the specification. This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing coverage results. Candidate must be a highly productive individual contributor with a demonstrated technical capability in system and sub-block level verification. Job Requirements: A Bachelor's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent 12+ year's relevant industry work experience. Experience in verifying designs at system level and block level. Fluent knowledge of RTL verification methodologies including System Verilog. Strong experience in ASIC design verification flows and DV methodologies Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills. Strong and independent design debugging capability. Strong verbal and written communication skills. Must be comfortable working in a team environment with verification team and design team members. Demonstrated ability to analyze and resolve complex verification trade-off scenarios. Must have legal authorization to work in the US The candidate should have expertise in some (or preferably all) of the following areas: Experience with hardware design and debug, C++/SystemC and other programming languages are a strong plus. Experience working with Emulators and FPGA based prototyping is a plus. Familiarity with overall chip design methodologies and tools Knowledge of CPU, DDR, Bus Protocol, Network Protocol or DSP design preferred Additional Job Description: Compensation and Benefits The annual base salary range for this position is $141,300 - $226,000. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Reality Labs focuses on delivering Meta's vision through AI-first devices that leverage our wearable technologies. The compute performance and power efficiency requirements require custom silicon. We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable Meta's Wearable devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement verification plans, and build test benches for block, IP, sub-system, and SoC level verification 2. Develop functional tests based on verification test plan 3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage 4. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality 5. Debug, root-cause and resolve functional failures in the design, partnering with the Design team **Minimum Qualifications:** Minimum Qualifications: 6. Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta 7. 2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies 9. Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments **Preferred Qualifications:** Preferred Qualifications: 10. Experience with revision control systems like Mercurial(Hg), Git or SVN 11. Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle 12. Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch 13. Experience verifying ARM/RISC-V based sub-systems and SoCs 14. Experience verifying CPU/GPU designs 15. Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation 16. Track record of 'first-pass success' in Application-Specific Integrated Circuit (ASIC) development cycle **Public Compensation:** $114,000/year to $172,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a team working with the best in the industry, focused on developing cutting-edge ASIC solutions for Meta's data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will be using other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer, Design Verification Responsibilities: 1. Define and implement block/IP/System on Chip (SoC) verification plans, build verification test benches to enable block/IP/sub-system/SoC level verification 2. Develop functional tests based on verification test plan 3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage 4. Debug, root-cause and resolve functional failures in the design, partnering with the Design team 5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality **Minimum Qualifications:** Minimum Qualifications: 6. Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta 7. 2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies 9. Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments **Preferred Qualifications:** Preferred Qualifications: 10. Experience with revision control systems like Mercurial(Hg), Git or SVN 11. Experience with Design verification of Data-center applications like Video, Artificial Intelligence/Machine Learning (AI/ML) and Networking designs 12. Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle 13. Track record of 'first-pass success' in Application-Specific Integrated Circuit (ASIC) development cycles 14. Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch 15. Experience with IP or integration verification of high-speed interfaces like Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR), Ethernet 16. Experience with verification of Advanced RISC Machines/Reduced Instruction Set Computing Five (ARM/RISC-V) based sub-systems or System-on-Chip (SoCs) **Public Compensation:** $114,000/year to $172,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. Meet the Team The ASIC Group works closely with other development teams within Cisco, including marketing, system hardware, software, product engineering, and manufacturing. Through this collaboration, members of our group play a major role in defining, developing and bringing new products to market across Cisco's product line. Open-minded, driven, diverse and deeply creative people at Cisco craft the hardware that makes the internet work. Bring your knowledge of computers and networking and take it to a new level in any one of the following product categories including: cloud, social, mobile/wireless, video, VoIP, collaboration, web, Internet of Things, routing, switching, IPv6, data center, HPC, TelePresence and many more. Your work will affect billions globally. Your Impact Join our award-winning ASIC team, where you'll collaborate with top industry talent to design and deliver ground breaking communications and network processing silicon. You'll contribute to system and processor architecture, high-speed logic design and verification, digital signal processing, memory and custom library development, physical design, DFT, signal integrity, and advanced packaging. Work with the latest VLSI techniques and deep submicron technologies, owning projects from concept to in-house physical implementation. Minimum Qualifications * Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelor's degree program. Familiarity with hardware description languages (HDLs), such as Verilog or VHDL. * Experience with RTL design and simulation tools (e.g., Synopsys, Cadence, Mentor Graphics). * Exposure to scripting languages (e.g., Python, Perl, TCL) for automation. * Familiarity with ASIC/SoC design flow including synthesis, place & route, and timing closure. Preferred Qualifications * Experience with ASIC verification methodologies (e.g., UVM, SystemVerilog) * Understanding of physical design and DFT (Design for Test) principles * Familiarity with Linux-based development environments * Ability to adapt to new technologies and problem-solve sophisticated engineering challenges * Excellent organizational, teamwork, and communication skills Why Cisco At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: * 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees * 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco * Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees * Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) * 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next * Additional paid time away may be requested to deal with critical or emergency issues for family members * Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: * .75% of incentive target for each 1% of revenue attainment up to 50% of quota; * 1.5% of incentive target for each 1% of attainment between 50% and 75%; * 1% of incentive target for each 1% of attainment between 75% and 100%; and * Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $94,200.00 - $137,500.00 Non-Metro New York state & Washington state: $84,000.00 - $122,200.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. **Meet the Team** The ASIC Group works closely with other development teams within Cisco, including marketing, system hardware, software, product engineering, and manufacturing. Through this collaboration, members of our group play a major role in defining, developing and bringing new products to market across Cisco's product line. Open-minded, driven, diverse and deeply creative people at Cisco craft the hardware that makes the internet work. Bring your knowledge of computers and networking and take it to a new level in any one of the following product categories including: cloud, social, mobile/wireless, video, VoIP, collaboration, web, Internet of Things, routing, switching, IPv6, data center, HPC, TelePresence and many more. Your work will affect billions globally. **Your Impact** ** ** Join our award-winning ASIC team, where you'll collaborate with top industry talent to design and deliver ground breaking communications and network processing silicon. You'll contribute to system and processor architecture, high-speed logic design and verification, digital signal processing, memory and custom library development, physical design, DFT, signal integrity, and advanced packaging. Work with the latest VLSI techniques and deep submicron technologies, owning projects from concept to in-house physical implementation. **Minimum Qualifications** ** ** + Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelor's degreeprogram.Familiaritywith hardware description languages (HDLs), such as Verilog or VHDL. + Experience with RTL design and simulation tools (e.g., Synopsys, Cadence, Mentor Graphics). + Exposure to scripting languages (e.g., Python, Perl, TCL) for automation. + Familiarity with ASIC/SoC design flow including synthesis, place & route, and timing closure. **Preferred Qualifications** ** ** + Experience with ASIC verification methodologies (e.g., UVM, SystemVerilog) + Understanding of physical design and DFT (Design for Test) principles + Familiarity with Linux-based development environments + Ability to adapt to new technologies and problem-solve sophisticated engineering challenges + Excellent organizational, teamwork, and communication skills **Why Cisco** ** ** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. **Why Cisco?** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. **Message to applicants applying to work in the U.S. and/or Canada:** Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: + 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees + 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco + Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees + Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) + 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next + Additional paid time away may be requested to deal with critical or emergency issues for family members + Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: + .75% of incentive target for each 1% of revenue attainment up to 50% of quota; + 1.5% of incentive target for each 1% of attainment between 50% and 75%; + 1% of incentive target for each 1% of attainment between 75% and 100%; and + Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $94,200.00 - $137,500.00 Non-Metro New York state & Washington state: $84,000.00 - $122,200.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements. Cisco is an Affirmative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records.

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. Meet the Team The ASIC Group works closely with other development teams within Cisco, including marketing, system hardware, software, product engineering, and manufacturing. Through this collaboration, members of our group play a major role in defining, developing and bringing new products to market across Cisco's product line. Open-minded, driven, diverse and deeply creative people at Cisco craft the hardware that makes the internet work. Bring your knowledge of computers and networking and take it to a new level in any one of the following product categories including: cloud, social, mobile/wireless, video, VoIP, collaboration, web, Internet of Things, routing, switching, IPv6, data center, HPC, TelePresence and many more. Your work will affect billions globally. Your Impact Join our award-winning ASIC team, where you'll collaborate with top industry talent to design and deliver ground breaking communications and network processing silicon. You'll contribute to system and processor architecture, high-speed logic design and verification, digital signal processing, memory and custom library development, physical design, DFT, signal integrity, and advanced packaging. Work with the latest VLSI techniques and deep submicron technologies, owning projects from concept to in-house physical implementation. Minimum Qualifications * Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelor's degree program. Familiarity with hardware description languages (HDLs), such as Verilog or VHDL. * Experience with RTL design and simulation tools (e.g., Synopsys, Cadence, Mentor Graphics). * Exposure to scripting languages (e.g., Python, Perl, TCL) for automation. * Familiarity with ASIC/SoC design flow including synthesis, place & route, and timing closure. Preferred Qualifications * Experience with ASIC verification methodologies (e.g., UVM, SystemVerilog) * Understanding of physical design and DFT (Design for Test) principles * Familiarity with Linux-based development environments * Ability to adapt to new technologies and problem-solve sophisticated engineering challenges * Excellent organizational, teamwork, and communication skills Why Cisco At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: * 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees * 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco * Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees * Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) * 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next * Additional paid time away may be requested to deal with critical or emergency issues for family members * Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: * .75% of incentive target for each 1% of revenue attainment up to 50% of quota; * 1.5% of incentive target for each 1% of attainment between 50% and 75%; * 1% of incentive target for each 1% of attainment between 75% and 100%; and * Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $94,200.00 - $137,500.00 Non-Metro New York state & Washington state: $84,000.00 - $122,200.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. **Meet the Team** The ASIC Group works closely with other development teams within Cisco, including marketing, system hardware, software, product engineering, and manufacturing. Through this collaboration, members of our group play a major role in defining, developing and bringing new products to market across Cisco's product line. Open-minded, driven, diverse and deeply creative people at Cisco craft the hardware that makes the internet work. Bring your knowledge of computers and networking and take it to a new level in any one of the following product categories including: cloud, social, mobile/wireless, video, VoIP, collaboration, web, Internet of Things, routing, switching, IPv6, data center, HPC, TelePresence and many more. Your work will affect billions globally. **Your Impact** ** ** Join our award-winning ASIC team, where you'll collaborate with top industry talent to design and deliver ground breaking communications and network processing silicon. You'll contribute to system and processor architecture, high-speed logic design and verification, digital signal processing, memory and custom library development, physical design, DFT, signal integrity, and advanced packaging. Work with the latest VLSI techniques and deep submicron technologies, owning projects from concept to in-house physical implementation. **Minimum Qualifications** ** ** + Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelor's degreeprogram.Familiaritywith hardware description languages (HDLs), such as Verilog or VHDL. + Experience with RTL design and simulation tools (e.g., Synopsys, Cadence, Mentor Graphics). + Exposure to scripting languages (e.g., Python, Perl, TCL) for automation. + Familiarity with ASIC/SoC design flow including synthesis, place & route, and timing closure. **Preferred Qualifications** ** ** + Experience with ASIC verification methodologies (e.g., UVM, SystemVerilog) + Understanding of physical design and DFT (Design for Test) principles + Familiarity with Linux-based development environments + Ability to adapt to new technologies and problem-solve sophisticated engineering challenges + Excellent organizational, teamwork, and communication skills **Why Cisco** ** ** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. **Why Cisco?** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. **Message to applicants applying to work in the U.S. and/or Canada:** Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: + 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees + 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco + Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees + Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) + 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next + Additional paid time away may be requested to deal with critical or emergency issues for family members + Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: + .75% of incentive target for each 1% of revenue attainment up to 50% of quota; + 1.5% of incentive target for each 1% of attainment between 50% and 75%; + 1% of incentive target for each 1% of attainment between 75% and 100%; and + Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $94,200.00 - $137,500.00 Non-Metro New York state & Washington state: $84,000.00 - $122,200.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements. Cisco is an Affirmative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records.

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. We are looking for a highly skilled Arithmetic Formal Verification Engineer to join our silicon design team. This role focuses on the formal verification of complex arithmetic hardware blocks, including fixed-point and floating-point datapaths. You will play a critical role in ensuring the mathematical correctness and corner-case robustness of arithmetic-intensive designs used in next-generation compute architectures. Key Responsibilities: Develop and execute formal verification strategies specifically targeting arithmetic logic units (ALUs), floating-point units (FPUs), dividers, multipliers, and custom math blocks. Develop formal verification testbenches and properties for arithmetic hardware designs. Collaborate with RTL designers to understand microarchitectural details and identify verification targets. Write and debug formal arithmetic specifications. Use formal tools (e.g., JasperGold, VC Formal, OneSpin) to prove correctness or find corner-case bugs. Analyze counterexamples and work with design teams to resolve issues. Contribute to the development of verification methodologies and best practices. Document verification plans, results, and coverage metrics. Qualifications: Minimum Qualifications: * You must possess a B.S. in Computer Engineering/ Electrical Engineering or any STEM Degree with 6+ years of experience listed below; * OR a M.S. in Computer Engineering/ Electrical Engineering or any STEM Degree with 4+ years of experience listed below; * OR a PhD in Computer Engineering/ Electrical Engineering or any STEM Degree with 6+ months of experience listed below. The experience must include the following areas: * Strong understanding of digital design fundamentals, especially arithmetic circuits (e.g., adders, multipliers, dividers, floating-point units). * Hands on experience with industry standard formal verification tools such as JasperGold, Questa Formal, VC Formal. * Experience with formal abstractions and other complexity reduction techniques. * Experience with a hardware modeling language, such as Verilog, VHDL, or System Verilog and industry standard logic simulation tools. * Experience in assertion writing, checker development, coverage analysis, failure debug, root cause analysis. Preferred Qualifications: * Knowledge of arithmetic computational formats. * Knowledge of theorem proving, model checking, or SAT/SMT solvers. * Knowledge of Intel Architecture ISA and system architecture, x86 assembly language. * Experience working in large-scale SoC or IP development environments. * Computer architecture knowledge with emphasis on out of order processor execution, memory hierarchy, and memory management. * Post-silicon debug and analysis. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, California, Folsom, US, California, Santa Clara, US, Texas, Austin Business group: The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: ********************************************************************************** Annual Salary Range for jobs which could be performed in the US: 139,710.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.