Electrical Project Engineer jobs at Intel - 357 jobs

Engineers with experience in HW emulation and prototyping required to build ASIC/System on Chip (SoC) and IP for data center applications. Responsibilities Deliver high-quality emulation and prototyping models on industry-standard emulation and prototyping platforms Design, build, and execute comprehensive emulation test plans to ensure model accuracy and support pre-silicon validation efforts Lead the development and adoption of best-in-class emulation methodologies to accelerate hardware verification and software development Collaborate with Design, DV, validation, and software teams to develop tools, flows, and mechanisms that demonstrate key performance indicators such as functionality, performance, and power efficiency Enhance and mature standard interfaces including PCIe, DDRx, USB, and other interfaces on emulation components such as speed bridges, transactors, and virtual components Continuously improve the efficiency and effectiveness of emulation components and workflows for testing, debugging, analysis, and automation Partner with vendors to troubleshoot issues, deploy new emulation capabilities, and drive ongoing improvements Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ Years of experience with EDA tools and scripting languages used to build tools and flows for complex emulation environments Experience with current emulation technologies and methods, simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods Preferred Qualifications Track record of successful ASIC/SoC where emulation is a critical workflow Experienced in compilation and build flows and creating build flows from scratch with necessary design modifications for emulation Experience in creating emulation systems for Multi-chip/SoC/IP designs and understanding of trade-offs between emulation resource consumptions, performance and ease of debug Experience managing multiple programs and enabling verification to achieve coverage closure and SW to achieve left shift of software development Experience with SystemVerilog and C++ to model RTL components and transactors Experience with post-silicon bring up, debug, and reproducing issues on emulators Experience with cadence (palladium/protium) and Synopsys (zebu) tools Experience with scripting languages such as Python, Perl and TCL Public Compensation $142,000/year to $203,000/year + bonus + equity + benefits Industry Internet Equal Opportunity Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com. #J-18808-Ljbffr

## Senior Electrical PCIe EngineerSan Jose, California, United States of America**Our vision is to transform how the world uses information to enrich life for *all*.**Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.Join our dynamic Systems Integration Group (SIG) at Micron, where we focus on developing groundbreaking semiconductor test equipment. Our team is dedicated to delivering innovative solutions that drive the future of technology!## Position Overview:As a Senior Electrical PCIe Engineer at Micron in San Jose, CA, you will play a pivotal role in crafting and verifying next-generation PCIe components. Your expertise will ensure flawless functionality of PCIe interfaces, collaborating with diverse teams to achieve world-class performance.## ## **What's Encouraged Daily:*** Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.* Develop and maintain firmware that adheres to PCIe specifications (Base, CEM, ECN).* Define device behavior at the transaction and data link layers of the PCIe stack.* Develop test plans, testbenches, and simulation environments to verify PCIe functionality.* Ensure compliance with PCIe specifications and participate in interoperability testing where needed.## ## **How To Qualify:*** BS or MS degree in Electrical Engineering or related field.* Minimum 5 years of experience in design, verification, and analysis of PCIe subsystems.* Expertise in PCIe protocols and architecture (Gen4/Gen5/Gen6).* Experience with high-speed serial interfaces including SerDes, PLL, and equalization techniques.* Knowledge of Python or other scripting languages for automation of testing and analysis.## ## **What Sets You Apart:*** Experience with other protocols such as USB, SATA, NVMe, or Ethernet.* Familiarity with PCB design and layout of high-speed digital circuits.* Linux kernel and driver knowledge.The US base salary range that Micron Technology estimates it could pay for this full-time position is:$190,500.00 - $324,000.00Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Additional compensation may include benefits, discretionary bonuses and equity.As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on .Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.To learn about your To learn more about Micron, please visit US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron's People Organization at hrsupport\_************* or ************** (select option #3) Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.AI alert**:** Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.Strong communities and education are vital to the success of both society and innovative companies. Every Micron site understands the complex needs of their local community. Whether it's through strategic giving, sponsorships or deploying team member volunteers, we are making a difference. Micron is committed to sustainable practices and supporting our global community. We are building and maintaining sustainable operations, products, and communities while focusing on opportunities and risks that are most important to our business success and stakeholders.Before submitting your CV, please review our . Micron recruiters use review tools to identify your unique skill set based on the information in your CV, and to assess how closely that skill set matches the defined skill set for open positions. While submitting your CV through this portal is not obligatory, we encourage you to do so. If you click “Submit my CV” below: 1. Our recruiting platform will use artificial intelligence to inform the recruiter of skills you may have that are not listed on your CV, based on your career history and work experience. 2. Our platform may also supplement the information provided in your CV with information obtained from publicly accessible professional-oriented sources, such as your public LinkedIn profile. 3. Our platform may highlight your application for the recruiter based on its content, the platform's analysis described above, and Micron's configuration of the skill and qualification matching software. 4. Our platform may recommend additional roles at Micron for you to consider. 5. These unique features help us ensure that we don't miss what you have to offer. They also support our efforts to eliminate bias in the hiring process. 6. If your application is unsuccessful, we'll keep your application after the close of the search so that we can match you with roles in the future and contact you about them. You can request deletion of your application at any time. **For applicants and job searchers in the European Union, Iceland, Norway, Liechtenstein, the United Kingdom or Switzerland**, if you do not want to benefit from the skill and qualification matching features described above, then you should not upload your CV through this platform. Instead, email your CV to TA\_*************** along with the Req Id number listed in the job description. Your CV will be forwarded to the appropriate recruiter for review. #J-18808-Ljbffr

Our team is responsible for designing rack power solutions covering in-rack AC/DC and DC/DC, to support our fast growing infrastructure at scale. Internally, we work closely with cross-functional teams to define the most efficient power hardware system, and to optimize for data center deployment. Externally, we work closely with industry partners, driving through the design cycle from beginning to end, ensuring high-quality product delivery. Our designs have been contributed to the Open Compute Project. Required Skills: Hardware Engineer, Power Responsibilities: Define and design rack level power systems to enable integration of a variety of IT gears into Meta data centers Work with cross-functional teams to drive product qualification full test coverage to meet product requirements and ensure product deployment Review and drive the product development with external power vendors, including in-depth design review, thorough test report review and manufacturing test coverage review. Create verification test case as needed Review circuit/PCB design, calculation and simulation Review and check bug reports Review and check manufacturing test reports Support trouble shooting and resolution for product operation issues in the field Contribute to rack level power system solution roadmap with cross-functional teams and vendor partners to ensure long term scalability of Meta power infrastructure Minimum Qualifications: Minimum Qualifications: BS in Electrical Engineering or Power Electronics 5+ years of experience in power supply design 5+ years of experience with AC-DC power conversion topologies, such as various active PFC approaches, PWM converters and resonant converters 5+ years of experience with high power redundant AC-DC power supply design and proven track of successfully delivering products into production 5+ years of experience with design tools for schematic, layout and simulation, such as Cadence, PCad, Mathcad, PSpice, or Simetrix/Simplis 5+ years of experience with product bring-up and troubleshooting skills with power supply testing methodologies 5+ years of experience developing design specifications, design guidelines, and test plans Preferred Qualifications: Preferred Qualifications: Familiar with rack level power system Familiar with digital bus design, such as I2C/PMBus, Modbus, and CANbus Familiar with safety standards and application process Familiar with power supply qualification standard and process, such as components derating, MTBF and EMC Detail oriented communication skills Experience with Data center power delivery is a plus Familiar with DC/DC power system design and evaluation is a plus Public Compensation: $139,000/year to $200,000/year + bonus + equity + benefits Industry: Internet Equal Opportunity: Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com. #J-18808-Ljbffr

Change the world. Love your job. We are seeking a highly skilled and experienced Analog and Mixed Signal Designer to drive the development of leading edge GaN and Si smart power stages, drivers and controllers, targeting the next gen solutions to power High performance computing. The ideal candidate will have a very strong analog design background, detailed familiarity with DC/DC converters and hands on experience in developing multiple power product families. Key Responsibilities: Conceptualize, design, develop and verify various mixed signal Ips associated with developing best in class power products Drive innovation in circuit design and packaging to address industry challenges in power density and thermal management associated with HPC solutions Collaborate with world-wide cross-functional teams, including layout, process technology, test engineering, and product teams Ensure designs meet technical specifications, project timelines, and quality standards Identify and mitigate design risks, ensuring robust circuit performance under process, voltage, and temperature (PVT) variations Stay updated on industry trends, emerging technologies, and best practices in HPC space Drive continuous improvement in design methodologies, tools, and workflows #J-18808-Ljbffr

A leading technology firm in California is seeking an experienced Hardware Offensive Security Manager to lead a team focusing on hardware security and penetration testing. This role involves developing strategies to uncover vulnerabilities in silicon architecture and collaborating with cross-functional teams to enhance security measures. The ideal candidate will have extensive experience in hardware security and strong leadership skills. A Master's degree in Electrical or Computer Engineering is required, with a competitive salary ranging from 224,000 to 356,500 USD. #J-18808-Ljbffr

A leading technology company in Santa Clara is seeking a Physical Design Engineer. The role involves developing chip floor plans, implementing design methodologies, and working with EDA tools. Ideal candidates hold a BSEE, MSEE or PhD and have deep knowledge in VLSI and physical design concepts. Competitive salary ranges from $96,000 to $184,000 depending on experience. Join a diverse team in a dynamic and innovative environment. #J-18808-Ljbffr

A leading technology company is seeking recent graduates for an ASIC engineering role in San Francisco. You'll be part of a dynamic team, collaborating with experts in the field to develop innovative communications and network processing solutions. Candidates should have a Bachelor's degree or be nearing completion, familiar with hardware description languages, and understand ASIC design flow. Join a company that is shaping the future of technology. #J-18808-Ljbffr

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. Make the choice to join us today.Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You will also be eligible for equity and .Applications for this job will be accepted at least until November 18, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts with the floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team to come up with an efficient clock programming sequence. The team works with the silicon solution team to triage silicon or programming bugs in the lab.**What you'll be doing:*** As a Clocks team member, you will be architecting the clock domain to satisfy functional, physical and testing design requirements.* Engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural/design/physical constraints.* Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.* Collaborate with Physical design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking.* Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams.* Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.**What we need to see:*** BS in Electrical Engineering or equivalent experience (MS preferred)* 3+ years of relevant work experience.* Deep understanding of logic optimization techniques and PPA trade-offs.* Excellent interpersonal skills and ability to collaborate with multiple teams.* Experience in RTL design (Verilog), verification and logic synthesis.* Strong coding skills in python or other industry-standard scripting languages.* Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.* Implementing on-chip clocking networks is a bonus**Ways to stand out from the crowd:*** Experience with clocks controller, clocks logic design* Understanding of system level artifacts like power, noise, etc* Experience with scalable designs and architecture.* Hands- on silicon debug is a plus.#LI-Hybrid #J-18808-Ljbffr

A leading technology company in California is seeking an ASIC Design Engineer. The role focuses on implementing and delivering high-performance RTL designs, collaborating with various teams to analyze architectural trade-offs. Candidates should have a Bachelor's degree in Electrical Engineering or equivalent, with experience in micro-architecture and RTL development. The company offers a diverse work environment and a competitive salary range, as well as equity opportunities. #J-18808-Ljbffr

A technology company in San Jose is seeking a Senior ASIC/RTL Design Engineer to contribute to the development of large SoCs. The role requires expertise in RTL ownership, complex timing constraints, and EDA tools, alongside strong communication skills. Candidates should have a Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. This is a non-remote role requiring in-person presence, and does not offer visa sponsorship. #J-18808-Ljbffr

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. Meet the Team The ASIC Group works closely with other development teams within Cisco, including marketing, system hardware, software, product engineering, and manufacturing. Through this collaboration, members of our group play a major role in defining, developing and bringing new products to market across Cisco's product line. Open-minded, driven, diverse and deeply creative people at Cisco craft the hardware that makes the internet work. Bring your knowledge of computers and networking and take it to a new level in any one of the following product categories including: cloud, social, mobile/wireless, video, VoIP, collaboration, web, Internet of Things, routing, switching, IPv6, data center, HPC, TelePresence and many more. Your work will affect billions globally. Your Impact Join our award-winning ASIC team, where you'll collaborate with top industry talent to design and deliver ground breaking communications and network processing silicon. You'll contribute to system and processor architecture, high-speed logic design and verification, digital signal processing, memory and custom library development, physical design, DFT, signal integrity, and advanced packaging. Work with the latest VLSI techniques and deep submicron technologies, owning projects from concept to in‑house physical implementation. Minimum Qualifications Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelor's degree program. Familiarity with hardware description languages (HDLs), such as Verilog or VHDL. Experience with RTL design and simulation tools (e.g., Synopsys, Cadence, Mentor Graphics). Exposure to scripting languages (e.g., Python, Perl, TCL) for automation. Familiarity with ASIC/SoC design flow including synthesis, place & route, and timing closure. Preferred Qualifications Experience with ASIC verification methodologies (e.g., UVM, SystemVerilog) Understanding of physical design and DFT (Design for Test) principles Familiarity with Linux-based development environments Ability to adapt to new technologies and problem‑solve sophisticated engineering challenges Excellent organizational, teamwork, and communication skills Why Cisco At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada Individual pay is determined by the candidate's hiring location, market conditions, job‑related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non‑exempt employees 1 paid day off for employee's birthday, paid year‑end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non‑exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full‑time employees Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non‑sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance‑based incentive pay on top of their base salary, which is split between quota and non‑quota components, subject to the applicable Cisco plan. For quota‑based incentive pay, Cisco typically pays as follows: 0.75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non‑quota‑based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $94,200.00 - $137,500.00 Non‑Metro New York state & Washington state: $84,000.00 - $122,200.00 For quota‑based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Employees in Illinois, whether exempt or non‑exempt, will participate in a unique time off program to meet local requirements. Cisco is an affirmative action and equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an ASIC Design Engineer, GPU/ML Shader Core who are motivated to challenge the status quo. If you are excited about building the next generation GPU/MI shader core, our team is on the lookout for you! You will be part of a fast-paced team working on the Graphics shader design, a team of engineers of varied disciplines who are responsible for micro-architecting, designing, and delivering GPU and ML/AI shader IP for various products. Since we are the heart of GPU engine, we strive to challenge ourselves in exceeding area, power, and performance targets. No idea is too small; we welcome every initiative that makes our product better. THE PERSON: You are an “out of the box” thinker, motivated to absorb dynamic changes and thirsty to keep innovating. You will work on the sub-block inside programmable engine aka shader core of the GPU. The shader core plays a key role in running applications program, feeding, and consuming the data to/from GPU shader resources and computing mathematical operations. Collaborate with software, architect, micro-architect and logic design team members to define and tackle “how to efficiently own an application program with the least number of instructions and data transfer while consuming the least amount of power”. Strong interpersonal skills and an excellent teammate. KEY RESPONSIBILITIES: Collaborate with block architect, ASIC designers and verification engineers to define and document block micro-architecture and analyze architectural trade-offs based on features, performance requirements and system limitations Responsible for owning full design cycle from defining micro-architecture, implementing RTL, and deliver fully verified and PD timing clean design. Consult DV engineers in describing features, outlining test plans, and closing on coverage Assist DV engineers to debug functional, performance or power test failures Work with Physical Design team to close on timing, area and power requirements PREFERRED EXPERIENCE: Experience in micro-architecture and RTL development (Verilog), focused on GPU/CPU/ML/AI pipelines, arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required. ACADEMIC CREDENTIALS: Undergraduate degree required. Bachelors or Masters degree in Computer Engineering/Electrical Engineering preferred. LOCATION: Santa Clara CA - San Diego CA - Folsom CA This role is not eligible for Visa sponsorship. Benefits offered are described: AMD benefits at a glance AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading technology company in Santa Clara seeks an experienced ASIC Design Engineer specializing in GPU/ML Shader Core. In this role, you will define micro-architecture, implement RTL, and collaborate with various engineering teams. Ideal candidates will have experience in micro-architecture and an undergraduate degree in Computer Engineering or Electrical Engineering. Enjoy a vibrant culture that fosters innovation and teamwork, while pushing the boundaries of next-generation computing. This role does not offer visa sponsorship. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD/Xilinx programmable devices. THE PERSON: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware and firmware engineers to understand the new features to be verified Take ownership of block level verification tasks Define test plans, test benches, and tests using System Verilog and UVM Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes Review functional and code coverage metrics to meet the coverage requirements Develop and improve existing verification flows and environments PREFERRED EXPERIENCE: Strong understanding of computer architecture and logic design Knowledge of Verilog, system Verilog and UVM is a must Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification Working knowledge of C/C++ and Assembly programming languages Exposure to scripting (python preferred) for post-processing and automation Experience with gate level simulation, power and reset verification ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Senior Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network‑on‑Chip (NoC), and cutting‑edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal‑based verification environments at both block and SoC‑level to achieve first‑pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre‑Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities: Lead the verification of high‑speed Crypto, Network‑on‑Chip (NoC), cutting‑edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal‑based verification environments at IP and SoC‑level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion‑based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. Proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analysed and verified system‑level Performance and QoS (Quality of Service) requirements. Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including assertion and coverage‑driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high‑performance IP and/or VLSI designs is a plus. Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate‑level simulation, power‑aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. ACADEMIC CREDENTIALS: BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. *Meet the Team* Engineering: Open-minded, driven, diverse and deeply creative people at Cisco design the hardware that makes the internet work. Bring your knowledge of computers and networking and take it to a new level in any one of the following product categories including: cloud, social, mobile/wireless, video, VoIP, big data, collaboration, web, Internet of Things, routing, switching, IPv6, data center, HPC, Telepresence and many more. Your work will impact billions globally. Supply Chain Operations: Collaborate with peers on projects that have a real-world impact. From our processes to manufacturing, you'll deliver a standout customer experience of Cisco products and services. Take your creative ideas from the drawing board to deliver powerful solutions. You'll collaborate with multi-functional teams to determine our infrastructural needs and product specifications. *Your Impact* Join our Creative Hardware Engineering team and make a tangible impact across the full product development cycle-from foundational circuit design to large system integration-seeing your contributions realized in high-volume manufacturing. Shape the product lifecycle by managing multiple priorities and advancing both immediate and long-term hardware goals. Build and sustain strong relationships with cross-functional teams while collaborating on ASIC Design and Verification for reliable, high-performance products. Drive innovation in System/Board Design, leveraging excellent communication skills to align and deliver robust hardware solutions. Apply your collaborative spirit and technical expertise to optimize Circuit Board Layout for efficiency, manufacturability, and quality. Champion Hardware Automation initiatives, working across business groups to streamline development and testing processes. Lead Validation and Test activities by fostering positive team dynamics and ensuring product excellence. Enhance Signal Integrity, coordinating with extended teams to achieve optimal speed and data fidelity in complex systems. Advance Power Design strategies, contributing to energy-efficient and sustainable hardware solutions as a trusted team player. Minimum Qualifications Currently enrolled in an undergraduate degree program in Electrical Engineering, Computer Engineering, or a related field. Foundational understanding of hardware engineering principles, including experience with hardware design and tools (e.g., Altium, Cadence, Mentor Graphics) and simulation software. Familiarity with hardware testing and debugging techniques using lab equipment such as oscilloscopes, logic analyzers, and multimeters. Strong grasp of engineering fundamentals and technical problem-solving abilities. Able to commit to a 6-month co-op program. Able to legally live and work in the country for which you're applying, without visa support or sponsorship *Preferred Qualifications* Ability to lead multiple tasks, prioritize effectively, and work toward both short- and long-term goals. Experience building and maintaining positive working relationships within diverse and extended teams. Excellent written and verbal communication skills. Proven ability to work collaboratively across business groups and teams (hardware, software, manufacturing, etc.). Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $44,000.00 - $185,000.00 Non-Metro New York state & Washington state: $44,000.00 - $185,000.00 For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements. Cisco is an Aff... (EOE statement continues) #J-18808-Ljbffr

A leading aerospace and defense company is looking for a Senior Principal Electronics Engineer - Hardware and Software Integration Lead in San Diego. This role involves leading the development of next-generation ground system solutions, managing software supplier interactions, and coordinating various engineering efforts. Candidates should have a strong background in STEM, relevant work experience, and active security clearance. The position requires on-site work but could offer hybrid options in the future. #J-18808-Ljbffr

Meet the Team The Firewall Hardware Team at Cisco is responsible for designing and developing high-performance, secure firewall hardware platforms that protect enterprise, data center, and cloud networks from evolving cyber threats. This team focuses on creating advanced hardware solutions, including FPGA-based crypto accelerators and network processing units, to deliver exceptional throughput, low latency, and robust security features. Your Impact We are looking for a skilled and proactive FPGA Design Engineer with 3+ years of industry experience to manage and implement complex digital modules. This role requires proficiency in the full FPGA development lifecycle, including independent RTL coding, verification, high-speed design practices, and debugging on hardware. The Intermediate Engineer is expected to deliver production-quality, optimized designs and contribute directly to system-level integration. Key Responsibilities include: Module Ownership and Implementation: Take ownership of complex FPGA sub-modules, from micro-architecture definition to RTL implementation using Verilog/SystemVerilog or VHDL. Design Optimization: Actively optimize designs for performance (high clock speed), area utilization, and power consumption, particularly for large, resource-intensive blocks (e.g., DSP pipelines, memory controllers). Timing Closure: Independently apply and analyze timing constraints, resolve critical timing paths, and successfully achieve timing closure for major functional blocks within the FPGA. Verification: Develop and enhance functional testbenches, verification components, and behavioral models to ensure thorough testing of assigned blocks; participate in formal design and code reviews. System Integration: Integrate developed IP cores and third-party modules (e.g., PCIe, AXI, DDR) into the top-level FPGA design; actively define interfaces between the FPGA and other system components (e.g., CPU, memory, sensors). Hardware Debugging: Lead debugging efforts during lab integration and board bring-up using advanced tools like Integrated Logic Analyzer (ILA), high-speed oscilloscopes, and logic analyzers. Scripting and Automation: Utilize Python and Tcl scripting to automate routine tasks within the synthesis/simulation flow and improve overall design efficiency. Minimum Qualifications: 3+ years of experience with a Masters' degree or 5+ years of experience with a Bachelors' degree. Experience expected to be in ASIC/FPGA design. Proficiency in end-to-end FPGA development process. Hands-on experience with EDA tools such as VCS, Spyglass, and nLint. Expertise in verifying complex blocks, clusters, and top-level designs. Practical knowledge of System Verilog constraints, structures, and classes. Familiarity with TCL and/or Python scripting for automation tasks. Preferred Qualifications: Strong domain expertise in one or more protocols, including PCIe, Ethernet, DMA, and DDR. In-depth knowledge of L2/L3/L4 networking protocols such as IPSec/DTLS, TLS, TCP/IP/UDP, and a deep understanding of cryptography technologies and algorithms such as AES-GCM/CBC, EDCHE RSA 2k, etc. A structured approach to design and effective problem-solving skills. Experience in x86 and ARM-based board design. Expertise in Ethernet interface design across various speeds (1G/10G/40G/100G/400G). Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada:The starting salary range posted for this position is $135,800.00 to $193,400.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours ofunused sick timecarried forwardfrom one calendar yearto the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $135,800.00 - $222,400.00 Non-Metro New York state & Washington state: $122,000.00 - $197,900.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Intel Integrated Photonics Solutions (IPS) is driving the future of high-speed connectivity for data centers through cutting-edge silicon photonics integration. As part of Intel's Data Center Group, we are transforming Intel from a PC-centric company into a leader powering the cloud and billions of connected devices. Since pioneering the world's first hybrid silicon laser, IPS has led the industry in scalable, high-volume manufacturing and advanced photonics development. Our mission: deliver next-generation bandwidth growth with smaller form factors, co-packaging, and speeds from 400G today to 1.6T+ tomorrow. We are seeking a Lead Analog SerDes Architect / Design Engineer to join our team and shape the future of data center connectivity. In this role, you will: + Defining circuit architecture and enabling designs meeting power, and performance for next generation optical interconnects based on system specifications. + As part of the team developing key integrated circuit components the engineer must be able to work collaboratively leading block level development. + Specify, architect and design low voltage and low power Mixed-Signal integrated circuits and work collaboratively with digital designers. + Plan design work with constraints on performance, schedule and quality. + Provide guidance to junior designers and layout engineers. + Guidance to develop test plans for post-silicon characterization. + Document all design work with review materials and detailed design descriptions. . **If you are passionate about pushing the limits and want to influence Intel's differentiation in advanced photonic development, join us and accelerate the future of data center technology,** **Qualifications:** Minimum Qualifications The ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies. - Hands-on circuit design experience of SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc. for 28Gbps+ data rates. - Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA) and modulator drivers. - Experience with design of precision analog circuits like ADC/DACs. - Experience with designing PAM4/NRZ links. - Experience with Mixed signal design flow - Experience with full-chip designs, ESDs and verification flows. Preferred Qualifications - Familiarity with Optical communications. - Experience with 400G/800G/1.6T optical links. - Experience with package/test setup design. **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, California, Santa Clara **Additional Locations:** **Business group:** At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.