Manufacturing Engineer jobs at Intel

Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below! * Life at Intel * Intel Global Diversity and Inclusion Responsibilities include, but are not limited to: * Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). * Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). * Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). * Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. * Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation. * Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. * Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. * Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high-quality integration of the IP block. * Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. * Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 4+ years of relevant experience * or - Master's degree in the same fields with 3+ years of relevant experience * or - PhD in the same fields with 6+ months of relevant experience Relevant work experience should be of the following: * Experience with DFT Array Test including MBIST or Scan/ATPG or DFT Verification Preferred Qualifications: * Expertise in Tessent DFT tool * Expertise in Primetime especially in DFT constraints * Expertise in Quality checks such as Lint, VCLP, CDC/RDC, LEC, Spyglass DFT Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Oregon, Hillsboro, US, Texas, Austin Business group: At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: ********************************************************************************** Annual Salary Range for jobs which could be performed in the US: 139,710.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Intergalactic now a part of Unison , a GE Aerospace Company, is a team of engineers, technologists, designers, mathematicians, and problem solvers committed to a singular idea: reviving the no-boundaries mentality in aerospace. We are a team of the nation's best, regardless of where we live. The Rotating Machinery Mechanical Design Engineer is key in coordinating the resources and activities required to support new designs, design reviews, detailed analysis, and work instructions to produce top of the line quality products that meet customer requirements. **Job Description** **Roles and Responsibilities** + Own design activities through life of development programs (from concept through detail design to production release). + Develop CAD 3D models and associated drawings and other documentation. + Design high speed rotating assemblies including shafts, housings, bearing cooling flow paths, seals, etc. + Support high speed bearing selection and design. + Support strategic new business opportunities and IR&D efforts including rapid iterations to at least a preliminary machine cross section + Support structural analysis team in generating deliverables such as rotor dynamics analysis and containment analysis. + Work closely with the Systems Engineer, performance engineers, aerodynamicists, structural engineers, and program team to ensure designs meet technical and program requirements. + Develop and maintain standard engineering methods and tools used to develop new designs. + Manage the development and implementation of new designs through design analysis, risk mitigation, review of safety factors & stack-ups, reliability tools, schedules, and design reviews. + Verify designs have adequate Safety Factors prior to releasing to production. Work with customer/ redesign if required to obtain producible designs. + Collaborate closely with customers to ensure product performance and integration into end platform. + Review and approve documentation for transition from prototype to production. + Provide engineering support to trouble shoot and diagnose non-performing product. + When assigned, oversee the failure analysis process providing support and final review of all reports. **Required Qualifications** + Bachelor's Degree in Mechanical Engineering or related technical field + **Must have a minimum 5 years** **experience in the mechanical layout and design of high-speed turbomachinery (speed greater than 30,000 RPM) for aerospace applications including axial fans, centrifugal blowers, centrifugal and/or mixed flow compressors, and radial inflow and axial turbines. Plus experience with designing internal machine gas paths and seals for motor and bearing cooling** + Willingness to travel up to 10% **Desired Characteristics** + Minimum 1 year of CAD experience (preferably in SolidWorks and/or NX) + Experience with PDM Vault and / or Teamcenter + Experience with Engineering Drawings utilizing GD&T + Working knowledge of key aerospace technical disciplines including mechanical design, materials, modeling/documentation, structural analysis, thermal fluid sciences, electrical systems, system controls, embedded controls, development testing and analysis, qualification analysis and testing + Understanding of aerospace requirements management methodologies and processes - traceability, verification, and validation. + Functional understanding of major aircraft systems: environmental control systems, powerplant, electrical, hydraulics, controls, avionics, power generation, and structures GE Aerospace will not sponsor individuals for employment visas, now or in the future, for this job opening. Reasonable accommodations will be made to enable individuals with disabilities to perform the following essential functions. The base pay range for this position is $120,000.00 - 190,000.00 USD Annual. The specific pay offered may be influenced by a variety of factors, including the candidate's experience, education, and skill set. This position is also eligible for an annual discretionary bonus based on a percentage of your base salary/ commission based on the plan. This posting is expected to close on July 20, 2025. GE Aerospace offers comprehensive benefits and programs to support your health and, along with programs like HealthAhead, your physical, emotional, financial and social wellbeing. Healthcare benefits include medical, dental, vision, and prescription drug coverage; access to a Health Coach from GE Aerospace; and the Employee Assistance Program, which provides 24/7 confidential assessment, counseling and referral services. Retirement benefits include the GE Aerospace Retirement Savings Plan, a 401(k) savings plan with company matching contributions and company retirement contributions, as well as access to Fidelity resources and planning consultants. Other benefits include tuition assistance, adoption assistance, paid parental leave, disability insurance, life insurance, and paid time-off for vacation or illness. GE Aerospace (General Electric Company or the Company) and its affiliates each sponsor certain employee benefit plans or programs (i.e., is a "Sponsor"). Each Sponsor reserves the right to terminate, amend, suspend, replace or modify its benefit plans and programs at any time and for any reason, in its sole discretion. No individual has a vested right to any benefit under a Sponsor's welfare benefit plan or program. This document does not create a contract of employment with any individual. \#LI-RS1 _This role requires access to U.S. export-controlled information. Therefore, employment will be contingent upon the ability to prove that you meet the status of a U.S. Person as one of the following: U.S. lawful permanent resident, U.S. Citizen, have been granted asylee or refugee status (i.e., a protected individual under the Immigration and Naturalization Act, 8 U.S.C. 1324b(a)(3))._ **Additional Information** GE Aerospace offers a great work environment, professional development, challenging careers, and competitive compensation. GE Aerospace is an Equal Opportunity Employer (****************************************************************************************** . Employment decisions are made without regard to race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, protected veteran status or other characteristics protected by law. GE Aerospace will only employ those who are legally authorized to work in the United States for this opening. Any offer of employment is conditioned upon the successful completion of a drug screen (as applicable). **Relocation Assistance Provided:** Yes \#LI-Remote - This is a remote position GE Aerospace is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, protected veteran status or other characteristics protected by law.

Production Engineers (PEs) at Meta are specialized software engineers who develop the underlying infrastructure for all of Meta's products and services, forming the backbone of every major engineering effort that keeps our platforms running smoothly and scaling efficiently.PEs work across Meta's product and infrastructure teams to ensure our services are reliable, performant, and capable of supporting billions of users. This means writing high‑quality code, solving complex problems in live production, and tackling challenges that impact over 2 billion people worldwide.Our PEs are embedded in teams across the spectrum - from products like Instagram, WhatsApp, Oculus, and Videos to critical backend services such as Storage, Cache, and Networking. The team brings together diverse levels of experience and backgrounds. Working alongside some of the best engineers in the industry, you'll contribute to code and systems that go into production and are used by millions every day. In Production Engineering at Meta, we navigate uncharted waters daily - solving problems at a scale few others face. **Required Skills:** Production Engineer Responsibilities: 1. Own back-end services which handle fleet management, front-end services such as WhatsApp / Instagram / Facebook / Meta Ads, infrastructure components that drive Meta's advances in AI, core services which are used by every team at Meta, the world's largest MySQL deployments, networking systems and everything in between 2. Write and review code, develop documentation and capacity plans, and debug the hardest problems, live, on some of the largest and most complex systems in the world 3. Together with your engineering team, you will share an on-call rotation and be an escalation contact for service incidents 4. Partner alongside the best engineers in the industry working on the coolest stuff around, the code and systems you work on will be in production and used by billions of people all around the world **Minimum Qualifications:** Minimum Qualifications: 5. 7+ years of experience in *nix (Linux or another UNIX-like OS) and Network fundamentals 6. 7+ years of coding experience in an industry-standard language (e.g. Java, Python, C++, PHP/Hack, Rust, Go) 7. Experience learning software, frameworks and APIs 8. Experience with Internet service architecture capacity planning and/or handling needs for urgent capacity augmentation 9. Knowledge of common web technologies and/or Internet service architectures (such as LAMP or MEAN stacks, CDN, Load Balancing techniques, etc.) 10. Experience configuring and running infrastructure level applications, such as Kubernetes, Terraform, MySQL, etc 11. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience **Preferred Qualifications:** Preferred Qualifications: 12. BS or MS in Computer Science **Public Compensation:** $177,000/year to $251,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

Production Engineers (PEs) at Meta are specialized software engineers who develop the underlying infrastructure for all of Meta's products and services, forming the backbone of every major engineering effort that keeps our platforms running smoothly and scaling efficiently.PEs work across Meta's product and infrastructure teams to ensure our services are reliable, performant, and capable of supporting billions of users. This means writing high‑quality code, solving complex problems in live production, and tackling challenges that impact over 2 billion people worldwide.Our PEs are embedded in teams across the spectrum - from products like Instagram, WhatsApp, Oculus, and Videos to critical backend services such as Storage, Cache, and Networking. The team brings together diverse levels of experience and backgrounds. Working alongside some of the best engineers in the industry, you'll contribute to code and systems that go into production and are used by millions every day. In Production Engineering at Meta, we navigate uncharted waters daily - solving problems at a scale few others face. **Required Skills:** Production Engineering Responsibilities: 1. Own back-end services which handle fleet management, front-end services such as WhatsApp / Instagram / Facebook / Meta Ads, infrastructure components that drive Meta's advances in AI, core services which are used by every team at Meta, the world's largest MySQL deployments, networking systems and everything in between 2. Write and review code, develop documentation and capacity plans, and debug the hardest problems, live, on some of the largest and most complex systems in the world 3. Together with your engineering team, you will share an on-call rotation and be an escalation contact for service incidents 4. Partner alongside the best engineers in the industry working on the coolest stuff around, the code and systems you work on will be in production and used by billions of people all around the world **Minimum Qualifications:** Minimum Qualifications: 5. 6+ years of experience in *nix (Linux or another UNIX-like OS) and Network fundamentals 6. 6+ years of coding experience in an industry-standard language (e.g. Java, Python, C++, PHP/Hack, Rust, Go) 7. Experience learning software, frameworks and APIs 8. Experience with Internet service architecture capacity planning and/or handling needs for urgent capacity augmentation 9. Knowledge of common web technologies and/or Internet service architectures (such as LAMP or MEAN stacks, CDN, Load Balancing techniques, etc.) 10. Experience configuring and running infrastructure level applications, such as Kubernetes, Terraform, MySQL, etc 11. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience **Preferred Qualifications:** Preferred Qualifications: 12. BS or MS in Computer Science **Public Compensation:** $147,000/year to $208,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

The Microsoft Silicon Engineering and Solutions Team within SCHIE is seeking passionate, driven and intellectually curious engineers to join our Central Front-End Tools, Flows and Methodology (TFM) group. This team drives state-of-the-art converged solutions, automation, and quality assurance checks across front-end areas like RTL & VIP Design, Design Verification, Validation, DFT, Emulation, Design Synthesis, RTL Power Anaysis, PD Handoff and SoC integration. This team supports numerous simultaneous projects within Microsoft by developing workflows and software for our design engineers so that they can deliver cutting-edge silicon solutions for Microsoft. As a Senior Front-End CAD Engineer, you'll drive the development and adoption of cutting-edge SoC and IP design methodologies, partnering with design teams across Microsoft Silicon to deliver scalable, high-performance CAD solutions. #azurehwjobs #SCHIE Responsibilities * Be part of a central FE CAD team that drives common FE methodologies for SoC and IP design. - Be the specialist in your domain and act in partnership with the execution team. - Provide leadership to the design community for the CAD domain for which you are responsible. - Work with stakeholders across the Microsoft Silicon group to collect TFM requirements. - Develop, enhance, and integrate common design and verification IP for organization-wide use. - Work with EDA vendors to adopt the most optimal solutions for silicon verification and design. - Embody our culture and values. Qualifications Required Qualifications: * Bachelor's Degree in Computer Science or related technical field AND 4+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python * OR equivalent experience. * Experience with hand-off to backend and Logic Design compilation, elaboration in addition to experience in Low Power design. * 5+ years of experience in digital design or CAD flows/tools development in this area. - Well-rounded and familiar with most Front-End Tools, Flows and Methodologies. * Experienced writing scripts/software with industry standard languages like Python, TCL, Perl, C/C++ or Java (Python preferred) Other Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: * Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. Preferred qualifications: * Master's Degree in Computer Science or related technical field AND 6+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR Bachelor's Degree in Computer Science or related technical field AND 8+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience. * 10+ years of relevant experience. * Expertise in CPU/SoC design principles. * For Front-End Handoff CAD Roles: - In-depth knowledge of Front-End workflows, methodologies, and best practices. * Ability to design and verify reusable design components. * Expertise in Synthesis and Timing Constraints. Exposure to tools Timevision, Fishtail, Formality/LEC, Genus, Fusion Compile. * Expertise in RTL power/UPF linting flows like Power Artist/Jules, VCLP. - Expertise in RTL filelist generation, SoC connectivity, integration. * Hands on experience with RTL2PD handoff process. - Expertise in one of the following areas: * Design compile, elaboration and filelist/libraries handling. * Design release packaging and qualification, RTL quality flows, static checks. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form. Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work. #azurehwjobs #SCHIE #HIFE #MSCareerEvents25 Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: **************************************************** This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

We are seeking a candidate for a key leadership role in scheduling for a portfolio of Data Center projects of strategic importance to Meta. The Schedule lead will act as a technical Schedule subject matter expert overseeing all schedule management and reporting for their portfolio of projects. The successful candidate will have focus on speed to market and be a critical partner for the Delivery Team and the Project Controls Lead to forecast and help mitigate schedule related risks and issues on the project, enable commercial accountability, manage schedule health reporting/escalation, and ensure that schedule change management is effective and expedient. Leadership, communication, and organization skills are a must in this highly collaborative, analytical, and strategic role. This position will work closely within the DEC Technical Operations team and various internal departments including Site Project Management teams, Pre-Construction, Contracts, Finance, Accounting, Sourcing and Operations Engineering. **Required Skills:** Area Schedule Lead - Data Center Design, Engineering and Construction Responsibilities: 1. Responsible for end to end schedule coordination and updates, including interface with risk management and pro-active communication of updates and alignment of variance root cause/commentary with Cross-functional partners 2. Identifies, documents, and communicates schedule risks through defined processes, including Risk Registers, health reviews, and New Build Program management meetings 3. Accountable for all aspects of vendor and Contractor schedule management 4. Accountable for Contractor baseline schedule development and evaluation during pre-con, including ensuring adherence to program guidance and specifications. Will lead efforts to optimize schedules for speed to market and successful on-time-delivery 5. Responsible for application of commercial entitlement for contractor Extensions Of Time (EOT) for their designated portfolio of projects. Provide leadership to site teams for Delay Tracking, EOT requests and claims. Responsible for making recommendations that are in line with contract and escalating when site decisions differ from the contractual or program guidance 6. Lead the identification and application of Proactive Risk Indicators in sub-area and ensure all risks are properly escalated to Health Reviews, and other appropriate forums. Lead ad-hoc schedule analysis to support program as required 7. Lead a small team of consultants (if required) to support effective schedule management for the designated portfolio of projects 8. Approximately 50% travel to other Data Center sites within the Area and home office **Minimum Qualifications:** Minimum Qualifications: 9. 10+ years of Planning, Scheduling, Construction Management, or Related field experience 10. Bachelor's degree in Engineering, Construction Management, or Equivalent Technical Field or related field experience 11. Subject Matter Expert in Primavera P6 and other scheduling related methodologies and software 12. Experience developing/managing an Owner's planning/scheduling program 13. Familiar with Data Center, Infrastructure or Construction programs requiring complicated commissioning specifications 14. Demonstrated analytical, communication, problem solving, prioritization, organization and reporting skills 15. Experience leading complex project or program planning and coordination amongst a large group of internal and external project stakeholders 16. Demonstrated experience developing and driving actions or operational adjustments based on schedule or project controls performance metrics 17. Demonstrated experience partnering with cross-functional teams to influence strategic direction **Preferred Qualifications:** Preferred Qualifications: 18. Experience identifying schedule efficiencies and driving programmatic or organizational alignment in changing execution strategies to optimize schedule performance 19. Experience negotiating schedule changes or complex construction claims 20. Successful development and implementation of scheduling or project controls strategies in a large organization 21. Familiar with complex networking systems and electrical infrastructure 22. Experience managing a team of Contingent Worker Schedulers **Public Compensation:** $144,000/year to $201,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

We are seeking a candidate for a key role in scheduling for a portfolio of Data Center projects of high strategic importance to Meta. The Schedule Lead will act as a technical Schedule subject matter expert, overseeing all schedule management and reporting for their portfolio of projects. You will focus on speed to market and be a critical partner for the Delivery Team and the Project Controls Lead to forecast and help mitigate schedule-related risks and issues on the project, enable commercial accountability, manage schedule health reporting/escalation, and ensure that schedule change management is effective and expedient. This position will work closely with the DEC (Design, Engineering, and Construction) Technical Operations team and various internal departments, including Site Project Management teams, Pre-Construction, Contracts, Finance, Accounting, Sourcing, and Operations Engineering. **Required Skills:** Area Schedule Lead - Data Center Design, Engineering and Construction Responsibilities: 1. Responsible for End to End schedule coordination and updates, including interface with risk management and pro-active communication of updates and alignment of variance root cause/commentary with cross- functional partners 2. Identifies, documents, and communicates schedule risks through defined processes, including Risk Registers, health reviews, and New Build Program management meetings 3. Accountable for all aspects of vendor and Contractor schedule management 4. Accountable for Contractor baseline schedule development and evaluation during pre-construction, including ensuring adherence to program guidance and specifications. Will lead efforts to optimize schedules for speed to market and successful on-time-delivery 5. Responsible for application of commercial entitlement for contractor Extensions Of Time (EOT) for their designated portfolio of projects. Provide leadership to site teams for Delay Tracking, EOT requests and claims. Responsible for making recommendations that are in line with contract and escalating when site decisions differ from the contractual or program guidance 6. Lead the identification and application of Proactive Risk Indicators in sub-area and ensure all risks are properly escalated to Area Heath Reviews and other appropriate forums. Lead ad-hoc schedule analysis to support program as required 7. Lead a small team of consultants (if required) to support effective schedule management for the designated portfolio of projects 8. Approximately 50% travel to other Data Center sites within the Area and home office **Minimum Qualifications:** Minimum Qualifications: 9. 10+ years of Planning, Scheduling, Construction Management, or Related field experience 10. Bachelor's degree in Engineering, Construction Management, or Equivalent Technical Field or related field experience 11. Subject Matter Expertise in Primavera P6 and other scheduling related methodologies and software 12. Experience developing/managing an Owner's planning/scheduling program 13. Experience within Data Center, Infrastructure or Construction programs requiring complicated commissioning specifications 14. Demonstrated analytical, communication, problem solving, prioritization, organization and reporting skills 15. Experience leading complex project or program planning and coordination amongst a large group of internal and external project stakeholders 16. Demonstrated experience developing and driving actions or operational adjustments based on schedule or project controls performance metrics 17. Demonstrated experience partnering with cross-functional teams to influence strategic direction **Preferred Qualifications:** Preferred Qualifications: 18. Experience identifying schedule efficiencies and driving programmatic or organizational alignment in changing execution strategies to optimize schedule performance 19. Experience negotiating schedule changes or complex construction claims 20. Successful development and implementation of scheduling or project controls strategies in a large organization 21. Familiar with complex networking systems and electrical infrastructure 22. Experience managing a team of Contingent Worker Schedulers **Public Compensation:** $122,000/year to $169,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

We are seeking a candidate for a key role overseeing our Contingent Workforce of Project Schedulers. Leadership, communication, and organization skills are important in this highly collaborative, analytical, and strategic role. This position will work closely within the DEC (Design, Engineering and Construction) Business Controls team and various internal departments including Site Project Management teams, Pre-Construction, Contracts, Finance, Accounting, Sourcing and Operations Engineering. **Required Skills:** Area Schedule Lead - Data Center Design, Engineering and Construction Responsibilities: 1. Oversee Contingent Worker schedulers on our dual sites. Review the schedule health reports produced by CW schedulers on site and provide feedback to CW account leads as required 2. Responsible for application of commercial entitlement for schedule. Provide leadership to site teams and CW Schedulers for Delay Tracking, Extension of Time (EOT) requests and claims and coordinate the change evaluation in collaboration with the cost team. Responsible for making recommendations that are in line with contract and escalating when site decisions differ from the contractual or program guidance 3. Support Precon team in ensuring that the GC/TC establishes a baseline that is aligned with precon estimates, and one that can be used as a true target schedule as the job progresses. Ensure all Baseline Expectations are meet and escalate appropriately if Schedule does not meet the revised checklist or DIV1 Spec 4. Accountable for maintaining Integrated Master Schedule (IMS) including reporting to site team, leadership and cross-functional partners 5. Lead the identification and application of Proactive Risk Indicators (Project Kronos) on site and ensure all risks are properly escalated on AHRs and other leadership functions. Collaborate with site teams on schedule mitigation strategies. Track implementation of GC/TC Quality Checklist and End of month Communications 6. Work through any XFN schedule coordination challenges with ISCE, IDC and other partners. Ensure Alignment on each site between Scheduling Team and Cost team at the project level **Minimum Qualifications:** Minimum Qualifications: 7. 10+ years of construction schedule experience 8. Experience with P6 (Primavera 6) and Excel 9. BA/BS in construction management, finance, business or equivalent **Preferred Qualifications:** Preferred Qualifications: 10. 5+ years data center experience **Public Compensation:** $122,000/year to $169,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

Meta is seeking a Research Engineer to join our Large Language Model (LLM) Research team. We conduct focused research and engineering to build state-of-the-art LLMs, which we often open-source, like our team's recent Llama 2. We are looking for strong engineers who have a background in generative AI and NLP, with experience in areas like language model evaluation; data processing for pre-training and fine-tuning; responsible LLMs; LLM alignment; reinforcement learning for language model tuning; efficient training and inference; and/or multilingual and multimodal modeling. **Required Skills:** Research Engineer, Language - Generative AI Responsibilities: 1. Design methods, tools, and infrastructure to push forward the state of the art in large language models 2. Define research goals informed by practical engineering concerns 3. Contribute to experiments, including designing experimental details, writing reusable code, running evaluations, and organizing results 4. Adapt standard machine learning methods to best exploit modern parallel environments (e.g. distributed clusters, multicore SMP, and GPU) 5. Work with a large and globally distributed team 6. Contribute to publications and open-sourcing efforts **Minimum Qualifications:** Minimum Qualifications: 7. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8. Research experience in machine learning, deep learning, and/or natural language processing 9. Experience with developing machine learning models at scale from inception to business impact 10. Programming experience in Python and hands-on experience with frameworks such as PyTorch 11. Exposure to architectural patterns of large scale software applications **Preferred Qualifications:** Preferred Qualifications: 12. A PhD in AI, computer science, data science, or related technical fields. 13. Master's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 14. First author publications at peer-reviewed AI conferences (e.g., NeurIPS, CVPR, ICML, ICLR, ICCV, and ACL). 15. Direct experience in generative AI and LLM research. **Public Compensation:** $85.10/hour to $251,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click "Apply to Job" online on this web page. **Required Skills:** Capacity Planning Engineer Responsibilities: 1. Own infrastructure supply chain planning for Meta (as part of Meta's overall capacity plan): including servers, network, and data center equipment from components to finished goods. 2. Design improvements to software systems to improve supply chain planning efficiency and quality, partner with software engineers to implement and contribute code yourself. 3. Develop and analyze business and technical data and scenarios to drive executive decisions around infrastructure supply and spend. 4. Contribute to end-to-end supply chain planning processes (as part of Meta's overall capacity plan), methodologies, and data to deliver an executable and optimized supply plan. 5. Manage and resolve critical escalations and exceptions in all areas of the supply chain. 6. Critique demand signals curated by upstream teams, and build an anticipatory demand view for ISCE through mathematical modeling and business judgement. 7. Influence and interweave technology strategy and transitions into planning models. 8. Develop and code models that drive supply flexibility and optionality to best balance delivery of required capacity, cost, and risk. 9. Build mathematical models to perform simulation and optimization studies of demand projections, scenario planning, and gap closure analysis while balancing constraints, product mixes and inventory costs. 10. Work cross-functionally to define problem statements, collect data, build analytical models and make recommendations to drive change and optimization at the most strategic levels. 11. Partner across Infra - platform teams, server hardware engineering, network engineering, data center engineering, operations, capacity planning, networking planning, data center planning, energy - to find the most optimal ways to build and scale our Infrastructure. 12. Partner with Finance to balance cost efficiency with technical, product and supply chain considerations. 13. Telecommute from anywhere in the U.S. permitted. 14. Domestic and International travel required between 10-20%. **Minimum Qualifications:** Minimum Qualifications: 15. Master's degree (or foreign degree equivalent) in Supply Chain Management, Computer Science, Computer Engineering, Electrical Engineering, Industrial Engineering, or a related field and 5 years of work experience in the job offered or related occupation 16. Requires 5 years in the following skills: 17. Designing and implementing models and optimization algorithms 18. Experience in supply chain management - planning, manufacturing, operations, inventory, etc 19. Experience working with distributed systems at scale 20. Experience in supply chain planning optimization 21. Experience working with cross-functional teams 22. Experience transforming business systems, models, and achieving results relative to goals, AND 23. Interfacing with internal & external partners in an entrepreneurial and cross-functional environment, requiring a latitude for independent judgment while coordinating people and technical resources **Public Compensation:** $151,502/year to $196,020/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

Drive quality for assigned suppliers, including quality plan implementation. Select suppliers through qualification processes. Own supplier results, drive improvements utilizing supplier scorecards. Own supplier audits, ensuring compliance, and driving improvement plans where needed. In-depth understanding of key business drivers; uses this understanding to accomplish own work. In-depth understanding of how work of own team integrates with other teams and contributes to the area. **Job Description** **Roles and Responsibilities** + Includes both Supplier Quality Assurance and Supplier Quality Development. Includes supplier qualifications, action plans, audits, performance monitoring, and assisting key suppliers towards industrial standards of excellence. SQEs have various levels of differentiation which are related to level of technical understanding of engineering drawings and ability to manage vendors. + Developing in-depth knowledge of a discipline. Uses prior experience and acquired expertise to execute functional policy/strategy. + A job at this level is likely to be an individual contributor, with proven interpersonal skills. Communication with direct colleagues and the business about design and coordination services rendered. Provides informal guidance to new team members. Explains complex information to others in straightforward situations. + Impacts projects, processes and procedures in own field. The role operates with some autonomy, but is focused on execution of activities/provision of advice within an enabling discipline covered by standard functional practices and procedures. Activities require professional judgment, but may require more senior levels of guidance. + Utilizes technical expertise and judgement to solve problems. Leverages technical skills and analytic thinking required to solve problems. May use multiple internal sources outside of own team to arrive at decisions. **Required Qualifications** + Bachelor's degree from an accredited college or institution (OR a high school diploma / GED with a minimum of 4 years' experience in supplier quality) A minimum of 3 years in Supplier Quality **Desired Characteristics** + Past experience in Machining or Welding processes and product + Ability to document, plan, market, and execute programs. + Established project management skills. + Background in supplier quality and supplier management + Experience managing quality or manufacturing teams + Strong interpersonal and leadership skills + Demonstrated ability to analyze and resolve problems + Humble: respectful, receptive, agile, eager to learn + Transparent: shares critical information, speaks with candor, contributes constructively + Focused: quick learner, strategically prioritizes work, committed + Leadership ability: strong communicator, decision-maker, collaborative + Problem solver: analytical-minded, challenges existing processes, critical thinker GE Aerospace offers comprehensive benefits and programs to support your health and, along with programs like HealthAhead, your physical, emotional, financial and social wellbeing. Healthcare benefits include medical, dental, vision, and prescription drug coverage; access to a Health Coach from GE Aerospace; and the Employee Assistance Program, which provides 24/7 confidential assessment, counseling and referral services. Retirement benefits include the GE Aerospace Retirement Savings Plan, a 401(k) savings plan with company matching contributions and company retirement contributions, as well as access to Fidelity resources and planning consultants. Other benefits include tuition assistance, adoption assistance, paid parental leave, disability insurance, life insurance, and paid time-off for vacation or illness. GE Aerospace (General Electric Company or the Company) and its affiliates each sponsor certain employee benefit plans or programs (i.e., is a "Sponsor"). Each Sponsor reserves the right to terminate, amend, suspend, replace or modify its benefit plans and programs at any time and for any reason, in its sole discretion. No individual has a vested right to any benefit under a Sponsor's welfare benefit plan or program. This document does not create a contract of employment with any individual. The base pay range for this position is $94,400-$125,900 The specific pay offered may be influenced by a variety of factors, including the candidate's experience, education, and skill set. This position is also eligible for an annual discretionary bonus based on a percentage of your base salary/ commission based on the plan. This posting is expected to close on **November 30, 2025.** _This role requires access to U.S. export-controlled information. Therefore, employment will be contingent upon the ability to prove that you meet the status of a U.S. Person as one of the following: U.S. lawful permanent resident, U.S. Citizen, have been granted asylee or refugee status (i.e., a protected individual under the Immigration and Naturalization Act, 8 U.S.C. 1324b(a)(3))._ **Additional Information** GE Aerospace offers a great work environment, professional development, challenging careers, and competitive compensation. GE Aerospace is an Equal Opportunity Employer (****************************************************************************************** . Employment decisions are made without regard to race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, protected veteran status or other characteristics protected by law. GE Aerospace will only employ those who are legally authorized to work in the United States for this opening. Any offer of employment is conditioned upon the successful completion of a drug screen (as applicable). **Relocation Assistance Provided:** No \#LI-Remote - This is a remote position GE Aerospace is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, protected veteran status or other characteristics protected by law.

We are now looking for a CPU Design Methodology Engineer! The complexity of chip development has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate about developing methodologies and automation solutions that enable SOC creation in the most optimized way. In this position, you will get the chance to build complex chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams. What you'll be doing: Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them Own front-end design quality checks and reviews to present the physical design team with high-quality RTL What we need to see: A Masters in Computer or Electrical Engineering or equivalent experience 5+ years of experience in chip design, specializing in SOC integration and design automation Excellent analytical and problem-solving skills Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation Strong coding skills in Perl, Python, or other industry-standard scripting languages Experience in synthesis and physical design is a plus Good interpersonal skills. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We employ some of the most forward-thinking and hardworking people in the world. Are you passionate about becoming a part of an outstanding team supporting the latest in CPU technology? If so, we want to hear from you. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until November 22, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

We are looking for a Senior CPU Design Engineer! NVIDIA is seeking best-in-class CPU Design Engineers to design the world's leading CPUs. This position offers you the opportunity to have a real impact in a dynamic, technology-focused company, designing for product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. We have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The NVIDIA CPU team is looking for inquisitive, motivated engineers with design experience to build ground-breaking CPUs. As a senior member of our design team, you will be responsible for the micro-architecture, design and implementation of high-performance, low power CPUs. You will work closely with fellow design engineers, architects, verification engineers, and physical design engineers to accomplish your tasks. What you will be doing: Drive the micro-architecture definition, feasibility studies and documentation of CPU sub-systems. Implement in RTL and coordinate execution with the verification team to ensure that the design is functional. Exercise logic design skills to optimize and meet performance, timing and power targets. Deliver a synthesis/timing clean design while working with the physical design team ensuring a routable and physically implementable design. Support hardware engineering activities including chip floor plan, power/clock distribution, chip assembly, timing closure, power and noise analysis, and back-end verification. Develop flows and tools as necessary in support of design activities. What we need to see: BS or MS in electrical engineering or computer engineering (or equivalent experience). 8+ years of proven experience in micro-architecture and RTL development of complex, high speed designs, ideally in CPU subsystems. Exposure to Computer Architecture and Digital Systems design. Highly proficient in logic design, Verilog and/or SystemVerilog, with a deep understanding of physical design and VLSI. Strengths in scripting languages such as Perl, Python. Good communication and interpersonal skills. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We employ some of the most forward-thinking and hardworking people in the world. Are you passionate about becoming a part of an outstanding team supporting the latest in CPU technology? If so, we want to hear from you. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until September 19, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This position will require the creation of integrated circuit (IC) layouts from start to finish. Using Cadence design software, you will floorplan, design, implement and verify analog integrated circuits while meeting schedule requirements. THE PERSON: We are seeking a skilled professional mid level Mask Design Engineer who has created mixed-signal, analog layout designs. Excellent problem-solving skills, attention to detail, and the ability to work independently or in a team, along with strong communication skills for creating layout designs and collaborating with stakeholders. KEY RESPONSIBILITIES: * Perform physical layout for custom analog structures in state-of-the-art sub-micron CMOS technologies using Cadence tools. * Assist in taking part in floor planning, LEF delivery, custom layout, and verifying all applicable design rules. * Perform power robustness check and EMIR verification and fixes. * Work closely with design engineers to achieve optimal circuit performance and produce high-quality layout designs. * Influence other layout designers to improve team efficiency and align design methodology. * Troubleshoot and resolve complex technical issues, ensuring high quality layout. * Work with other mask designers across AMD's many global sites to macro completion. * Effectively work in a team, good interpersonal skills, passion, and positive energy. PREFERRED EXPERIENCE: * Experience with layout design and verification tools such as Calibre verification and Cadence design tools. * Verifying design integrity through DRC, LVS, ERC, PERC, LUP and ESD, EMIR, timing, Antenna, and DFM across all major foundry processes. * Must have a deep understanding of analogue circuit layout concepts in submicron CMOS technologies, device matching, shielding, etc. * Excellent problem-solving and critical thinking skills, able to make decisions independently. * Familiarity with foundry command deck, PDK, fabrication & mask process. * Proven record of completing tasks on time or ahead of schedule while maintaining quality. ACADEMIC CREDENTIALS: * No degree requirements but would need to be senior level in mask design experience. LOCATION: Portland, OR #LI-SC3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This position will require the creation and management of integrated circuit (IC) layouts from start to finish. Using Cadence design software, you will floorplan, design, implement and verify analog integrated circuits while meeting schedule requirements. THE PERSON: We are seeking a skilled professional senior level Mask Design Engineer who has created mixed-signal, analog layout designs. Excellent problem-solving skills, attention to detail, and the ability to work independently or in a team, along with strong communication skills for creating layout designs and collaborating with stakeholders. KEY RESPONSIBILITIES: * Perform physical layout for custom analog structures in state-of-the-art sub-micron CMOS technologies using Cadence tools. * Assist in taking part in floor planning, LEF delivery, custom layout, and verifying all applicable design rules. * Perform power robustness check and EMIR verification and fixes. * Work closely with design engineers to achieve optimal circuit performance and produce high-quality layout designs. * Lead and influence other layout designers to improve team efficiency and align design methodology. * Troubleshoot and resolve complex technical issues, ensuring high quality layout. * Mentor and lead other mask designers across AMD's many global sites to macro completion. * Effectively work in a team, good interpersonal skills, passion, and positive energy. PREFERRED EXPERIENCE: * Experience with layout design and verification tools such as Calibre verification and Cadence design tools. * Verifying design integrity through DRC, LVS, ERC, PERC, LUP and ESD, EMIR, timing, Antenna, and DFM across all major foundry processes. * Must have a deep understanding of analogue circuit layout concepts in submicron CMOS technologies, device matching, shielding, etc. * Excellent problem-solving and critical thinking skills, able to make decisions independently. * Solid understanding of analog layout and all design requirements. * Knowledge of foundry command deck, PDK, fabrication & mask process. * Must have design management techniques to ensure quality and meet schedules. * Proven record of completing tasks on time or ahead of schedule while maintaining quality. ACADEMIC CREDENTIALS: * No degree requirements but would need to be senior level in mask design experience. LOCATION: Portland, OR #LI-SC3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This position will require the creation and management of integrated circuit (IC) layouts from start to finish. Using Cadence design software, you will floorplan, design, implement and verify analog integrated circuits while meeting schedule requirements. THE PERSON: We are seeking a skilled professional senior level Mask Design Engineer who has created mixed-signal, analog layout designs. Excellent problem-solving skills, attention to detail, and the ability to work independently or in a team, along with strong communication skills for creating layout designs and collaborating with stakeholders. KEY RESPONSIBILITIES: * Perform physical layout for custom analog structures in state-of-the-art sub-micron CMOS technologies using Cadence tools. * Assist in taking part in floor planning, LEF delivery, custom layout, and verifying all applicable design rules. * Perform power robustness check and EMIR verification and fixes. * Work closely with design engineers to achieve optimal circuit performance and produce high-quality layout designs. * Lead and influence other layout designers to improve team efficiency and align design methodology. * Troubleshoot and resolve complex technical issues, ensuring high quality layout. * Mentor and lead other mask designers across AMD's many global sites to macro completion. * Effectively work in a team, good interpersonal skills, passion, and positive energy. PREFERRED EXPERIENCE: * Experience with layout design and verification tools such as Calibre verification and Cadence design tools. * Verifying design integrity through DRC, LVS, ERC, PERC, LUP and ESD, EMIR, timing, Antenna, and DFM across all major foundry processes. * Must have a deep understanding of analogue circuit layout concepts in submicron CMOS technologies, device matching, shielding, etc. * Excellent problem-solving and critical thinking skills, able to make decisions independently. * Solid understanding of analog layout and all design requirements. * Knowledge of foundry command deck, PDK, fabrication & mask process. * Must have design management techniques to ensure quality and meet schedules. * Proven record of completing tasks on time or ahead of schedule while maintaining quality. ACADEMIC CREDENTIALS: * No degree requirements but would need to be senior level in mask design experience. LOCATION: Portland, OR #LI-SC3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Embark with us on a journey of growth and transformation as we create exceptionally engineered technology and bring AI everywhere. As a valued team member, your adaptability and attention to detail will contribute to our drive for results and relentless pursuit of quality, ensuring we meet our customers' needs with precision. Join us and build on our legacy of innovation and collaboration as we deliver world-changing technology that improves the life of every person on the planet. As a **Lithography Supply Chain Engineer** , you will: + Supports management/senior leadership to incorporate process and quality improvements in Intel's supply chain and logistics strategy. + Defines material inspection methodology, conducts studies related to cost control, process control, and production yield, and implements plans and programs to optimize supply chain. + Supports product long range plan development by defining next generation methodology capabilities to support Intel's supply chain roadmap. + Explores and benchmarks emerging technology in the industry. + Contributes to Intel's future technology definition and requirements. + Highlights gaps between roadmap strategy, manufacturing capability, and market demands and recommends solutions to addresses those gaps. + Tracks supply demand trends, conducts root cause analysis to find opportunities for process and quality improvements, and collaborates with supply chain leads to implement solutions. + Leads supplier selections for new business in partnership with commodity managers and technical/quality partners and drives product and purchase specification content to ensure commodity performance compliance. + Performs alternate sourcing risk mitigation for single sourced commodities. + Establishes control standards, determines KPIs, monitors performance against targets, and drives root cause analysis for supply chain issues to arrive at solutions. + Drives supplier process window validation activities on critical process modules through all stages of development. + Drives supplier improvements on quality, reliability, yield, and cost. + Maintains quality standards and systems, creating relevant specifications to minimize variability and subjectivity to align with operational capability requirements. + Leads quality excursion management and drives failure mode analysis with suppliers. **Qualifications:** You must possess the below minimum qualifications to be initially considered for this position. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience. **T** **his position is not eligible for Intel immigration sponsorship.** **Minimum Qualifications:** **Education** : Bachelor's or Master's degree in Chemistry, Chemical Engineering, Physics, or Materials Science or related fields. 6+ years of relevant **experience** in: + Factory Operations or Support Group Work + Lithography Processes + FMEA, SPC, PCSA, and 8D **Preferred Qualifications:** + PhD in relevant technical field + Prior experience working with and/or managing suppliers + Strong analytical skills and the ability to work effectively in ambiguous situations. + Experience in supply chain or supplier management, particularly with suppliers based in Asia. **Interview Tips** here. (********************************************************* By applying to this posting your resume and profile will become visible to Intel Recruiters and will allow them to consider you for current and future job openings aligned with the skills and positions mentioned above. **Intel Benefits:** ********************************************************** **Life Inside Intel:** *************************************************************** **Interviewing Tips:** ******************************************************** **Intel's core values:** **************************************************************************************************** **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Oregon, Hillsboro **Additional Locations:** US, Arizona, Phoenix **Business group:** Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits:** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: ********************************************************************************** Annual Salary Range for jobs which could be performed in the US: 136,990.00 USD - 193,390.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

**Do Something Wonderful!** Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and have a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. **Who We Are** You will be a part of a high performing team specializing in clocking architecture, clock distribution network design, custom clock circuits, clock tree synthesis, and low power design for Intel's flagship IA cores in the most advanced process nodes. **Who You Are** Your responsibilities will include but not be limited to: + Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. + Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. + Conducts verification and signoff include formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. + Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. + Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. + Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. + Optimizes CPU design to improve product level parameters such as power, frequency, and area. + Participates in the development and improvement of physical design methodologies and flow automation. + Good understanding with fundamentals of static timing analysis, clock related timing parameters, EM, IR, Place and Route flows. + Strong understanding of sub-micron process technology and circuits. + Excellent written and communication skills + Works well independently and develops quick engineering solutions for complex problems + Skilled at interfacing with engineers and managers by providing schedule updates + High problem-solving skills and good tolerance for ambiguity + Knows how to prioritize tasks independently + Natural focus on quality, discipline, and accurate results for engineering customers + Contributes and works well in a multi-site team setting **Qualifications:** You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. **Minimum Qualifications** + The ideal candidate must have a Master's Degree in Electrical Engineering, Computer Engineering related STEM field with 3+ years of experience listed below: + Backend design and/or integration on leading edge process nodes + Perl, TCL, or other industry-standard scripting languages High frequency clock distribution design and implementation, custom circuits and clock tree synthesis. **Preferred Qualifications** + Experience with computer architecture + Experience with IA-32 assembly and/or Verilog programming experience + Experience with validation or testing experience, especially in a silicon design team **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Texas, Austin **Additional Locations:** US, Oregon, Hillsboro **Business group:** The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits:** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: ********************************************************************************** Annual Salary Range for jobs which could be performed in the US: 139,710.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Intel's Discrete Graphics Engineering (DGE) organization develops cutting-edge discrete graphics products for gaming and AI. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role You will be responsible for designing and/or integrating IP for a discrete graphics SoC. You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation of discrete graphics SoC products, including: + Creating a design to produce key assets that help improve product KPIs for discrete graphics products + Working with SoC Architecture and platform architecture teams to establish silicon requirements + Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule + Creating micro architectural specification document for the design. + Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs. + Driving vendor's methodology to meet world class silicon design standards + Architecting area and power efficient low latency designs with scalabilities and flexibilities + Power and Area efficient RTL logic design and DV support + Running tools to ensure lint-free and CDC/RDC clean design, VCLP + Synthesis and timing constraints + Having achieved multiple tape-outs reaching production with first pass silicon + Ability to drive and improve digital design methodology to achieve high quality first silicon Hands on experience with FPGA emulation, silicon bring-up, characterization and debug + Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule + Strong verbal and written communication skills Good understanding of verilog and system verilog, synthesizable RTL + Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis + Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post silicon power correlation + Background in computer architecture + Bus fabric, including, but not limited to APB/AHB/AXI + Power management with multiple power domains, UPF, Power state tables. + Knowledge of lint tools, CDC and RDC tools, timing constraints, fishtail. + Knowledge of connectivity tools. + Understanding of key SoC design elements, arbiters, async FIFOs, DMAs, basic Controllers. + Comprehension of asynchronous clock crossing means and methodologies + Proven track record of bringing logic designs into high volume production + Ability to work well in a team and be productive under ambitious schedules + Should be self-motivated and well organized **Qualifications:** + BS+5 Years of relevant industry experience **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, California, Santa Clara **Additional Locations:** US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro **Business group:** The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. **Benefits:** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: ********************************************************************************** Annual Salary Range for jobs which could be performed in the US: 214,730.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.