Mechanical Engineer jobs at Intel - 723 jobs

About Intel Foundry Services Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. Position Overview The Aerospace, Defense & Government (ADG) Memory Design Application Engineer provides specialized technical support to Intel Foundry Services customers on memory compiler generation and integration challenges. This critical role ensures successful customer tape-outs by resolving complex memory IP integration issues, driving quality improvements in memory collaterals, and delivering comprehensive technical guidance on memory design methodologies for advanced semiconductor applications. Key Responsibilities Memory IP Technical Support & Integration * Provide comprehensive technical support to Intel Foundry Services customers on memory compiler generation and integration issues * Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, Memory IP providers, and EDA vendors on foundational IP integration issue resolution * Drive resolution of customer issues related to memory IP collaterals, ensuring seamless integration and optimal performance Technical Content Development & Training * Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams * Drive quality improvements in design kits, Memory IP collaterals, and documentation to remove barriers to successful customer design tape-outs * Develop best practice guidelines for memory integration across advanced process technologies and customer applications Memory Design Methodology & Problem Solving * Lead debugging and problem-solving activities in collaborative team environments * Provide technical expertise on memory compiler design, generation, and optimization * Support customers through complex memory design challenges and advanced integration requirements * Drive methodology improvements to enhance memory design productivity and reliability Customer Engagement & Technical Excellence * Deliver customer-facing technical support with focus on memory design and integration solutions * Ensure maximum customer satisfaction through expert guidance on memory IP implementation * Support aerospace, defense, and government customers with specialized memory requirements and security considerations Core Competencies * Self-driven and results-oriented with capability to effectively manage multiple complex tasks * Effective communicator with strong interpersonal and leadership capabilities, fostering collaboration across cross-functional teams and providing constructive feedback Qualifications: The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates Minimum Qualifications * US Citizenship required * Ability to obtain a US Government Security Clearance * Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study * 3+ years of experience with Memory design or Memory Compiler development and implementation Preferred Qualifications: * Active US Government Security Clearance with a minimum of Secret level * Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study * Proficient in common memory types, including SRAM, Register Files (RF), and ROM, with a solid understanding of CMOS digital circuit design principles * Knowledgeable in both behavioral and physical modeling of memory architectures, supporting accurate simulation and verification * Hands-on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and anti FUSE and MBIST * Experience with IP development is a strong plus * Proficient in scripting languages like Perl/Tcl/Python, and power-aware RTL and UPF flow is a plus * Experience in ASIC or SoC development What We Offer * Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications * Direct customer engagement and technical leadership in advanced memory design * Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio * Competitive compensation * Professional development in memory design methodologies and foundry services * Direct impact on national security through advanced memory semiconductor solutions Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Manager, Mechanical Engineering page is loaded Manager, Mechanical EngineeringApply locations Santa Clara,CA time type Full time posted on Posted Yesterday job requisition id R2516057 Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world - like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries ofscience and engineering to make possiblethe next generations of technology, join us to Make Possible a Better Future. What We Offer Salary: $185,000.00 - $254,000.00 Location: Santa Clara,CA At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. We're committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits . You'll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers.We empower our team to push the boundaries of what is possible-while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. Key Responsibilities Manages a mechanical engineering group with specific responsibility for mechanical systems and equipment design function, staffing, technical mentoring as required within the engineering group, staff professional and personal development, team building, defining organizational roles, hiring and retention. Additional responsibilities include developing and sustaining supervisors/technical leaders for key areas of responsibility, and budget adherence. Also, technically lead and/or execute engineering projects/programs Ensures customer satisfaction via on time delivery of product releases and prompt resolution of extremely complex issues for entire range of products for division of significantly complex scope Ensures the integration of engineering resources with cross-functional teams to meet product goals for the units product line of significantly complex scope Interface with internal and external customers regarding extremely complex engineering issues to address customers High Value Problems (HVP) for a range of products for the division Provides management with updates pertaining to progress in specific programs and initiatives, and assures that information required in other functional areas is disseminated appropriately Define, develop, and sustain product strategy, objectives and roadmap Guides programs for the research and development of new technologies relating to mechanical engineering as appropriate, and ensures that newly created processes, designs, and/or methodologies are incorporated into Applied Materials products/services, and/or disseminated to other areas as needed Assures that a full range of technical reviews are held Functional Knowledge Demonstrates comprehensive understanding of concepts and principles within own job family and knowledge of other related job families Business Expertise Applies in-depth understanding of how own discipline integrates within the segment/function Leadership Manages multiple related teams, sets organizational priorities and allocates resources Problem Solving Identifies and resolves complex technical, operational and organizational problems Impact Impacts the business results of a team or area by supporting and funding of projects, products, services and/or technologies and developing policies and plans Guided by business unit, department or sub-functional business plans Interpersonal Skills Influences others internally and externally, including senior management Position requires understanding of Applied Materials global Standards of Business Conduct and compliance with these standards at all times. This includes demonstrating the highest level of ethical conduct reflecting Applied Materials' core values. Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes The salary offered to a selected candidate will be based on multiple factors including location, hire grade, job-related knowledge, skills, experience, and with consideration of internal equity of our current team members. In addition to a comprehensive benefits package, candidates may be eligible for other forms of compensation such as participation in a bonus and a stock award program, as applicable. For all sales roles, the posted salary range is the Target Total Cash (TTC) range for the role, which is the sum of base salary and target bonus amount at 100% goal achievement. Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law. In addition, Applied endeavors to make our careers site accessible to all users. If you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_****************, or by calling our HR Direct Help Line at ************, option 1, and following the prompts to speak to an HR Advisor. This contact is for accommodation requests only and cannot be used to inquire about the status of applications. #J-18808-Ljbffr

Physical Design Engineer - New College Grad 2026 page is loaded## Physical Design Engineer - New College Grad 2026locations: US, CA, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR2009983We are now looking for a Physical Design Engineer!NVIDIA has continuously pioneered and reinvented itself over two decades through various avenues of computing: Graphics, High Performance Computing, Artificial Intelligence, Research, and more. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can solve, and that matter to the world. This is our life's work, to amplify human creativity, intelligence, and technology. Today, visual computing is becoming increasingly central to how people interact with technology, and there has never been a more exciting time to join our team. We are looking for a Physical Design Engineer who will be responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets, and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets.**What you will be doing:*** As a member of the team, you will participate in the efforts in establishing CAD and physical design methodologies (flow and tools development) as well as implementation.* Your day to day will include developing chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects.* This position requires you to work with EDA vendor (Synopsys, Cadence, Mentor, etc.) tool suites such as: ICC2,PrimeTime, dc\_shell, Innovus, SeaHawk.* You will interact with a diverse team engineers.**What we need to see:*** Completing an BSEE, MSEE or PhD (or equivalent experience).* Deep understanding of VLSI and Physical Design related basics & concepts.* Possess a deep understanding of static timing analysis, clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis.* Experience in scripting and programming using several of the following languages/tools: Perl, C, C++, TCL, Scheme, Skill, or Make.* Previous internship or project experience in physical design implementation With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a passion for technology, we want to hear from you!Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 96,000 USD - 161,000 USD for Level 1, and 108,000 USD - 184,000 USD for Level 2.You will also be eligible for equity and .Applications for this job will be accepted at least until December 19, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking a Physical IC Design Engineer to drive next-generation AI and ML ecosystems through PCIe Switch Products. This role requires a strong background in Physical Design, including execution of design, verification, and timing closure. The ideal candidate must have a Bachelor's degree in Electrical or Electronics Engineering and at least 8 years of experience. The position offers a competitive salary range of $120,000 to $192,000, along with comprehensive benefits. #J-18808-Ljbffr

A leading technology company in San Jose is looking for a Physical IC Design Engineer to drive next-gen AI and ML ecosystems. The role requires 8+ years of experience and a Bachelor's degree in Electrical or Electronics Engineering. Responsibilities include execution of Physical Design, Synthesis, and collaborating with IC Design engineers. This position has a salary range of $120,000 - $192,000 and offers a comprehensive benefits package including health plans, 401(K) matching, and paid leave. #J-18808-Ljbffr

Meet the Team The Splunk Observability Application Platform Team is a dynamic group of engineers responsible for the core platform powering Splunk Observability Cloud. Our platform is the foundation for advanced observability capabilities that enable our customers to thrive. We operate in small, high-performing teams, driving significant impact and working with microservices at scale. Our mission is to optimize platform systems for reliability, transparency, efficiency, and cost-effectiveness, so engineering teams across Splunk Observability can focus on innovation and deliver unique value to customers. As we enter the agentic AI era, we face exciting opportunities and challenges to expand our platform for both agents and human users. Join us as we shape the next chapter of our platform, increase our scale, and delight our customers. You'll work with distributed systems, leverage open source where it fits, and build high-performance custom solutions when needed. Your Impact Lead the design and implementation of shared libraries, components, and microservices to build a modern, highly reliable, secure, and scalable application platform. Influence and contribute to critical decisions on technical architecture and platform design. Collaborate across multiple teams within Cisco to drive platform innovation and ensure seamless integration. Mentor and develop engineering talent, fostering a culture of growth and collaboration. Minimum Qualifications At least 6 months of hands‑on experience effectively leveraging AI coding assistance, with a strong “AI‑first” mindset. 3+ years of proven experience delivering large‑scale, distributed SaaS solutions. Bachelor's degree in Computer Science, Engineering, or a related field with 8+ years of software engineering experience, or a Master's degree with 6+ years of experience. Deep understanding of microservices and distributed application architecture, including when to simplify and seek alternatives. Exceptional problem‑solving and communication skills, with the ability to explain complex technical concepts to both technical and non‑technical stakeholders. Proficiency in Java and the ability to quickly learn new programming languages. Preferred Qualifications Experience and knowledge in the observability and monitoring domain. Strong troubleshooting and performance profiling capabilities. A devops automation mindset with a passion for engineering efficiency and process optimization. Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job‑related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non‑exempt employees 1 paid day off for employee's birthday, paid year‑end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non‑exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non‑sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance‑based incentive pay on top of their base salary, which is split between quota and non‑quota components, subject to the applicable Cisco plan. For quota‑based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non‑quota‑based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $183,800.00 - $303,100.00 Non‑Metro New York state & Washington state: $163,600.00 - $269,800.00 For quota‑based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non‑exempt, will participate in a unique time off program to meet local requirements. Cisco is an affirmative action and equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. Cisco will consider for employment, on a case‑by‑case basis, qualified applicants with arrest and conviction records. #J-18808-Ljbffr

A leading technology firm in San Jose is seeking a Physical Design Engineer to focus on the implementation and optimization of IC layouts for advanced technologies. The ideal candidate has extensive experience in physical layout, strong scripting skills in TCL and Python, and a solid background in electrical engineering. This role offers a competitive salary, bonus potential, and comprehensive benefits. #J-18808-Ljbffr

A global technology company is looking for a seasoned software engineer to enhance AI capabilities within their observability platform. Candidates should have a strong background in AI/ML systems, cloud computing, and robust technical leadership. This role is pivotal in driving innovation in data analysis and delivering scalable solutions. The ideal candidate will thrive in an agile environment and provide mentorship to junior engineers. Enjoy competitive salaries and benefits while contributing to impactful technology solutions. #J-18808-Ljbffr

A leading semiconductor company in Santa Clara is looking for an FPGA Hardware Validation Engineer to create and implement validation platforms while collaborating with design and firmware teams. Candidates should have extensive experience in FPGA prototyping and strong problem-solving skills, along with a BS in Electrical or Computer Engineering. The role involves complex architecture designs and debugging hardware/firmware issues. Join a culture of innovation driven by collaboration and inclusivity. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. The Role This role is an exciting opportunity in SBIO team to create FPGA hardware validation platforms and debugging complex issues involving both hardware and software. Collaborate with design and firmware teams to define validation plans and execute on FPGA prototyping platforms. This role requires a proven track record of successfully bringing complex FPGA designs from concept through production quality, with strong debugging and problem-solving capabilities. The Person Strong analytical and problem solving skills with a pronounced attention to detail Strong communication, mentoring and leadership skills Self-driven, Methodical and attention to detail in troubleshooting and problem-solving Can work well with cross functional teams Excellent verbal and written communication skills Responsibility Design, develop, and implement complex FPGA architectures using Xilinx devices (UltraScale, UltraScale+, Versal, etc.) Create RTL designs using Verilog/SystemVerilog for high-performance applications Perform FPGA prototype design, implementation, and bring‑up activities Create comprehensive design documentation, specifications, and technical reports Perform timing analysis, closure, and optimization using Vivado tools Conduct board-level bring‑up and system integration testing Debug complex hardware/firmware issues using logic analyzers, oscilloscopes, and other test equipment Validate FPGA designs against specifications and performance requirements Independently troubleshoot and resolve challenging technical issues Work closely with hardware, software, and systems engineering teams Participate in design reviews and technical discussions Communicate project status, risks, and technical challenges to stakeholders Preferred Skill Set & Experience Extensive experience in field of FPGA hardware prototyping Have worked with prototyping platforms such as Xilinx reference boards, Synopsys HAPS platforms etc Experience with Xilinx Versal ACAP or UltraScale+ devices Knowledge of FPGA synthesis tools and methodologies Familiarity with Python/TCL scripting for design automation Knowledge of FPGA-based system architecture and hardware/software co‑design Familiarity with board design and hardware debugging tools (logic analyzers, oscilloscopes, protocol analyzers) Fluent in System Verilog and a familiarity with simulation and debug Familiarity with industry standard high-speed protocols such as USB and PCIE is a plus EDUCATION BS (or higher) degree in Electrical or Computer Engineering desired LOCATION Santa Clara, CA This role is not eligible for visa sponsorship. #LI‑SC3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE We are seeking a Senior Member of Technical Staff (SMTS) SoC Architect to join our SoC Architecture team. In this role, you will define and drive architecture for critical SoC functions across roadmap and custom devices. You will focus on chip pervasive components, while ensuring seamless integration with processor subsystems, interconnect, AI accelerators, and memory systems. THE PERSON You are passionate about complex SoC architecture and thrive in cross-functional environments. You have deep technical expertise, strong analytical skills, and the ability to balance performance, power, and area trade-offs. You communicate effectively across teams and are comfortable influencing architecture decisions for next-generation silicon. KEY RESPONSIBILITIES Define and develop SoC architecture for CPF components, including Analog IPs, clocking/reset, and silicon monitors. Collaborate with processor, interconnect, AI, and memory subsystem architects to ensure cohesive system-level design. Specify architecture requirements, conduct early-stage analysis, and create detailed specifications. Drive PPA optimization and ensure scalability across roadmap and custom devices. Partner with design, verification, and physical implementation teams to ensure functional correctness and timing closure. Analyze trade-offs for performance, power, reliability, and manufacturability. Influence strategies for security, safety, and reliability across CPF domains. Strong communication and leadership skills to influence cross-functional teams. PREFERRED EXPERIENCE Strong background in SoC architecture, including processor subsystems, interconnect, memory systems, and AI accelerators. Expertise in Analog IPs (IOs, PLLs, eFuses, monitors), clocking/reset architecture, and silicon lifecycle management. Familiarity with SoC on-chip protocols (e.g., AXI) and system-level QoS. Experience with low-power design techniques, boot/reset flows, and power management. Knowledge of design methodologies, advanced process technologies, and associated challenges. Proficiency in modeling and automation using Python, SystemC, or similar languages. ACADEMIC & EXPERIENCE REQUIREMENTS BS or MS or PhD in Electrical/Computer Engineering or related field. Proven track record in delivering architecture for high-performance, low-power SoCs. LOCATION: San Jose, California Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading technology firm in Santa Clara is seeking a Robotics Deep Learning Expert to push the boundaries of robotics. You will work on imbuing humanoid robots with advanced capabilities, requiring strong skills in algorithm development and deep learning frameworks. The salary range is competitive, reflecting your experience and position level, and additional benefits and equity are offered. Join a team that thrives on creativity and challenge. #J-18808-Ljbffr

A leading technology company is seeking a Senior Generative AI Software Engineer to drive the evolution of cutting-edge AI models and infrastructure. You will refactor research code, build model-serving endpoints, and ensure code quality across teams. Candidates should be proficient in Python and PyTorch with over 10 years of experience. This position offers competitive salary ranges between $224,000 and $425,500 depending on level and experience. #J-18808-Ljbffr

A leading technology company in San Jose is looking for a recent graduate or PhD candidate for an AI/ML development role. The position requires backend development skills in Go or Python and understanding of LLM infrastructure. Candidates should be ready to collaborate with cross-functional teams, optimizing models for real-world deployment. This role offers competitive salary ranges based on location, benefiting from Cisco's extensive employee perks and growth opportunities. #J-18808-Ljbffr

A leading technology company in San Jose is seeking a skilled engineer to develop applications based on generative AI models such as GPT-4. This role involves collaborating with cross-functional teams to optimize performance and ensure reliability, as well as engaging in cutting-edge AI developments. The ideal candidate will have a Bachelor's or Master's degree in a relevant field and deep knowledge of machine learning methodologies. Competitive compensation, benefits, and opportunities for growth will be offered. #J-18808-Ljbffr

A leading technology company in San Francisco is seeking a professional to develop AI/ML solutions. You will work closely with various teams to implement and optimize applications based on large language models. The ideal candidate has a Bachelor's or Master's degree in a relevant field and a strong understanding of machine learning algorithms. Join us to contribute to innovative projects and collaborate in a dynamic environment. #J-18808-Ljbffr

A leading technology firm in San Francisco is looking for an innovative engineer to develop generative AI applications. This role requires a PhD in a relevant field and backend development experience, preferably in Go or Python. You will work with cutting-edge technologies and collaborate with world-class teams to create and implement AI solutions. Cisco offers a competitive salary and a collaborative work environment that fosters growth and innovation. #J-18808-Ljbffr

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 6 - 15 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem‑solving skills are top‑notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You'll Be Doing: Designing, developing, and troubleshooting core algorithms for compiler. Collaborating with local and global teams to enhance runtime performance for verilog compiler. Engaging in pure technical roles focused on software development and architecture. Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation. Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting‑edge solutions. The Impact You Will Have: Driving technological innovation in chip design and verification. Enhancing the performance and quality of simulation tools used globally. Solving complex compiler optimizations problems to improve simulation performance. Collaborating with cross‑functional teams to achieve project milestones. Pioneering new software architectures that set industry standards. What You'll Need: Strong hands‑on experience in C/C++ based software development. Deep understanding of design patterns, data structures, algorithms, and programming concepts. Knowledge of ASIC design flow and EDA tools and methodologies. Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: Highly enthusiastic and energetic team player with excellent communication skills. Strong desire to learn and explore new technologies. Effective problem‑solver with a keen analytical mind. Experienced in working on Unix/Linux platforms. Adept at using developer tools such as gdb and Valgrind. The Team You'll Be A Part Of: You will be part of the performance team in Digital Simulation. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #J-18808-Ljbffr

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 6 - 15 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem‑solving skills are top‑notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You'll Be Doing: Designing, developing, and troubleshooting core algorithms for compiler. Collaborating with local and global teams to enhance runtime performance for verilog compiler. Engaging in pure technical roles focused on software development and architecture. Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation. Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting‑edge solutions. The Impact You Will Have: Driving technological innovation in chip design and verification. Enhancing the performance and quality of simulation tools used globally. Solving complex compiler optimizations problems to improve simulation performance. Collaborating with cross‑functional teams to achieve project milestones. Pioneering new software architectures that set industry standards. What You'll Need: Strong hands‑on experience in C/C++ based software development. Deep understanding of design patterns, data structures, algorithms, and programming concepts. Knowledge of ASIC design flow and EDA tools and methodologies. Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: Highly enthusiastic and energetic team player with excellent communication skills. Strong desire to learn and explore new technologies. Effective problem‑solver with a keen analytical mind. Experienced in working on Unix/Linux platforms. Adept at using developer tools such as gdb and Valgrind. The Team You'll Be A Part Of: You will be part of the performance team in Digital Simulation. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #J-18808-Ljbffr