Research Engineer jobs at Intel

At Intel, the Foundry Technology Development (TD) unit is the driving force behind Moore's Law, enabling us to create groundbreaking technology that enriches lives globally. With over 15,000 dedicated employees, Foundry TD spearheads innovative research, develops next-generation processes and packaging technologies, and manages high-volume manufacturing in state-of-the-art facilities. Within Intel Foundry TD, our Logic Technology Development (LTD) organization is at the forefront of creating and refining each process technology node, paving the way for tomorrow's computing solutions. The LTD organization is seeking a Yield Development Engineer who is passionate, innovative, and results-oriented with experience in semiconductor manufacturing equipment and systems. The individual will be expected to develop, implement, optimize, maintain, and document procedures for design database analysis supporting metrology equipment used for development and manufacturing for foundry customers. The engineer will work closely with equipment development, operations, automation, and computational and modeling technology collaborators to provide quality end-to-end foundry solutions. The candidate should be excited to work in a fast-paced environment where flexibility and adaptability is key to their success. Ability to learn rapidly in a complex and rapidly changing environment and to communicate effectively with co-workers and across teams is a must. About the Role: As a Yield Development Engineer with factory equipment focus, you will play a pivotal role in advancing our technology and foundry capabilities. Your responsibilities will include, but are not limited to: * Develops tools, multivariate algorithms, and methodologies to perform high volume data analysis to identify root cause yield limiters and identify key process changes to advance yield improvement. * Develops measurement recipes to provide quick and accurate feedback on product integrity, helping resolve issues with yield or product quality impact. * Develops and hardens equipment capable of meeting operational and capability needs for leading edge logic node including close work with equipment vendors and internal collaborators. * Develops methods, processes, and systems to consolidate and analyze diverse big data sources, establishing optimal methodologies for defect mode understanding and yield modeling, leading to accurate yield Pareto construction and process roadmap definition. * Organizes, interprets, and structures insights from fab process, defect, and electrical data and detects data anomalies and drives process changes for yield enhancement. * Extracts insights from structured and unstructured data by quickly synthesizing large volumes of data, and applying statistics, machine learning and coding techniques. * Develops systems to transform complex experimental and manufacturing data into yield improvement actions using knowledge of product design and test features. * Ensures manufacturability over process and product design through thorough analysis of process and spec corners and works with design to resolve yield issues before manufacturing ramp. * Executes new product introductions, enables design technology co-optimization, and participates in design of experiments in factory task forces. * Develop computational tools and AI/ML applications that improve patterning solutions, decrease process debug time, improve design efficiency, and bridge the gap between design and manufacturing. * Work will span solution exploration, technical design, implementation, deployment in a production environment, and maintenance of the deployed solutions. * Create innovative solutions to problems, collaborate with internal teams to ensure data integrity, implement custom algorithms to perform feature engineering, develop efficient software solutions that meet computing constraints, and ensure code quality to enable deployment in a production environment. * Technically document and train collaborators on methods and best practices developed. * Debug equipment, software, and procedural anomalies in the production environment which occasionally may require off hour urgent support. Join us and transform technology to create a better future. At Intel, we foster a collaborative, supportive, and dynamic environment where the brightest minds come together to achieve exceptional results. We offer: * Competitive salaries and financial benefits, including bonuses, life and disability insurance, and opportunities to purchase Intel stock at a discounted rate. * Comprehensive benefits that promote a healthy, enjoyable life, including excellent medical plans, wellness programs, time off, recreational activities, and discounts on various products and services. * A commitment to creating a more connected and intelligent future, with opportunities to make a global impact. Change tomorrow. Start today. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous jobs and internships. Minimum Qualifications: * US Citizenship required. * Ability to obtain and maintain an Active US Government Security Clearance. * Candidate must possess one of the following: * Bachelor's degree in an Engineering and/or Science discipline such as Electrical Engineering, Applied Physics, Physics, Chemistry, Materials Science, Chemical Engineering AND 4+ years of experience with semiconductor processing, semiconductor devices and circuits device physics or Nanotechnology OR Master's degree in an Engineering and/or Science discipline such as Electrical Engineering, Applied Physics, Physics, Chemistry, Materials Science, Chemical Engineering AND 2+ years of experience with semiconductor processing, semiconductor devices and circuits device physics or Nanotechnology OR PhD degree in an Engineering and/or Science discipline such as Electrical Engineering, Applied Physics, Physics, Chemistry, Materials Science, Chemical Engineering. * 4+ years of professional and/or educational experience in relevant areas of FIB/SEM and TEM based materials characterization and failure analysis. Preferred Qualifications: * Active US Government Security Clearance. * 10+ years of advanced expertise and experience in focused ion-beam (FIB), scanning electron microscopy (SEM) and transmission electron microscopy (TEM) techniques for materials analysis with 5+ years of experience in a professional setup. * 5+ years of extensive hands-on experience of FIB-SEM and TEM based characterization of semiconductor materials. * Detailed knowledge of the tool-specific automation software and tool maintenance/capabilities. * Demonstrated experience of Statistical Process Control (SPC) for process development and tight control of tool performance. * Demonstrated experience and ability to work with external and internal partners. * Experience with technical documentation, training and project management. Job location and requirements: * Hillsboro, OR, USA * On-site is required. Remote or Hybrid work mode is not supported. We are looking for passionate individuals who are ready to make a difference. If you are driven by innovation and eager to contribute to a team that is shaping the future, we want to hear from you. Join us at Intel and be part of something extraordinary. Benefits at Intel Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: ********************************************************************************** Annual Salary Range for jobs which could be performed in the US: 110,880.00 USD - 216,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Meta is seeking a Research Engineer to join our Large Language Model (LLM) Research team. We conduct focused research and engineering to build state-of-the-art LLMs, which we often open-source, like our team's recent Llama 2. We are looking for strong engineers who have a background in generative AI and NLP, with experience in areas like language model evaluation; data processing for pre-training and fine-tuning; responsible LLMs; LLM alignment; reinforcement learning for language model tuning; efficient training and inference; and/or multilingual and multimodal modeling. **Required Skills:** Research Engineer, Language - Generative AI Responsibilities: 1. Design methods, tools, and infrastructure to push forward the state of the art in large language models 2. Define research goals informed by practical engineering concerns 3. Contribute to experiments, including designing experimental details, writing reusable code, running evaluations, and organizing results 4. Adapt standard machine learning methods to best exploit modern parallel environments (e.g. distributed clusters, multicore SMP, and GPU) 5. Work with a large and globally distributed team 6. Contribute to publications and open-sourcing efforts **Minimum Qualifications:** Minimum Qualifications: 7. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8. Research experience in machine learning, deep learning, and/or natural language processing 9. Experience with developing machine learning models at scale from inception to business impact 10. Programming experience in Python and hands-on experience with frameworks such as PyTorch 11. Exposure to architectural patterns of large scale software applications **Preferred Qualifications:** Preferred Qualifications: 12. A PhD in AI, computer science, data science, or related technical fields. 13. Master's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 14. First author publications at peer-reviewed AI conferences (e.g., NeurIPS, CVPR, ICML, ICLR, ICCV, and ACL). 15. Direct experience in generative AI and LLM research. **Public Compensation:** $85.10/hour to $251,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

Research Internships at Microsoft provide a dynamic environment for research careers with a network of world-class research labs led by globally-recognized scientists and engineers, who pursue innovation in a range of scientific and technical disciplines to help solve complex challenges in diverse fields, including computing, healthcare, economics, and the environment. This Research Internship is an opportunity to work alongside world-class engineers to optimize the performance of Azure Central Processing Units (CPUs) for workloads representing actual usages. The project involves profiling applications at scale and developing new, innovative solutions for applying machine learning/artificial intelligence (ML/AI) to optimization methods such as PGO, LTO, BOLT, FDO etc. Candidates will gain hands-on experience in applying ML/AI for low-level software optimization, systems performance engineering and practical exposure to hyperscale architecture and workloads. Responsibilities Research Interns put inquiry and theory into practice. Alongside fellow doctoral candidates and some of the world's best researchers, Research Interns learn, collaborate, and network for life. Research Interns not only advance their own careers, but they also contribute to exciting research and development strides. During the 12-week internship, Research Interns are paired with mentors and expected to collaborate with other Research Interns and researchers, present findings, and contribute to the vibrant life of the community. Research internships are available in all areas of research, and are offered year-round, though they typically begin in the summer. * Qualifications Required Qualifications * Currently enrolled in a master's or PhD program in Computer Science, Computer Engineering or a related STEM field. * At least 1 year of experience with data analysis. Other Requirements * Research Interns are expected to be physically located in their manager's Microsoft worksite location for the duration of their internship. * In addition to the qualifications below, you'll need to submit a minimum of two reference letters for this position as well as a cover letter and any relevant work or research samples. After you submit your application, a request for letters may be sent to your list of references on your behalf. Note that reference letters cannot be requested until after you have submitted your application, and furthermore, that they might not be automatically requested for all candidates. You may wish to alert your letter writers in advance, so they will be ready to submit your letter. Preferred Qualifications * Familiarity with computer architecture and system performance measurement and modeling. * Experience with compilers, Linux, ARM ISA. * Demonstrated ability to develop original research agendas. * Ability to think unconventionally and derive creative, innovative solutions. * Proficient communication skills, both written and verbal. * Proven interpersonal skills with the ability to work effectively across groups and cultures. Applied Sciences IC2 - The base pay range for this internship is USD $5,610 - $11,010 per month. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $7,270 - $12,030 per month. Applied Sciences IC3 - The base pay range for this internship is USD $6,710 - $13,270 per month. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: ************************************************* Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work. This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Silicon, Manufacturing and Packaging Engineering (SMPE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Debug Engineer to join the team. Responsibilities * This is a senior technologist role that will guide Microsoft's strategy and execution on silicon debug, FA/FI and debug tool readiness * The candidate should have experience building end to end debug solutions: HW, SW, design collateral procurement, readiness for physical/electrical debug tools and physical FA readiness * The position requires someone with experience in semiconductor debug, fault isolation, failure analysis and product engineering yield debug * The candidate will be responsible for developing new silicon debug methodologies for all test content types in our MFG flow * The candidate will also be responsible for root-cause of key product issues, circuit marginalities, special circuit failures and translate them into corrective actions in the design, our design methodologies and/or the MFG test flow * Successful candidates have deep understanding and experience debugging product issues on ATE and using analytical equipment to isolate failures * Deep understanding of best-in class silicon debug tools and methodologies is a must * Successful candidates should have strong project leadership skills to manage external vendors, drive cross functional teams and drive sub-project as part of larger development programs Qualifications Required Qualifications: * Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience * OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience * OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience * OR equivalent experience. * 5+ years of experience in product and test engineering, specialize in silicon debug or FA/FI * 5+ years of experience building debug methodology solutions for complex state-of-the-art SoC in advance process nodes Other Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: * Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter Preferred Qualifications: * Experience with System-level debug and correlation to ATE * Strong presentation and communication skills. * Experience in * Leading cross functional teams and understands program/project management. * Managing supply chain, vendors / partners, and Integrated Circuit production. * Experience in system/customer requirements gathering and interfacing. * Strong probability and statistics background including DOE's. * Knowledgeable in DFT and DFM techniques. * Good understanding of bring-up/debug, characterization/manufacturing test (on ATEs). * Ability to drive development and bring up test content on mixed signal IP's is a plus. * Device physics background. #SCHIE #CSME Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: **************************************************** This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Hardware, Infrastructure Management, and Fundamentals Engineering (HIFE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Engineer to join the team. #azurehwjobs #SCHIE #HIFE Responsibilities * Lead development and implementation of end to end debug solutions for @scale datacenter systems. * Lead collaboration projects with hardware, firmware and software teams that drive root cause analysis. * Accountable for successful execution of targeted defect reduction projects. * Provide technical recommendations on at scale test content deployment technologies. * Lead resolution of complex problems based on technical and business understanding. * Develop world class at scale debug methodologies, test strategies and test routines in data center solutions. * Solve problems relating to mission critical services and build automation to drive debug efficiency. * Effectively communicate with partners and stakeholders for planning and progress on initiatives using data. * Embody our culture and values. Qualifications Required Qualifications: * Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, * OR related field AND 7+ years technical engineering experience * OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, * OR related field AND 8+ years technical engineering experience * OR equivalent experience. * 5+ years of experience of technical leadership as a platform or software architect or validation architect or a lead debug engineer or equivalent industry experience leadership position. * Deep understanding of modern server or datacenter architectures or System on Chip features like virtualization technologies or major architectural blocks like Memory Controllers or Central Processing Units or Storage or Networking solutions for Cloud or Datacenter infrastructures * Experience leading technical deep dives into datacenter software solutions used in at scale environments or datacenter infrastructure and data systems, cloud native operating systems, or virtualization technologies. Other Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: * Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. Preferred Qualifications: * Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, * OR related field AND 7+ years technical engineering experience * OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, * OR related field AND 8+ years technical engineering experience * OR equivalent experience. * Platform or system level debug and validation experience * Data analytical skills- Knowing how to use large scale data and analytical tools. * Great communication skills using various forms of media. * Able to plan work, and work to a plan adapting as necessary in a rapidly evolving Environment. * Individual effectiveness skills such as discipline, time management, decision making, planning, and organizing work, summarizing results through technical reports * Self-driven, self-motivated individual who can work independently as well as collaboratively in a team environment and across the team of engineers. Hardware Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: **************************************************** This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Principal Engineer to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Hardware, Infrastructure Management, and Fundamentals Engineering (HIFE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the cloud infrastructure. We are looking for a Principal Engineer to join the team. Responsibilities * Lead development and implementation of end to end debug solutions for at scale datacenter systems. * Lead collaboration projects with hardware, firmware and software teams that drive root cause analysis. * Accountable for successful execution of targeted defect reduction projects. * Provide technical recommendations on at scale test content deployment technologies. * Lead resolution of complex problems based on technical and business understanding. * Develop world class at scale debug methodologies, test strategies and test routines in data center solutions. * Solve problems relating to mission critical services and build automation to drive debug efficiency. * Effectively communicate with partners and stakeholders for planning and progress on initiatives using data. Qualifications Required * Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 7+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years technical engineering experience OR equivalent experience. Preferred * Platform or system level debug and validation experience. * Knowledgable on utilizing large scale data and analytical tools. * Ablility to plan work, and work to a plan adapting as necessary in a rapidly evolving environment. Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Hardware Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: **************************************************** This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Sr Principal Data Architect is responsible for defining the data and information architecture vision, strategy, and roadmap across DISE and Corporate Functions (Legal, HR, Finance, Compliance, Security, middleware/hosting). This leader will drive enterprise data lake strategy, govern data across multiple domains, and enable secure, trusted analytics. The role partners with platform owners, cybersecurity, enterprise architecture, and product teams; it does not directly own infrastructure platforms. The role accelerates digital utilization by standardizing data models, establishing reusable patterns, ensuring high data quality, and enabling self-service analytics. Success improves Safety, Quality, Delivery, and Cost through better decisions, automation, and compliance-grade data. **Job Description** **Key Responsibilities** **Strategy and Architecture** + Define and maintain the enterprise data and information architecture across Corporate Functions, spanning relational, non-relational, streaming, and file-based stores. + Lead data lake strategy (including zone design and reusable data product patterns) with clear decision guardrails for cost, performance, and security. + Establish reference architectures for data ingestion, transformation, serving, and interoperability across HR, Legal, Finance, Compliance, and Security. + Set and govern standards for canonical/conformed data models, semantic layers, and reusable transformation patterns. **Data Management and Governance** + Implement data governance with domain-aligned stewardship, cataloging, lineage, and metadata management. + Drive data quality strategy: profiling, rules, monitoring, remediation playbooks, and service-level objectives. + Define and enforce data security, privacy, and retention controls in partnership with Cybersecurity, Legal, and Compliance (e.g., role- and attribute-based access). + Guide master and reference data strategies and processes, including patterns for MDM and reference data management. **Delivery and Enablement** + Partner with engineering, architecture, analytics, and product teams to design and deliver end-to-end data products and use cases. + Standardize orchestration and CI/CD practices for data pipelines to ensure reliability, observability, and cost transparency. + Provide architectural oversight from design through stabilization, including technical reviews and readiness gates. + Maintain technical data dictionaries and align with business glossaries and shared semantics. **Risk, Compliance, and Lifecycle** + Ensure adherence to regulatory, contractual, and export control requirements across sensitive corporate data domains. + Define data lifecycle management (tiering, archiving, purging) balancing compliance, performance, and cost. + Lead incident response for data issues; drive root cause analysis and implementation of preventive controls. **Leadership and Stakeholder Management** + Influence senior stakeholders (including executives and c-suite leaders) on strategic data and technology investments and their implementation considerations. + Represent the company externally by participating in relevant industry forums and leading discussions on data and software architecture. + Introduce company-wide patterns and tools that improve collaboration, productivity, and community-building across data and engineering teams. + Partner with executives and senior business leaders to guide technology decisions on data and software products. + Coach and mentor team members on technical skills and leadership behaviors; foster a culture of reuse, standard work, and continuous improvement. + Communicate architecture decisions, tradeoffs, and ROI clearly to executive and non-technical audiences. **Required Qualifications / Experience** + Bachelor's degree from accredited university or college with minimum of 10 years of professional experience OR associate's degree with minimum of 13 years of professional experience OR High School Diploma with minimum of 15 years of professional experience + Minimum 8 years of professional experience incomputer science, Information Systems, Engineering, Mathematics, or related field + 7 years designing and operating data lakes and data pipelines across multiple domains + Legal authorization to work in the U.S.; sponsorship not available + **Note** : Military experience is equivalent to professional experience **Eligibility Requirement:** + Legal authorization to work in the U.S. is required. We will not sponsor individuals for employment visas, now or in the future, for this job. The base pay range for this position is $176,000- $293,300. The specific pay offered may be influenced by a variety of factors, including the candidate's experience, education, and skill set. This position is also eligible for an annual discretionary bonus based on a percentage of your base salary/ commission based on the plan. This posting is expected to close on December 31, 2025. Healthcare benefits include medical, dental, vision, and prescription drug coverage; access to a Health Coach, a 24/7 nurse-based resource; and access to the Employee Assistance Program, providing 24/7 confidential assessment, counseling and referral services. Retirement benefits include the GE Retirement Savings Plan, a tax-advantaged 401(k) savings opportunity with company matching contributions and company retirement contributions, as well as access to Fidelity resources and planning consultants. Other benefits include tuition assistance, adoption assistance, paid parental leave, disability insurance, life insurance, and paid time-off for vacation or illness. General Electric Company, Ropcor, Inc., their successors, and in some cases their affiliates, each sponsor certain employee benefit plans or programs ( _i.e_ ., is a "Sponsor"). Each Sponsor reserves the right to terminate, amend, suspend, replace, or modify its benefit plans and programs at any time and for any reason, in its sole discretion. No individual has a vested right to any benefit under a Sponsor's welfare benefit plan or program. This document does not create a contract of employment with any individual. **Qualifications:** + Experience in aerospace/defense, highly regulated industries, or mission-critical corporate functions (Legal, HR, Finance, Compliance, Security) + Proven expertise building and scaling data lake platforms and patterns on major clouds (AWS, Azure, or GCP) + Hands-on depth with MPP and distributed data processing + Strong data modeling across OLTP and OLAP; dimensional, data vault, and canonical modeling approaches + Mastery of ELT/ETL tooling and orchestration (e.g., dbt, Informatica, Talend, Airflow, Azure Data Factory, Glue) + Strong SQL and at least one programming language (Python/Scala/Java); experience with APIs, event-driven patterns, and files (JSON, Avro, Parquet) + Data governance tooling and practices (Collibra, Alation), metadata/lineage (OpenLineage, built-in catalogs), and data quality frameworks + Security and privacy by design: encryption, tokenization, masking, key management, IAM/RBAC/ABAC; exposure to SOC2, SOX, GDPR, CCPA, ITAR/EAR considerations + Experience defining data product standards, semantic layers (e.g., semantic modeling in BI/ML stacks), and self-service analytics enablement + Familiarity with MDM patterns and tools; reference data management at enterprise scale + Executive communication, influencing, and stakeholder management skills in a matrixed environment **Key Competencies:** + Enterprise Data Architecture + Data Lake Strategy + Data Modeling (canonical, dimensional, vault) + Data Governance, Quality, and Metadata + Security, Privacy, and Compliance + Pipeline Engineering, Observability, and Reliability + Financial acumen for cloud/data cost optimization + Product thinking and value delivery + Leadership, coaching, and cross-functional influence _This role requires access to U.S. export-controlled information. Therefore, employment will be contingent upon the ability to prove that you meet the status of a U.S. Person as one of the following: U.S. lawful permanent resident, U.S. Citizen, have been granted asylee or refugee status (i.e., a protected individual under the Immigration and Naturalization Act, 8 U.S.C. 1324b(a)(3))._ **Additional Information** GE Aerospace offers a great work environment, professional development, challenging careers, and competitive compensation. GE Aerospace is an Equal Opportunity Employer (****************************************************************************************** . Employment decisions are made without regard to race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, protected veteran status or other characteristics protected by law. GE Aerospace will only employ those who are legally authorized to work in the United States for this opening. Any offer of employment is conditioned upon the successful completion of a drug screen (as applicable). **Relocation Assistance Provided:** No \#LI-Remote - This is a remote position GE Aerospace is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, protected veteran status or other characteristics protected by law.

Meta is seeking a data center Critical Facility Engineer to join our Data Center Facility Operations team. Our data centers serve as the foundation upon which our software operates to meet the demands of our customers. The Critical Facility Engineer will be a part of the Facility Operations team responsible for operating and maintaining critical systems in our data centers. Minimum Qualifications * 6+ years of experience in electrical, HVAC, mechanical, controls, or other technical maintenance field * Associate's degree in engineering plus 4+ years experience or Bachelor's degree in related field plus 2+ years experience in electrical, HVAC, mechanical, or controls will be considered in lieu of 6+ years experience * Use hands and fingers * Reach/push/pull with arms/hands/shoulders * Stoop, kneel, crouch and crawl * Lift and/or otherwise move 45 pounds or more * Able to sit or stand at a workstation for extended periods of time Preferred Qualifications * Knowledge of mechanical, electrical, and life safety monitoring and control systems typically used in critical environments * Knowledge of EAM/CMMS systems * Experience interpreting blueprints/CAD drawings * Trade Certification or state licensure in Electrical or Mechanical (HVAC) * 8+ years experience in a data center or other Critical Environment (pharma, clean room, medical, power production, etc.) * Professional affiliations (7x24 Exchange, IFMA, Data Center Pulse, etc.) * Knowledge of critical facilities operations Responsibilities * Perform hands-on operations and maintenance which includes all physical and administrative operations tasks, service, and maintenance in accordance with site processes and procedures to ensure the highest levels of uptime, efficiency, and safety without disruption to the business * Complete work order requests accurately and on time in an enterprise asset management (EAM) system (Hexagon) * Achieve and maintain a high-level of technical knowledge regarding data center infrastructure and operations. Successfully complete personnel qualification standards (PQS) training * Provides technical expertise and assistance as required * Respond quickly, using Meta procedures or emergency operating procedures to data center facility emergencies * Regularly inspect equipment, buildings, safety routes and grounds to check or identify any abnormal or unsafe conditions or faults * Troubleshoot, evaluate and recommend system upgrades * Order parts and supplies for maintenance and repairs * Work with vendors and contractors to ensure work is in accordance with the agreed Meta processes, procedures, and standards * Escalate issues to facility management appropriately and timely * Assist in scheduling and supervising vendors/subcontractors during equipment/systems maintenance and service * Provide recommendation of improvements to the operations and maintenance program on an on-going basis * Required to work on a shift schedule, which may include nights and holidays * Utilize computerized tooling, in a control room environment, to operate remote equipment, monitor system alerts, centralize communications, diagnose faults, and prioritize dispatching of resources About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today-beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence. What you'll be doing: * Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. * Work with PD, DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving timing and power convergence, as well as ECO implementation * Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: * BS (or equivalent experience) in Electrical or Computer Engineering with 5 years experience or MS (or equivalent experience) with 2 years experience in Timing and STA * Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management. * Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis. * Expertise and in-depth knowledge of industry standard STA and timing convergence tools. * Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes. Ways to stand out from the crowd: * Background in domain specific STA and timing convergence, such as GPUs, CPUs, DPUs/Network processors, or SOCs * Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc. * Understanding and timing closure of digital logic/macros in AMS designs/IPs. * Experience in methodology and/or flow development as well as automation. NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until November 21, 2025. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA's HPC compiler group wants to hire a Compiler Developer to join the team building one of the world's most important optimizing compilers. If you want to be in the driver seat of state of the art compiler development for high-performance computing, then we want you! We're the team implementing C++ Standard Language Parallel Algorithms, OpenACC, and Flang with a keen focus on high-level optimization for GPUs and CPUs using MLIR and LLVM. What you'll be doing: Solve difficult problems at the intersection of compilers, programming models, and high-performance computing architectures Implement new and future OpenACC, OpenMP, and standard language parallelism features for C++, Fortran, and Python for NVIDIA GPUs and Multicore CPUs Participate in the evolution of standard language parallelism for GPUs and Multicore CPUs Balance individual effort with teamwork throughout debugging, prototyping, and productization Discuss and refine software designs and implementation strategies with peers Partner with application teams to investigate interesting and meaningful compilation problems from the HPC community What we need to see: Bachelors, Masters, or Ph.D. Degree in Computer Science, ECE or equivalent experience 6+ years experience developing production-quality compilers, tools, or similar software Proven understanding of compiler internals including experience targeting auto-parallelization and GPU targets Knowledge of programming fundamentals, especially in C/C++, with a deep understanding of parallel computer architectures and optimizations Ways to stand out from the crowd: Direct experience with Fortran or GPU programming models is a huge plus Experience writing code using Modern C++ Experience with GPU-based parallel computing Familiarity with C++, Fortran, OpenACC, OpenMP, or CUDA compilation You have a real passion for compiler development NVIDIA's invention of the GPU revolutionized parallel computing. Our GPUs are being used in many of the largest high-performance computing projects around the world, solving real world problems. Our products are used to build and parallelize the most meaningful scientific applications for weather modeling, climatology, fluid dynamics and defense. We support real science and scientists throughout the world. NVIDIA is widely considered to be one of high technology's most desirable employers. We have some of the most forward-thinking and experienced people in the world working for us. Our goal is to craft an environment where we can do our life's best work. If you're creative, autonomous, and highly motivated, we want to hear from you! Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until October 19, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Meta is seeking a data center Critical Facility Engineer to join our Data Center Facility Operations team. Our data centers serve as the foundation upon which our software operates to meet the demands of our customers. The Critical Facility Engineer will be a part of the Facility Operations team responsible for operating and maintaining critical systems in our data centers. **Required Skills:** Critical Facility Engineer Responsibilities: 1. Perform hands-on operations and maintenance which includes all physical and administrative operations tasks, service, and maintenance in accordance with site processes and procedures to ensure the highest levels of uptime, efficiency, and safety without disruption to the business 2. Complete work order requests accurately and on time in an enterprise asset management (EAM) system (Hexagon) 3. Achieve and maintain a high-level of technical knowledge regarding data center infrastructure and operations. Successfully complete personnel qualification standards (PQS) training 4. Provides technical expertise and assistance as required 5. Respond quickly, using Meta procedures or emergency operating procedures to data center facility emergencies 6. Regularly inspect equipment, buildings, safety routes and grounds to check or identify any abnormal or unsafe conditions or faults 7. Troubleshoot, evaluate and recommend system upgrades 8. Order parts and supplies for maintenance and repairs 9. Work with vendors and contractors to ensure work is in accordance with the agreed Meta processes, procedures, and standards 10. Escalate issues to facility management appropriately and timely 11. Assist in scheduling and supervising vendors/subcontractors during equipment/systems maintenance and service 12. Provide recommendation of improvements to the operations and maintenance program on an on-going basis 13. Required to work on a shift schedule, which may include nights and holidays 14. Utilize computerized tooling, in a control room environment, to operate remote equipment, monitor system alerts, centralize communications, diagnose faults, and prioritize dispatching of resources **Minimum Qualifications:** Minimum Qualifications: 15. 6+ years of experience in electrical, HVAC, mechanical, controls, or other technical maintenance field 16. Associate's degree in engineering plus 4+ years experience or Bachelor's degree in related field plus 2+ years experience in electrical, HVAC, mechanical, or controls will be considered in lieu of 6+ years experience 17. Use hands and fingers 18. Reach/push/pull with arms/hands/shoulders 19. Stoop, kneel, crouch and crawl 20. Lift and/or otherwise move 45 pounds or more 21. Able to sit or stand at a workstation for extended periods of time **Preferred Qualifications:** Preferred Qualifications: 22. Knowledge of mechanical, electrical, and life safety monitoring and control systems typically used in critical environments 23. Knowledge of EAM/CMMS systems 24. Experience interpreting blueprints/CAD drawings 25. Trade Certification or state licensure in Electrical or Mechanical (HVAC) 26. 8+ years experience in a data center or other Critical Environment (pharma, clean room, medical, power production, etc.) 27. Professional affiliations (7x24 Exchange, IFMA, Data Center Pulse, etc.) 28. Knowledge of critical facilities operations **Public Compensation:** $42.31/hour to $58.65/hour + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

We are now looking for a CPU Design Methodology Engineer! The complexity of chip development has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate about developing methodologies and automation solutions that enable SOC creation in the most optimized way. In this position, you will get the chance to build complex chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams. What you'll be doing: Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them Own front-end design quality checks and reviews to present the physical design team with high-quality RTL What we need to see: A Masters in Computer or Electrical Engineering or equivalent experience 5+ years of experience in chip design, specializing in SOC integration and design automation Excellent analytical and problem-solving skills Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation Strong coding skills in Perl, Python, or other industry-standard scripting languages Experience in synthesis and physical design is a plus Good interpersonal skills. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We employ some of the most forward-thinking and hardworking people in the world. Are you passionate about becoming a part of an outstanding team supporting the latest in CPU technology? If so, we want to hear from you. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until November 22, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

We are looking for a Senior CPU Design Engineer! NVIDIA is seeking best-in-class CPU Design Engineers to design the world's leading CPUs. This position offers you the opportunity to have a real impact in a dynamic, technology-focused company, designing for product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. We have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The NVIDIA CPU team is looking for inquisitive, motivated engineers with design experience to build ground-breaking CPUs. As a senior member of our design team, you will be responsible for the micro-architecture, design and implementation of high-performance, low power CPUs. You will work closely with fellow design engineers, architects, verification engineers, and physical design engineers to accomplish your tasks. What you will be doing: Drive the micro-architecture definition, feasibility studies and documentation of CPU sub-systems. Implement in RTL and coordinate execution with the verification team to ensure that the design is functional. Exercise logic design skills to optimize and meet performance, timing and power targets. Deliver a synthesis/timing clean design while working with the physical design team ensuring a routable and physically implementable design. Support hardware engineering activities including chip floor plan, power/clock distribution, chip assembly, timing closure, power and noise analysis, and back-end verification. Develop flows and tools as necessary in support of design activities. What we need to see: BS or MS in electrical engineering or computer engineering (or equivalent experience). 8+ years of proven experience in micro-architecture and RTL development of complex, high speed designs, ideally in CPU subsystems. Exposure to Computer Architecture and Digital Systems design. Highly proficient in logic design, Verilog and/or SystemVerilog, with a deep understanding of physical design and VLSI. Strengths in scripting languages such as Perl, Python. Good communication and interpersonal skills. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We employ some of the most forward-thinking and hardworking people in the world. Are you passionate about becoming a part of an outstanding team supporting the latest in CPU technology? If so, we want to hear from you. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until September 19, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This position will require the creation of integrated circuit (IC) layouts from start to finish. Using Cadence design software, you will floorplan, design, implement and verify analog integrated circuits while meeting schedule requirements. THE PERSON: We are seeking a skilled professional mid level Mask Design Engineer who has created mixed-signal, analog layout designs. Excellent problem-solving skills, attention to detail, and the ability to work independently or in a team, along with strong communication skills for creating layout designs and collaborating with stakeholders. KEY RESPONSIBILITIES: * Perform physical layout for custom analog structures in state-of-the-art sub-micron CMOS technologies using Cadence tools. * Assist in taking part in floor planning, LEF delivery, custom layout, and verifying all applicable design rules. * Perform power robustness check and EMIR verification and fixes. * Work closely with design engineers to achieve optimal circuit performance and produce high-quality layout designs. * Influence other layout designers to improve team efficiency and align design methodology. * Troubleshoot and resolve complex technical issues, ensuring high quality layout. * Work with other mask designers across AMD's many global sites to macro completion. * Effectively work in a team, good interpersonal skills, passion, and positive energy. PREFERRED EXPERIENCE: * Experience with layout design and verification tools such as Calibre verification and Cadence design tools. * Verifying design integrity through DRC, LVS, ERC, PERC, LUP and ESD, EMIR, timing, Antenna, and DFM across all major foundry processes. * Must have a deep understanding of analogue circuit layout concepts in submicron CMOS technologies, device matching, shielding, etc. * Excellent problem-solving and critical thinking skills, able to make decisions independently. * Familiarity with foundry command deck, PDK, fabrication & mask process. * Proven record of completing tasks on time or ahead of schedule while maintaining quality. ACADEMIC CREDENTIALS: * No degree requirements but would need to be senior level in mask design experience. LOCATION: Portland, OR #LI-SC3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This position will require the creation and management of integrated circuit (IC) layouts from start to finish. Using Cadence design software, you will floorplan, design, implement and verify analog integrated circuits while meeting schedule requirements. THE PERSON: We are seeking a skilled professional senior level Mask Design Engineer who has created mixed-signal, analog layout designs. Excellent problem-solving skills, attention to detail, and the ability to work independently or in a team, along with strong communication skills for creating layout designs and collaborating with stakeholders. KEY RESPONSIBILITIES: * Perform physical layout for custom analog structures in state-of-the-art sub-micron CMOS technologies using Cadence tools. * Assist in taking part in floor planning, LEF delivery, custom layout, and verifying all applicable design rules. * Perform power robustness check and EMIR verification and fixes. * Work closely with design engineers to achieve optimal circuit performance and produce high-quality layout designs. * Lead and influence other layout designers to improve team efficiency and align design methodology. * Troubleshoot and resolve complex technical issues, ensuring high quality layout. * Mentor and lead other mask designers across AMD's many global sites to macro completion. * Effectively work in a team, good interpersonal skills, passion, and positive energy. PREFERRED EXPERIENCE: * Experience with layout design and verification tools such as Calibre verification and Cadence design tools. * Verifying design integrity through DRC, LVS, ERC, PERC, LUP and ESD, EMIR, timing, Antenna, and DFM across all major foundry processes. * Must have a deep understanding of analogue circuit layout concepts in submicron CMOS technologies, device matching, shielding, etc. * Excellent problem-solving and critical thinking skills, able to make decisions independently. * Solid understanding of analog layout and all design requirements. * Knowledge of foundry command deck, PDK, fabrication & mask process. * Must have design management techniques to ensure quality and meet schedules. * Proven record of completing tasks on time or ahead of schedule while maintaining quality. ACADEMIC CREDENTIALS: * No degree requirements but would need to be senior level in mask design experience. LOCATION: Portland, OR #LI-SC3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This position will require the creation and management of integrated circuit (IC) layouts from start to finish. Using Cadence design software, you will floorplan, design, implement and verify analog integrated circuits while meeting schedule requirements. THE PERSON: We are seeking a skilled professional senior level Mask Design Engineer who has created mixed-signal, analog layout designs. Excellent problem-solving skills, attention to detail, and the ability to work independently or in a team, along with strong communication skills for creating layout designs and collaborating with stakeholders. KEY RESPONSIBILITIES: * Perform physical layout for custom analog structures in state-of-the-art sub-micron CMOS technologies using Cadence tools. * Assist in taking part in floor planning, LEF delivery, custom layout, and verifying all applicable design rules. * Perform power robustness check and EMIR verification and fixes. * Work closely with design engineers to achieve optimal circuit performance and produce high-quality layout designs. * Lead and influence other layout designers to improve team efficiency and align design methodology. * Troubleshoot and resolve complex technical issues, ensuring high quality layout. * Mentor and lead other mask designers across AMD's many global sites to macro completion. * Effectively work in a team, good interpersonal skills, passion, and positive energy. PREFERRED EXPERIENCE: * Experience with layout design and verification tools such as Calibre verification and Cadence design tools. * Verifying design integrity through DRC, LVS, ERC, PERC, LUP and ESD, EMIR, timing, Antenna, and DFM across all major foundry processes. * Must have a deep understanding of analogue circuit layout concepts in submicron CMOS technologies, device matching, shielding, etc. * Excellent problem-solving and critical thinking skills, able to make decisions independently. * Solid understanding of analog layout and all design requirements. * Knowledge of foundry command deck, PDK, fabrication & mask process. * Must have design management techniques to ensure quality and meet schedules. * Proven record of completing tasks on time or ahead of schedule while maintaining quality. ACADEMIC CREDENTIALS: * No degree requirements but would need to be senior level in mask design experience. LOCATION: Portland, OR #LI-SC3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Job Details:Job Description: At Intel, the Foundry Technology Development (TD) unit is the driving force behind Moore's Law, enabling us to create groundbreaking technology that enriches lives globally. With over 15,000 dedicated employees, Foundry TD spearheads innovative research, develops next-generation processes and packaging technologies, and manages high-volume manufacturing in state-of-the-art facilities. Within Intel Foundry TD, our Logic Technology Development (LTD) organization is at the forefront of creating and refining each process technology node, paving the way for tomorrow's computing solutions. The LTD organization is seeking a Yield Development Engineer who is passionate, innovative, and results-oriented with experience in semiconductor manufacturing equipment and systems. The individual will be expected to develop, implement, optimize, maintain, and document procedures for design database analysis supporting metrology equipment used for development and manufacturing for foundry customers. The engineer will work closely with equipment development, operations, automation, and computational and modeling technology collaborators to provide quality end-to-end foundry solutions. The candidate should be excited to work in a fast-paced environment where flexibility and adaptability is key to their success. Ability to learn rapidly in a complex and rapidly changing environment and to communicate effectively with co-workers and across teams is a must. About the Role: As a Yield Development Engineer with factory equipment focus, you will play a pivotal role in advancing our technology and foundry capabilities. Your responsibilities will include, but are not limited to: Develops tools, multivariate algorithms, and methodologies to perform high volume data analysis to identify root cause yield limiters and identify key process changes to advance yield improvement. Develops measurement recipes to provide quick and accurate feedback on product integrity, helping resolve issues with yield or product quality impact. Develops and hardens equipment capable of meeting operational and capability needs for leading edge logic node including close work with equipment vendors and internal collaborators. Develops methods, processes, and systems to consolidate and analyze diverse big data sources, establishing optimal methodologies for defect mode understanding and yield modeling, leading to accurate yield Pareto construction and process roadmap definition. Organizes, interprets, and structures insights from fab process, defect, and electrical data and detects data anomalies and drives process changes for yield enhancement. Extracts insights from structured and unstructured data by quickly synthesizing large volumes of data, and applying statistics, machine learning and coding techniques. Develops systems to transform complex experimental and manufacturing data into yield improvement actions using knowledge of product design and test features. Ensures manufacturability over process and product design through thorough analysis of process and spec corners and works with design to resolve yield issues before manufacturing ramp. Executes new product introductions, enables design technology co-optimization, and participates in design of experiments in factory task forces. Develop computational tools and AI/ML applications that improve patterning solutions, decrease process debug time, improve design efficiency, and bridge the gap between design and manufacturing. Work will span solution exploration, technical design, implementation, deployment in a production environment, and maintenance of the deployed solutions. Create innovative solutions to problems, collaborate with internal teams to ensure data integrity, implement custom algorithms to perform feature engineering, develop efficient software solutions that meet computing constraints, and ensure code quality to enable deployment in a production environment. Technically document and train collaborators on methods and best practices developed. Debug equipment, software, and procedural anomalies in the production environment which occasionally may require off hour urgent support. Join us and transform technology to create a better future. At Intel, we foster a collaborative, supportive, and dynamic environment where the brightest minds come together to achieve exceptional results. We offer: • Competitive salaries and financial benefits, including bonuses, life and disability insurance, and opportunities to purchase Intel stock at a discounted rate. • Comprehensive benefits that promote a healthy, enjoyable life, including excellent medical plans, wellness programs, time off, recreational activities, and discounts on various products and services. • A commitment to creating a more connected and intelligent future, with opportunities to make a global impact. Change tomorrow. Start today. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous jobs and internships. Minimum Qualifications: US Citizenship required. Ability to obtain and maintain an Active US Government Security Clearance. Candidate must possess one of the following: Bachelor's degree in an Engineering and/or Science discipline such as Electrical Engineering, Applied Physics, Physics, Chemistry, Materials Science, Chemical Engineering AND 4+ years of experience with semiconductor processing, semiconductor devices and circuits device physics or Nanotechnology OR Master's degree in an Engineering and/or Science discipline such as Electrical Engineering, Applied Physics, Physics, Chemistry, Materials Science, Chemical Engineering AND 2+ years of experience with semiconductor processing, semiconductor devices and circuits device physics or Nanotechnology OR PhD degree in an Engineering and/or Science discipline such as Electrical Engineering, Applied Physics, Physics, Chemistry, Materials Science, Chemical Engineering. 4+ years of professional and/or educational experience in relevant areas of FIB/SEM and TEM based materials characterization and failure analysis. Preferred Qualifications: Active US Government Security Clearance. 10+ years of advanced expertise and experience in focused ion-beam (FIB), scanning electron microscopy (SEM) and transmission electron microscopy (TEM) techniques for materials analysis with 5+ years of experience in a professional setup. 5+ years of extensive hands-on experience of FIB-SEM and TEM based characterization of semiconductor materials. Detailed knowledge of the tool-specific automation software and tool maintenance/capabilities. Demonstrated experience of Statistical Process Control (SPC) for process development and tight control of tool performance. Demonstrated experience and ability to work with external and internal partners. Experience with technical documentation, training and project management. Job location and requirements: Hillsboro, OR, USA On-site is required. Remote or Hybrid work mode is not supported. We are looking for passionate individuals who are ready to make a difference. If you are driven by innovation and eager to contribute to a team that is shaping the future, we want to hear from you. Join us at Intel and be part of something extraordinary. Benefits at Intel Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion. Job Type:Experienced HireShift:Shift 1 (United States of America) Primary Location: US, Oregon, HillsboroAdditional Locations:Business group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A Benefits: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: ********************************************************************************** Annual Salary Range for jobs which could be performed in the US: 110,880.00 USD - 216,140.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

**About the Group:** Central Engineering Group (CEG) oversees all test chip design, all foundational and hard IP, all EDA and design platform functions for Intel Products, as well as all external IP and EDA commercial licensing. The Central Engineering group is also responsible for delivering industry-leading Custom Silicon Solutions for Intel Customers in the Client and Hyperscaler Domains. **About the Role:** Intel's Central Engineering Group is seeking a Silicon Packaging Architect, responsible for bridging silicon design and advanced packaging to deliver high-performance, cost-effective solutions for next-generation SOCs and DDR PHY interfaces. **Key Responsibilities:** + Lead the co-design of silicon and package, focusing on DDR PHY and mixed signal IP integration for server SOCs. + Design bump maps, floor plans, and manage area constraints for PHYs, collaborating closely with packaging technical experts. + Conduct hands-on package extractions and simulations (signal integrity, power integrity) to assess package trace and electrical impacts, and perform risk assessments for bump-out strategies. + Finalize bump-out, floor plan, and area decisions at the end of tech readiness phases. + Interface with packaging teams on advanced technologies (e.g., C4 bumps, micro bumps, EMIB, hybrid bonding as needed). + Focus on design, development, and architecture, not process or materials engineering. **Required Experience:** + Experience in both silicon design (preferably mixed signal/analog) and packaging co-design. + Background in DDR, SOC, or similar high-speed interface development. + Hands-on expertise with bump mapping, floor planning, and packaging constraints. + Proven ability to collaborate across silicon and packaging teams, including risk assessment and simulation. + Familiarity with advanced packaging technologies (hybrid bonding, EMIB, etc.) is a plus but not required. + Individual contributor or principal engineer level preferred; management experience is not required. + Experience at leading companies in advanced packaging and PHY design (e.g., Apple, Broadcom, Qualcomm, Micron, AMD, Nvidia). **Qualifications:** + Bachelors in electrical engineering, chemical engineering, mechanical engineering, material science or similar field (Master's or Ph.D. preferred). + 10+ years in silicon and packaging co-design **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, California, Folsom **Additional Locations:** US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro **Business group:** The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. **Benefits:** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: ********************************************************************************** Annual Salary Range for jobs which could be performed in the US: 214,730.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

About the Group: Central Engineering Group (CEG) oversees all test chip design, all foundational and hard IP, all EDA and design platform functions for Intel Products, as well as all external IP and EDA commercial licensing. The Central Engineering group is also responsible for delivering industry-leading Custom Silicon Solutions for Intel Customers in the Client and Hyperscaler Domains. About the Role: Intel's Central Engineering Group is seeking a Silicon Packaging Architect, responsible for bridging silicon design and advanced packaging to deliver high-performance, cost-effective solutions for next-generation SOCs and DDR PHY interfaces. Key Responsibilities: * Lead the co-design of silicon and package, focusing on DDR PHY and mixed signal IP integration for server SOCs. * Design bump maps, floor plans, and manage area constraints for PHYs, collaborating closely with packaging technical experts. * Conduct hands-on package extractions and simulations (signal integrity, power integrity) to assess package trace and electrical impacts, and perform risk assessments for bump-out strategies. * Finalize bump-out, floor plan, and area decisions at the end of tech readiness phases. * Interface with packaging teams on advanced technologies (e.g., C4 bumps, micro bumps, EMIB, hybrid bonding as needed). * Focus on design, development, and architecture, not process or materials engineering. Required Experience: * Experience in both silicon design (preferably mixed signal/analog) and packaging co-design. * Background in DDR, SOC, or similar high-speed interface development. * Hands-on expertise with bump mapping, floor planning, and packaging constraints. * Proven ability to collaborate across silicon and packaging teams, including risk assessment and simulation. * Familiarity with advanced packaging technologies (hybrid bonding, EMIB, etc.) is a plus but not required. * Individual contributor or principal engineer level preferred; management experience is not required. * Experience at leading companies in advanced packaging and PHY design (e.g., Apple, Broadcom, Qualcomm, Micron, AMD, Nvidia). Qualifications: * Bachelors in electrical engineering, chemical engineering, mechanical engineering, material science or similar field (Master's or Ph.D. preferred). * 10+ years in silicon and packaging co-design Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Folsom Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro Business group: The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: ********************************************************************************** Annual Salary Range for jobs which could be performed in the US: 214,730.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.