Senior Design Engineer jobs at Intel

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Senior Physical Design Engineer - CPU Core
Intel Corp 4.7
Senior design engineer job at Intel
Intel's Silicon Engineering Group seeks a Senior CPU Core Physical Design Engineer to lead the physical implementation of cutting-edge processor designs from RTL to manufacturing-ready GDS. This role requires deep expertise in advanced physical design methodologies and CPU-specific design challenges to deliver world-class, high-performance, low-power processors that power Intel's industry-leading products. Key Responsibilities Physical Design Implementation * Execute complete physical design flow for custom CPU designs from RTL to GDS, creating manufacturing-ready design databases * Perform synthesis, place and route, clock tree synthesis, floorplanning, and power/clock distribution for complex CPU Cores * Conduct static timing analysis, reliability analysis, and power/noise analysis for high-performance processor designs * Optimize CPU designs to improve critical product parameters including power, frequency, and area Verification & Signoff * Execute comprehensive verification and signoff processes including formal equivalence verification and static timing analysis * Perform reliability verification, static and dynamic power integrity analysis, and layout verification * Conduct electrical rule checking (ERC) and structural design checking to ensure manufacturing compliance * Ensure design quality and manufacturability across all verification domains CPU-Specific Expertise & Optimization * Apply specialized knowledge in CPU structural and physical design including physical clock design and timing closure * Perform coverage analysis, multiple power domain analysis, structured placement, and routing optimization * Implement design-for-test (DFT) methodologies specific to CPU architectures * Collaborate closely with logic, circuit, architecture, and design automation teams to optimize microarchitectures Technology Leadership & Innovation * Work with industry EDA vendors to build and enhance tool capabilities for high-speed, low-power synthesizable CPU design * Analyze design results and provide recommendations to improve current and future CPU microarchitectures * Participate in development and improvement of physical design methodologies and flow automation * Drive adoption of advanced design techniques and emerging technologies Qualifications: The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications * Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study * 5+ years of experience in VLSI circuit design and synthesis * 4+ years of experience in static timing analysis * 4+ years of experience in low power design methodologies * Experience with physical design EDA tools (i.e. Synopsys, Cadence, Mentor Graphics) * Experience with timing closure, power optimization, and signal integrity analysis Preferred Qualifications * Postgraduate degree (Master's/PhD) in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study * Experience with x86 CPU architecture and Intel processor designs * Experience with Tcl, Perl, Python Programming * Experience in CPU microarchitecture and high-performance design principles What We Offer * Competitive compensation and comprehensive benefits * Opportunity to work on industry-leading CPU architectures and technologies * Access to cutting-edge EDA tools and advanced process technologies * Collaboration with world-class CPU architects and design engineers * Professional development and career advancement opportunities * Direct impact on products powering global computing infrastructure Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Folsom Additional Locations: Business group: The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: ********************************************************************************** Annual Salary Range for jobs which could be performed in the US: 139,710.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
$124k-159k yearly est. Auto-Apply 21d ago
Senior Silicon Design Engineer
Intel 4.7
Senior design engineer job at Intel
Intel Central Engineering Group is engaged with customers today starting with our existing foundry offerings. We are expanding at a torrid pace to include our most advanced technologies, which are ideal for high-performance applications, and they are completely dedicated to the success of its customers with full profit and loss responsibilities. Our Focus us to ensure the successful integration and adoption of Intel technologies by its original equipment manufacturers (OEMs), original design manufacturers (ODMs), and Design partners. This team serves as a critical technical interface, acting as the "voice of the customer" within Intel to drive product improvements and resolve issues throughout the entire product lifecycle. **The Senior Silicon Design Engineer** **will be responsible for, but not limited to:** + Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. + Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. + Conducts verification and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. + Analyzes results and makes recommendations to fix violations for current and future product architecture. + Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. + Optimizes design to improve product level parameters such as power, frequency, and area. + Participates in the development and improvement of physical design methodologies and flow automation. **Qualifications:** The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. **Minimum Qualifications:** + Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study. + 5+ years of experience with complex ASIC/SOC Implementation. + Experience in system and processor architecture. + Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller. + Experience with System Verilog/SOC development environment. + Experience in scripting languages (i.e. PERL, TCL, or Python). + Experience with Hardware validation techniques (i.e. formal Verification, Test and Function Verification). **Preferred Qualifications:** + Post graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study. + Experience with Industry standard protocols (i.e. PCIE, USB, DRR, etc). + Experience with interaction of computer hardware with software. + Experience with Low power/UPF implementation/verification techniques. + Experience with Formal verification techniques. **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Texas, Austin **Additional Locations:** US, California, Santa Clara, US, Oregon, Hillsboro **Business group:** Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits:** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: ********************************************************************************** Annual Salary Range for jobs which could be performed in the US: 139,710.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
$125k-160k yearly est. 60d+ ago
Senior Silicon Design Engineer
Advanced Micro Devices, Inc. 4.9
San Jose, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE We are seeking a Senior Member of Technical Staff (SMTS) SoC Architect to join our SoC Architecture team. In this role, you will define and drive architecture for critical SoC functions across roadmap and custom devices. You will focus on chip pervasive components, while ensuring seamless integration with processor subsystems, interconnect, AI accelerators, and memory systems. THE PERSON You are passionate about complex SoC architecture and thrive in cross-functional environments. You have deep technical expertise, strong analytical skills, and the ability to balance performance, power, and area trade-offs. You communicate effectively across teams and are comfortable influencing architecture decisions for next-generation silicon. KEY RESPONSIBILITIES * Define and develop SoC architecture for CPF components, including Analog IPs, clocking/reset, and silicon monitors. * Collaborate with processor, interconnect, AI, and memory subsystem architects to ensure cohesive system-level design. * Specify architecture requirements, conduct early-stage analysis, and create detailed specifications. * Drive PPA optimization and ensure scalability across roadmap and custom devices. * Partner with design, verification, and physical implementation teams to ensure functional correctness and timing closure. * Analyze trade-offs for performance, power, reliability, and manufacturability. * Influence strategies for security, safety, and reliability across CPF domains. * Strong communication and leadership skills to influence cross-functional teams. PREFERRED EXPERIENCE * Strong background in SoC architecture, including processor subsystems, interconnect, memory systems, and AI accelerators. * Expertise in Analog IPs (IOs, PLLs, eFuses, monitors), clocking/reset architecture, and silicon lifecycle management. * Familiarity with SoC on-chip protocols (e.g., AXI) and system-level QoS. * Experience with low-power design techniques, boot/reset flows, and power management. * Knowledge of design methodologies, advanced process technologies, and associated challenges. * Proficiency in modeling and automation using Python, SystemC, or similar languages. ACADEMIC & EXPERIENCE REQUIREMENTS * BS or MS or PhD in Electrical/Computer Engineering or related field. * Proven track record in delivering architecture for high-performance, low-power SoCs. LOCATION: San Jose, California #LI-DR1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$126k-160k yearly est. 51d ago
Sr. Silicon Design Engineer
Advanced Micro Devices, Inc. 4.9
San Jose, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SENIOR SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: * Develop/Maintain tests for functional verification and performance verification at the core level * Build testbench components to support the next generation IP * Maintain or improve current test libraries to support IP level testing * Create hardware emulation build to verify the IP functional performance * Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility * Provide technical support to other teams PREFERRED EXPERIENCE: * Good at C/C++ * Familiarity with SystemVerilog and modern verification libraries like UVM * Experience/Background on Computing/Graphics is a benefit * Experience with OpenGL/OpenCL/D3D programming is a benefit ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-CJ2 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$126k-160k yearly est. 60d+ ago
Sr. Silicon Design Engineer
Advanced Micro Devices, Inc. 4.9
San Jose, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are seeking a highly motivated and experienced Senior Silicon Design Engineer to join our AECG SIT team. This role involves leading and contributing to the design, integration, and characterization of advanced silicon testchips for FPGA products across cutting-edge process nodes. THE PERSON: You are an expert in IC design and manufacturing including analog/digital IP integration, chip design, silicon process or packaging technologies. A good understanding of foundry technology PDK, device physics, reliability and silicon chip manufacturing is essential. The candidate must also demonstrate effective communication, good interpersonal skills, along with a strong interest in emerging technologies and innovation. KEY RESPONSIBILITIES: * Facilitate the design and seamless integration of custom digital and analog blocks. * Support functional, timing and EMIR verification of IP blocks in custom design flow. * Collaborate cross-functionally with layout designers, IC design teams, foundry partners, CAD engineers, and test teams to ensure seamless integration and execution. * Develop end-to-end test solutions, including board-level and system-level design, for advanced test vehicle initiatives. * Assist with the bring-up and debugging of testchip silicon in lab environments. PREFERRED EXPERIENCE: * Strong foundation in circuit design and semiconductor device physics and reliability. * Hands-on experience in designing and validating circuits across advanced technology nodes such as FinFET and Gate-All-Around. * Working knowledge of digital P&R design and verification. * Working knowledge of 2.5D and 3D stacked silicon and advanced package assembly technologies. * Experience with usage of major EDA tools for device model, layout, circuit simulation, parasitic extraction, and physical verification. * Working knowledge of PCB/package design and signal/power integrity (SI/PI) analysis. * Proficiency in C/C++ and Python for programming and scripting tasks. Exposure to AI-based coding tools (e.g., GitHub Copilot) is a plus. * Hands-on experience with silicon bring-up and lab bench test equipment. ACADEMIC CREDENTIALS: Preferably holds an advanced degree (PhD or MS) in electrical & electronics engineering or physical sciences; alternatively, a bachelor's degree with 5+ years of relevant industry experience is acceptable. LOCATION: San Jose, California #LI-DR1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$126k-160k yearly est. 15d ago
ASIC Physical Design Engineer
AMD 4.9
Santa Clara, CA jobs
What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. ASIC Physical Design Engineer THE ROLE: The position will involve working with a very experienced physical design team of AMD graphics core and is responsible for delivering the physical design of blocks to meet challenging goals for frequency, power and other design requirements for AMD next generation graphics processors in a fast-paced environment on cutting edge technology. THE PERSON: Physical design Engineer with strong analytical thinking and problem-solving skills with excellent attention to detail. The candidates should have excellent communication skills, very good team player and ability to drive, lead and mentor team of engineers for project execution. KEY RESPONSIBILITIES: Physical design of complex GPU multi-millions gate design and achieve required performance, area and power targets Work with RTL design to analyze potential bottlenecks for frequency, resolve LOL and timing issue upfront in the project cycle to achieve frequency targets Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Innovus, genus PREFERRED EXPERIENCE: 10+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in leading team of Engineers for design closure Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Experience in RTL design and LOL reduction is preferred Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. Proficient in perl, python, tcl etc ACADEMIC CREDENTIALS: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Orlando FL, Santa Clara CA, Folsom CA, Austin TX, Boston, #LI-PH1 Requisition Number: 176681 Country: United States State: California City: Santa Clara Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.
$112k-148k yearly est. 60d+ ago
ASIC Physical Design Engineer-GPU
AMD 4.9
Santa Clara, CA jobs
What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. The Role: This is a great opportunity to be part of the next generation GPU chip development team at AMD Santa Clara for ASIC Physical Design engineer. You will join us as Sr. Staff Engineer / Principal Member of Technical Staff. KEY RESPONSIBILITIES: Senior level lead engineer driving PPA improvements in both pre-silicon and post-silicon design phase Drive cross-functional teams (technology, CAD tools, platform characterization , binning practices and design methodology) and optimize margining practices across boundaries to deliver best in class performance/watt Improve low voltage margining methodology and design practices to improve Vmin and performance/watt for low power GFXIP Drive design practices to improve boost frequency for GFXIP Drive silicon correlation and deliver systematic improvements to improve silicon to STA on high performance Graphics IP PREFERRED EXPERIENCE: Over 18 years' experience with BSEE/BSCS or 15+ years of MSEE or MSCE in ASIC Physical Design from RTL to GDSII Excellent analytical and problem-solving skills along with attention to details Strong RTL analysis skills including Verilog, Timing Analysis and library understanding Strong knowledge in design margining methodology, low voltage design, silicon - STA correlation Hands on experience in taping out 5nm, 7nm, 14nm and/or 16nm SOC Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics Strong communication, Time Management, and Presentation Skills Must be a self-starter, and be able to independently and efficiently drive tasks to completion Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player ACADEMIC CREDENTIALS: Bachelor's or Master's Degree in Electrical Engineering, Computer Science, or equivalent is preferred. #LI-PH1 Requisition Number: 181183 Country: United States State: California City: Santa Clara Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.
$112k-148k yearly est. 60d+ ago
ASIC Design Engineer, GPU/ML Shader Core
Advanced Micro Devices, Inc. 4.9
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for a ASIC Design Engineer, GPU/ML Shader Core who are motivated to challenge the status quo. If you are excited about building the next generation GPU/MI shader core, our team is on the lookout for you! You will be part of a fast-paced team working on the Graphics shader design, a team of engineers of varied disciplines who are responsible for micro-architecting, designing, and delivering GPU and ML/AI shader IP for various products. Since we are the heart of GPU engine, we strive to challenge ourselves in exceeding area, power, and performance targets. No idea is too small; we welcome every initiative that makes our product better. THE PERSON: You are an "out of the box" thinker, motivated to absorb dynamic changes and thirsty to keep innovating. You will work on the sub-block inside programmable engine aka shader core of the GPU. The shader core plays a key role in running applications program, feeding, and consuming the data to/from GPU shader resources and computing mathematical operations. Collaborate with software, architect, micro-architect and logic design team members to define and tackle "how to efficiently own an application program with the least number of instructions and data transfer while consuming the least amount of power". Strong interpersonal skills and an excellent teammate. KEY RESPONSIBILITIES: * Collaborate with block architect, ASIC designers and verification engineers to define and document block micro-architecture and analyze architectural trade-offs based on features, performance requirements and system limitations * Responsible for owning full design cycle from defining micro-architecture, implementing RTL, and deliver fully verified and PD timing clean design. * Consult DV engineers in describing features, outlining test plans, and closing on coverage * Assist DV engineers to debug functional, performance or power test failures * Work with Physical Design team to close on timing, area and power requirements PREFERRED EXPERIENCE: * Experience in micro-architecture and RTL development (Verilog), focused on GPU/CPU/ML/AI pipelines, arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. * Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. * Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required. ACADEMIC CREDENTIALS: * Undergraduate degree required. Bachelors or Masters degree in Computer Engineering/Electrical Engineering preferred. LOCATION: * Santa Clara CA - San Diego CA - Folsom CA This role is not eligible for Visa sponsorship. #LI-BM1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$112k-148k yearly est. 10d ago
Senior ASIC RTL Design Engineer
Advanced Micro Devices, Inc. 4.9
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the AMD, you will help bring to life cutting-edge designs and deliver IPs to SOC. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi - site environment are keys to being successful in this role. KEY RESPONSIBLITIES: * RTL design of high speed design, clock/reset/power features, IP Integration, sub-system level design * Architect and design of power management features. * Design optimization for implementing power efficient IP, implementing the RTL using low power techniques * Responsible for the inter IP integration issues resolution * Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem. * Work closely with FEINT, DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design * Architecting, micro-architecting and documentation of the design features * Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: * Extensive experience in Digital IP/ASIC design and Verilog RTL development * Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. * Should be well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation. * Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects. Should possess expertise in front-end EDA tools sign-off and its flows. * Familiarity with low power design and low power flow is an added plus. * Ability to program with scripting languages such as Python or Perl is a plus; * Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements; * Proven interpersonal skills, leadership and teamwork; * Excellent writing skills in the English language, editing and organizational skills required; Skilled at prioritization and multi-tasking; * Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts; * Knowledge of, or experience in, functional design verification or design is highly desired. ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering This role is not eligible for visa sponsorship. LOCATION: Santa Clara, CA #LI-SC3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$112k-148k yearly est. 3d ago
Lead Design Verification Engineer
Advanced Micro Devices, Inc. 4.9
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are seeking a seasoned Lead Design Verification Engineer with expertise in verifying networking chip. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead verification teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: We are seeking an experienced and hands-on Lead Design Verification Engineer to drive the verification strategy, methodology, and execution for our next-generation high-performance networking chip. The ideal candidate will have deep expertise in SoC/ASIC verification, strong knowledge of networking protocols and architectures, and a proven ability to lead verification teams in a fast-paced environment. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: * Ownership of verification strategy for one or more major IP blocks or subsystems within a complex networking ASIC. * Architect and implement testbenches using UVM/SystemVerilog, ensuring maximum coverage and quality. * Develop and maintain test plans, coverage models, and scoreboards to ensure comprehensive verification of all design features. * Lead and mentor a team of DV engineers - drive reviews, define milestones, and ensure high-quality deliverables. * Collaborate closely with design, architecture, and software teams to define verification requirements and debug issues across the full chip. * Develop and maintain automation and regression infrastructure, including CI/CD integration. * Drive coverage closure and signoff for IP and SoC-level verification. * Contribute to methodology improvements, verification IP reuse, and best practices across the DV organization. * Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements * Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: * Proven line management experience, including hiring, mentoring, and performance management of DV engineers. * Demonstrated ability to build and lead high-performing verification teams, setting goals and driving execution across projects. * Experience with chip-level verification for networking ASICs, switches, or routers. * Familiarity with traffic generators, packet-level verification, and network protocol stacks. * Knowledge of SystemC, C testbenches, or hardware/software co-verification. * Exposure to emulation or FPGA prototyping environments (e.g., Palladium, Veloce). * Prior experience leading cross-site or multi-IP verification efforts. * Strong communication, collaboration, and leadership skills with the ability to influence technical direction across disciplines. ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in related discipline preferred LOCATION: Santa Clara, CA This role is not eligible for VISA sponsorship #LI-BW1 #LI-hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$118k-158k yearly est. 50d ago
Design Verification Engineer
Advanced Micro Devices, Inc. 4.9
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Graphic Memory Controller(GMC) is an IP that delivers into all SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for a design verification engineer in the Dram Controller IP at AMD's Santa Clara, CA Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. This is a highly visible position in a growing team. Leadership opportunity is available. We are seeking a highly skilled Formal Verification Expert to join our talented team as a Staff Engineer and technical lead. This role is crucial to ensuring IP quality through rigorous formal verification processes. THE PERSON: The successful candidate will play a key role in developing verification strategies, leading formal verification team, and collaborating across departments to ensure the highest quality standards. KEY RESPONSIBILITIES: * Lead formal verification team to ensure IP quality and project execution. * Develop and implement comprehensive formal verification plans, including constraint/assertion property development, model development, inconclusive issue resolve and sign off, etc.. * Collaborate with IP architects, hardware designer, verification engineers, and other stakeholders to design efficient formal verification strategies. * Mentor and guide junior engineers in formal verification techniques and best practices. * Communicate results and progress effectively to cross-functional teams, providing insights and actionable recommendations. * Drive continuous improvement in formal verification processes and contribute to the advancement of the organization's verification capabilities. PREFERRED EXPERIENCE: * Proven experience in formal verification and simulation, model checking, and theorem proving applied to complex IP or systems. * Proficiency in formal verification tools such as VC-Formal or JasperGoal * Strong understanding of hardware description languages (e.g., VHDL, Verilog) and/or programming languages (e.g., System verilog, C, C++, Python). ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Santa Clara, CA This role is not eligible for visa sponsorship #LI-SL3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$118k-158k yearly est. 26d ago
IP Design Verification Engineer
Advanced Micro Devices, Inc. 4.9
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. You will participate in design verification methodology definition as well as contribute to design verification infrastructure that facilitates maximum re-use of components, improves productivity, and guarantees to the maximum extent possible, bug-free designs. THE PERSON: You have a passion for digital design and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems KEY RESPONSIBILITIES: * Collaborate with architects, hardware and firmware engineers to understand the features to be verified * Take ownership of different verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL simulations and work with HW and FW development teams to verify fixes * Review functional and code coverage metrics to meet the coverage requirements * Develop and improve existing verification flows and environments * Provide technical support to other teams PREFERRED EXPERIENCE: * Proficient in IP level ASIC verification * Experience identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills * Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE) * Working knowledge of Formal Verification methods and apps ( FPV, CC, Sequence equivalence, etc.) * Proficient in debugging firmware and RTL code using simulation tools * Proficient in using UVM testbenches and working in Linux and Windows environments * Experienced with Verilog, System Verilog, C, and C++ * Developing UVM based verification frameworks and testbenches, processes and flows * Automating workflows in a distributed compute environment. * Good understanding and hands-on experience in the UVM concepts and SystemVerilog language * Good to have : prior experience with USB / PCIE / UFS Controllers. ACADEMIC CREDENTIALS: * Bachelors or Masters degree in Computer Engineering/Electrical Engineering LOCATION: Santa Clara, Folsom, CA Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$118k-158k yearly est. 4d ago
DDR Design Verification Engineer
Advanced Micro Devices, Inc. 4.9
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an experienced Verification Engineer to join our team as a Technical Lead for cutting-edge server memory products. This individual will be responsible for driving the verification efforts of DDR interfaces, including advanced memory protocols such as DFI, DDR5, and LPDDR5, across a range of DIMMs (Dual In-line Memory Modules). The ideal candidate will possess expert-level knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl, and will have a proven track record of multiple tape-out experiences and successful verification sign-offs in a high-performance server memory environment.. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: * Technical Leadership & Project Oversight: Lead and guide a team of verification engineers in the development and execution of verification strategies for DDR5, LPDDR5, and DFI memory systems in server products. * Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface. * Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements * Knowledge sharing and other contributions to verification methodology * As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests * Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs * Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: * Developed and implemented SystemVerilog and UVM (Universal Verification Methodology) based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems. * Worked closely with hardware, firmware, and software teams to align on system-level memory architecture, identify potential integration issues, and define validation requirements early in the design phase. * Provided technical leadership across multiple teams, driving cross-functional collaboration to solve complex issues in memory systems, from firmware to hardware. * Built VIPs and BFMs for memory interfaces from scratch (preferrable) * GLS, NLP, XPROP simulation experience is required * Strong proficiency in system verilog assertions, constraints and coverage. * Worked in formal verification methods, with proven record of tool usage beyond the standard apps. * Working knowledge of DFT flows (preferrable) * Excellent communication, management, and presentation skills. * Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in related discipline preferred LOCATION: Santa Clara, CA #LI-SC3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$118k-158k yearly est. 5d ago
SERDES Analog Mixed Signal Circuit Design Engineer
Advanced Micro Devices, Inc. 4.9
San Jose, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD Serdes Technology Group develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS process. We are currently seeking an analog/mixed-signal design engineer to join our world-class team. THE PERSON: The candidate will be responsible for the design of high-speed ADC-based receivers, DAC-based transmitters, or silicon photonics transceivers. KEY RESPONSIBILITIES: * Define circuit architectures optimized for high bandwidth electrical and optical links * Perform link level simulation in Matlab and/or SPICE to prove the architecture * Perform design and modeling of on-die RF passive components (e.g., inductors and capacitors) and/or optical structures * Design circuit components (e.g., DAC, SAR-ADC, S/H, Analog Front-End, PLL, reference generation, clock distribution) required to implement the architecture in advanced FinFET process PREFERRED EXPERIENCE: * Strong background in analog and mixed-signal circuit design * Strong teamwork and communication skills * History of coming up with innovative circuit design/architecture is a plus ACADEMIC CREDENTIALS: * BS or MS or PhD in Electrical Engineering or Computer Engineering or related equivalent. LOCATION: San Jose, CA #LI-TB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$113k-145k yearly est. 53d ago
Staff ASIC Design Engineer - AI Engine
AMD 4.9
San Jose, CA jobs
What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ Staff ASIC Design Engineer - AI Engineer- 152880 THE ROLE: AMD-Xilinx is seeking a capable and motivated RTL/ASIC design engineer to be part of front-end design team of next generation AI Engine/ML processors. THE PERSON: You will take part in design and implementation of high-performance, low-power processor and accelerator IP for AI/ML applications. KEY RESPONISIBILITES: In this role you will: Define and specify micro-architecture of processor building blocks based on architecture requirements RTL design and debug of complex blocks in Verilog / System Verilog Analyze performance and make implementation choices to optimize timing Analyze and optimize design for power efficiency and power integrity Work with verification and physical design teams to achieve high quality design and successful tape out Solve customer problems through innovative enhancements to product architecture/ micro-architecture Design and implement underlying clocking infrastructures to ensure implementation tool requirements are met and are optimized for compile time and memory Collaborate with cross-functional teams to solve novel problems across multiple functional areas in development of clocking features and/or algorithms PREFERRED EXPERIECE: Strong experience in the following ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes Digital design and experience with RTL design in Verilog/System Verilog Circuit timing/STA, and practical experience with Prime Time or equivalent tools Low power digital design and analysis Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation Experience in following is highly desired Understanding of FPGA architecture and implementation flow TCL, Perl, Python scripting Version control systems such as Perforce, ICManage or Git Strong verbal and written communication skills Ability to organize and present complex technical information Fluent in working with Linux environment Needs to be manually updated. ACADEMIC CREDENTIALS BSEE or equivalent and 8 years of relevant work experience, or MSEE or equivalent with 6 years of experience LOCATION:San Jose, CA #LI-DA1 Requisition Number: 152880 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.
$112k-148k yearly est. 60d+ ago
STA ASIC Design Engineer
Advanced Micro Devices, Inc. 4.9
San Jose, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate's responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred. THE PERSON: High energy candidates with strong written and verbal communication skills, and structured, well-organized work habits will be successful. Team and goal oriented are essential. KEY RESPONSIBILITIES: * Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff * Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency. * Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA checks. * collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows. * Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts) PREFERRED EXPERIENCE: * Worked with EDA tools that enable RTL quality checks * Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. * Experience with analyzing the timing reports and identifying both the design and constraints related issues. * Ability to multitask, grasp new flows/tools/ideas. * Experience in improving the methodologies. * Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. * Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT) * Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters * Strong analytical and problem-solving skills ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA This role is not eligible for visa sponsorship. #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$112k-148k yearly est. 60d+ ago
Silicon Design Verification Engineer.
Advanced Micro Devices, Inc. 4.9
San Jose, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD/Xilinx programmable devices. THE PERSON: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: * Collaborate with architects, hardware and firmware engineers to understand the new features to be verified * Take ownership of block level verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes * Review functional and code coverage metrics to meet the coverage requirements * Develop and improve existing verification flows and environments PREFERRED EXPERIENCE: * Strong understanding of computer architecture and logic design * Knowledge of Verilog, system Verilog and UVM is a must * Familiarity with common security protocols and algorithms, including hashing, digital signatures, and encryption standards like AES and SHA. * Strong understanding of computer architecture and logic design * Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification * Working knowledge of C/C++ and Assembly programming languages * Exposure to scripting (python preferred) for post-processing and automation * Experience with gate level simulation, power and reset verification ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
$118k-158k yearly est. 60d+ ago
Silicon Design Engineer 1
AMD 4.9
San Jose, CA jobs
What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ TITLE: Design Engineer At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. THE ROLE: This position is within the AMD SERDES Technology team in San Jose, CA, looking for a talented and motivated team member with a focus on FPGA design and hands on silicon bring-up. You will use your knowledge of high-speed SerDes and design experience to develop various solutions for common high-speed SerDes interfaces and applications. RESPONSIBILITIES: FPGA design and IP solutions development Develop embedded firmware for validation and applications development Work with internal teams to create IP solution, debug features associated with physical layer functionalities Provide customer support and field debugging as required Preferred Skills & Experience: FPGA design and debug experience C/C++ for embedded system development Knowledge of physical layer specifications in IEEE 802.3 and / or PCIe Programming experience in Python or Perl scripting languages Hands-on experience with various lab equipment for silicon bring-up and validation Knowledge of 50G+ multi-level (i.e. PAM4) SERDES is preferred Excellent verbal and written communication skills ACADEMIC CREDENTIALS: B.S. or M.S. Electrical or Computer Engineering preferred Requisition Number: 179684 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.
$118k-155k yearly est. 60d+ ago
Physical Design Application Engineer
Synopsys, Inc. 4.4
Sunnyvale, CA jobs
Category Engineering Hire Type Employee Job ID 12583 Base Salary Range $157000-$235000 Remote Eligible No Date Posted 21/08/2025 This position requires access to or use of information, which is subject to export restrictions, including the International Traffic in Arms Regulations (ITAR). All applicants for this position must be "U.S. Persons" within the meaning of the ITAR. "U.S. Persons" include U.S. Citizens, U.S. Lawful Permanent Residents (i.e. 'Green Card Holders'), Political Asylees, Refugees or other protected individuals as defined by 8 U.S.C. 1324b(a)(3). This role is required to work onsite in our Sunnyvale CA location. We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced engineer with a deep understanding of the RTL to GDSII flow. You thrive on solving complex technical issues and enjoy working closely with customers to enhance their experience with cutting-edge technology. With your strong background in synthesis, physical design, and static timing analysis, you excel in diagnosing and resolving technical challenges. You are an excellent communicator, capable of conveying technical concepts clearly and effectively to both technical and non-technical stakeholders. Your scripting skills in Perl, Tcl, and Python, along with your knowledge of CAD automation methods, make you a valuable asset to any team. You are motivated to work collaboratively with internal teams and customers to drive product adoption and satisfaction. What You'll Be Doing: * Providing technical and engineering insight to support and improve the usability, applicability, and adoption of Synopsys products. * Diagnosing, troubleshooting, and resolving complex technical issues on customer installations. * Deploying and training customers on new implementations and capabilities. * Reviewing and acting upon product feedback and solutions performance from customers and other application partners. * Working directly with R&D to develop and implement the technical roadmap, specifications, and validation for improvements and enhancements. * Partnering with customer technical managers and Sales to identify business challenges and develop effective technical solutions for new accounts. The Impact You Will Have: * Enhancing customer satisfaction by ensuring seamless product deployment and support. * Driving product adoption and utilization through effective technical training and support. * Contributing to the technical roadmap and product improvements based on customer feedback. * Supporting the sales team in acquiring new accounts by providing technical expertise. * Improving product performance and reliability through collaborative efforts with R&D. * Strengthening customer relationships by addressing and resolving technical challenges promptly. What You'll Need: * 7+ years of RTL to GDSII full flow experience or knowledge. * In depth experience debugging complex engineering issues related to STA, DRC/DRV and PPA optimization * Exceptional interest and knowledge of Advanced Node & Design methodologies. * Proven aptitude and motivation to work with internal and customer groups. * Excellent verbal and written presentation/communication skills. * Hands-on experience in synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis. * Knowledge of ASIC implementation domains outside of RTL2GDS including RTL coding, Verification, formal checking is a plus. * Good scripting skills (Python, Tcl, Perl); working knowledge of CAD automation methods. Who You Are: * A collaborative team player who thrives in a dynamic environment. * An excellent communicator with the ability to convey complex technical concepts effectively. * A proactive problem-solver with a keen eye for detail. * Customer-focused, with a passion for delivering exceptional service and support. * A continuous learner, always seeking to expand your technical knowledge and skills. The Team You'll Be A Part Of: You will be part of a highly skilled and dedicated team of engineers focused on providing exceptional technical support and solutions to our customers. Our team collaborates closely with R&D, Sales, and Customer Success to drive product innovation, adoption, and satisfaction. We value continuous learning, open communication, and a customer-centric approach in everything we do. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
$157k-235k yearly 18d ago
Physical Design Applications Engineer
Synopsys, Inc. 4.4
Sunnyvale, CA jobs
Category Engineering Hire Type Employee Job ID 13867 Base Salary Range $109000-$163000 Remote Eligible No Date Posted 20/12/2025 At Synopsys, we drive the innovations that shape the way the world connects and computes. Our technology powers cutting-edge silicon in applications from mobile and AI to autonomous systems and advanced computing. Join us to help customers achieve breakthrough performance using our leading EDA tool suite. We are seeking a Physical Design Engineer with strong technical skills in digital implementation and optimization. In this role you will work with engineering teams and customers to deliver solutions that drive timing closure, power and area optimization, and robust RTL-to-GDS flows using Synopsys tools. You Are You are an ASIC/physical design engineer with 2-4 years of hands-on experience in digital implementation flows. You understand full RTL-to-GDS design flows and are comfortable applying state-of-the-art methodologies to achieve timing closure and quality signoff. You have solid scripting skills to automate flows and customize solutions, and you communicate clearly with internal teams and customers to solve complex design challenges. What You'll Be Doing * Execute RTL-to-GDSII digital implementation flows, including logic synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off quality closure. * Work with customers and internal teams to troubleshoot and optimize implementation challenges, propose solutions, and deliver highly-tuned PPA results. * Utilize Synopsys tools such as Fusion Compiler, PrimeTime, and DSO.ai/FusionAI in digital implementation and static timing analysis. * Develop and enhance automation scripts and flows using TCL, Python, Perl, or other scripting languages. * Perform static timing analysis (STA), debug timing violations, and implement ECOs to improve performance and timing closure. * Drive DRC/LVS/Signoff quality closures at advanced technology nodes. * Collaborate with customers, product teams, and research groups to share best practices and feedback to improve tool flows. What You'll Need * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. * 2-4 years of hands-on experience in digital physical design or backend implementation. * Experience with full RTL-to-GDS flows, including place & route methodologies, STA, timing closure, and signoff strategies. * Proficiency with Synopsys tools such as Fusion Compiler, PrimeTime, and familiarity with AI-assisted optimization tools (e.g., DSO.ai/FusionAI) is highly desirable. * Solid scripting skills in TCL, Python, Perl, or equivalent for flow automation. * Strong analytical ability to dissect complex timing, PPA, and design challenges. * Familiarity with unix/linux environments and engineering workflows. * Excellent communication skills and ability to work in collaborative team and customer-facing environments. Who You Are * A proactive self-starter who takes ownership of technical solutions and delivery. * Comfortable interfacing with customers and internal teams to understand requirements and deliver effective outcomes. * Able to adapt to evolving methodologies and rapidly learn emerging tool capabilities in EDA. * Detail-oriented and organized, capable of balancing multiple priorities in a fast-paced environment. The Team You'll Be Part Of Join a dynamic Applications Engineering team dedicated to customer success and powerful EDA solutions. You'll work closely with fellow engineers, researchers, and tool developers to enable high-performance physical design solutions and push the boundaries of what's possible in semiconductor design. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
$109k-163k yearly 7d ago

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