Senior Principal Engineer jobs at Intel - 1111 jobs
Senior Logic Design Engineer - Remote
Intel Corporation 4.7
Senior principal engineer job at Intel
A leading technology company in California seeks an IP Logic Design Engineer with a Bachelor's degree in relevant fields and at least 3 years of experience in IP design. The role includes designing, integrating, and validating silicon solutions while collaborating with architecture teams. Preferred qualifications include experience with scripting, hardware validation, and industry protocols. This position allows for remote work with competitive compensation ranging from $164,470 to $232,190 USD annually.
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$164.5k-232.2k yearly 5d ago
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Senior Logic Design Engineer
Intel Corporation 4.7
Senior principal engineer job at Intel
# **Welcome!**## .# **Job Details:**## :Job Description**Do Something Wonderful!**Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.or the links below!**WHO WE ARE:**We are a Custom IP and Silicon engineering team part of Intel's Silicon Engineering Group. The team works on design and verification of cutting edge IP and SoCs geared towards Intel's advanced Data center and AI SoCs. We look to drive major technological and methodological advancements across multiple areas of IP and SoC Design and Verification, looking to set a high bar across the organization and ensure that Intel has a competitive product in the market.**WHO YOU ARE:**As an IP Logic Design Engineer your responsibilities will include but are not limited to:* Designing and/or integrating IP for Intel's Custom Silicon solutions.* You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation.* Creating a design to produce key assets that help improve product KPIs for discrete graphics products.* Working with SoC Architecture and platform architecture teams to establish silicon requirements.* Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule.* Creating micro architectural specification document for the design.* Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs.* Driving vendor's methodology to meet world class silicon design standards.* Architecting area and power efficient low latency designs with scalabilities and flexibilities.* Power and Area efficient RTL logic design and DV support.* Running tools to ensure lint-free and CDC/RDC clean design, VCLP.* Synthesis and timing constraints.* Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.## **Qualifications:****Minimum Qualifications:**Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 3+ years of relevant experience- or -Master's degree in the same fields with 2+ years of relevant experience- or -PhD in the same fields.Relevant work experience should be of the following:* Experience with complex IP/ASIC/SOC Design Implementation.* Experience in system and processor architecture.* Experience with System Verilog/SOC development environment.Preferred Qualifications:* Experience in scripting languages (i.e. PERL, TCL, or Python).* Experience with Hardware validation techniques (i.e. formal Verification, Test and Function Verification).* Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller.* Experience in leading small team of engineers.* Experience with Industry standard protocols (i.e. PCIE, USB, DDR, etc).* Experience with interaction of computer hardware with software.* Experience with Low power/UPF implementation/verification techniques.* Experience with Formal verification techniques.## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:Virtual US## Additional Locations:## Business group:At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A## BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the .Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. \* Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 12/31/2027\*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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$164.5k-232.2k yearly 5d ago
Senior Principal Electronics Engineer - Hardware and Software Integration Lead
Northrop Grumman Corp. (JP 4.7
San Diego, CA jobs
At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work - and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.
Northrop Grumman Aeronautics Systems is looking to add a SeniorPrincipal Electronics Engineer - Hardware and Software Integration Lead to join our team in San Diego (Rancho Bernardo), CA. This position will support the RQ- 4B program.
This position will be responsible for the development of next generation ground system solutions within the Mission Systems Integrated Product Team (IPT) and will be the technical lead and primary interface for the Ground Control software supporting deficiency investigations, development, integration, testing, and sustainment artifacts for updates to the system with a major Hardware and software supplier.
Duties and Responsibilities include, but are not limited to:
Coordinating the efforts of the software supplier for multiple software programs and efforts and seeing projects through from start to finish.
Coordinating with the subcontracts management team, systems engineering, supplier quality assurance representatives, safety engineers, cyber team, test team, logistics engineers, cost account manager, and scheduler.
Monitoring and advising on critical dependencies intercedences for ground segment and implementation integration
Coordinating and managing the execution of all phases of software performance, including planning, new capability development, testing, deliveries, deployment, and sustainment.
Reviewing supplier, hardware, and software product documentation.
Reporting hardware upgrades and software supplier status to upper management.
The selected candidate should thrive working in a fast-paced work environment with high expectations, engaged in significantly diverse assignments, within a collaborative/team setting across all levels of the organization. This position requires excellent communication skills to manage the Ground Control hardware and software updates and ensure all design, development, and artifacts are correct.
The selected candidate will be required to work full-time, on-site at our facility. Once in the role, this position could possibly offer a hybrid work environment. Scheduled telework days are approved at manager's discretion. This position requires the ability to travel up to 25% of the time.
Basic Qualifications
Bachelor's Degree in a STEM (Science, Technology, Engineering or Mathematics) discipline and 8 years of related experience; OR a Master's degree in a STEM discipline and 6 years of related engineering experience; OR a PhD in a STEM discipline with 4 years of related engineering experience.
Experience working with aerospace Ground System architecture
Experience in creating engineering drawings and conducting system audits
Experience with programming and scripting languages
Active DoD Secret (or higher) clearance (with a background investigation within the past 6 years or enrolled into Continuous Evaluation).
Ability to obtain and maintain Special Program Access (SAP).
Preferred Qualifications
Degree in Computer Science or Electronic/Electrical Engineering
Experience managing hardware and Software related issues with supplier-based interaction as part of a Government/DOD contract
Familiarity with full hardware integration and Software Development Life Cycles
Experience with software and development, integration, and testing to include Agile, JIRA, Confluence programs
Experience with government acquisition related to hardware and software development and sustainment activities
Familiarity with Prime and supplier hardware and software proposal development including technical evaluations of supplier proposals.
CAM/EV experience
Primary Level Salary Range: $142,200.00 - $213,400.00
The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.
Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.
The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.
Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit *********************************** U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.
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$142.2k-213.4k yearly 4d ago
Principal OR Sr. Principal Electronics Engineer (Ground System Architect/Integrator)
Northrop Grumman Corp. (JP 4.7
San Diego, CA jobs
At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work - and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.
Please note that this opportunity is contingent on program funding. Start dates are determined after funding confirmation.
Northrop Grumman Aeronautics Systems is looking to add a Principal OR Sr. Principal Electronics Engineer (Ground System Architect/Integrator) to our team in San Diego Rancho Bernardo, CA. This position will support the RQ-4 program.
This candidate will be responsible for the development of next generation ground system solutions within the Mission Systems Integrated Product Team (IPT).
Duties and Responsibilities include, but are not limited to:
Determine customer needs and develop approaches, implementations, components, and interfaces, while identifying standards and constraints, civil requirements, and security needs in the software deployment of the system.
Survey the industry for awareness of customer needs and alternative systems.
Lead trade studies, technology development, and subcontractor teams.
Lead technical and cost proposals
Write white papers describing the offerings and provide leadership and/or direction to software integration and deployment, test leads and engineering team.
The selected candidate will be required to work full-time, on-site at our facility. Once established in role, the position could potentially offer a hybrid work environment. Scheduled telework days are approved at manager's discretion. This position requires the ability to travel up to 25% of the time.
- This position can be filled at either the Principal Electronics Engineer level or the SeniorPrincipal Electronics Engineer level, depending upon the qualifications below.
Basic Qualifications for Principal Electronics Engineer (Ground System Architect/Integrator)
Bachelor's Degree in a STEM (Science, Technology, Engineering or Mathematics) discipline and 5 years of related engineering experience; OR a Master's degree in a STEM discipline and 3 years of related engineering experience; OR a PhD in a STEM discipline and 1 year of related engineering experience.
Demonstrated understanding of Ground System architecture including UAV Command and Control (C2), classified and unclassified networks, network storage devices, security appliances, and government external interfaces.
Knowledge of/experience with common ground approaches, implementations, components, standards, interfaces, constraints, and security needs.
Working knowledge of systems engineeringprinciples, processes, software/hardware integration, and system software deployment.
Active DoD Secret (or higher) clearance (with a background investigation within the past 6 years or enrolled into Continuous Evaluation) with the ability to obtain and maintain a DoD Top Secret clearance.
Basic Qualifications for SeniorPrincipal Electronics Engineer (Ground System Architect/Integrator)
Bachelor's Degree in a STEM (Science, Technology, Engineering or Mathematics) discipline and 8 years of related engineering experience; OR a Master's degree in a STEM discipline and 6 years of related engineering experience; OR a PhD in a STEM discipline and 4 years of related engineering experience.
Demonstrated understanding of Ground System architecture including UAV Command and Control (C2), classified and unclassified networks, network storage devices, security appliances, and government external interfaces.
Knowledge of/experience with common ground approaches, implementations, components, standards, interfaces, constraints, and security needs.
Working knowledge of systems engineeringprinciples, processes, software/hardware integration, and system software deployment.
Active DoD Secret (or higher) clearance (with a background investigation within the past 6 years or enrolled into Continuous Evaluation) with the ability to obtain and maintain a DoD Top Secret clearance.
Preferred Qualifications for both levels
Experience with Agile development and JIRA.
Experience with IFC Upgrade to include integration and fielding for operational purposes
Experience with the RQ-4 program.
Experience writing and presenting technical information to customer and internal management audience.
Experience with Cyber Security requirements and/or implementation.
Experience in initial design, review, and the approval process and implementation thereof said design cradle to grave.
Experience in Teamcenter, release process, CATIA and CAD drawing.
Experience with supplier subcontractors and supplier SOW.
Primary Level Salary Range: $114,000.00 - $171,000.00
Secondary Level Salary Range: $142,200.00 - $213,400.00
The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.
Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.
The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.
Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit *********************************** U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.
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$142.2k-213.4k yearly 6d ago
Senior Mask Layout Engineer - Hybrid, Analog CMOS
Nvidia Corporation 4.9
Santa Clara, CA jobs
A leading technology company in California is seeking a Senior Mask Layout Design Engineer to perform physical layout for digital and mixed-signal functions. You'll collaborate with multi-disciplinary teams and have a significant role in mentoring junior mask designers. Ideal candidates should have a BS in Electrical Engineering and over 7 years of layout design experience with expertise in Cadence tools. This position offers a competitive salary and a hybrid work model.
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$138k-180k yearly est. 5d ago
Principal ML Engineer for AI-Driven Cyber Defense
Cisco Systems 4.8
San Jose, CA jobs
A leading technology company in San Jose is seeking a candidate for a role focused on designing and building AI-driven workflows for security operations. Candidates should have a strong background in security operations, extensive Python development experience, and familiarity with security data tools. You'll collaborate closely with various teams to enhance detection and response strategies. The position offers competitive compensation ranging from $291,500 to $369,100, alongside a rich suite of benefits.
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$291.5k-369.1k yearly 4d ago
Senior ML Engineer - GenAI & RAG Platforms
Cisco Systems 4.8
Santa Clara, CA jobs
A global technology leader seeks an experienced engineer to develop AI-driven services and APIs for its hybrid, multi-cloud environment. Ideal candidates will have 5+ years in backend or distributed systems and proficiency in modern programming languages like Python or TypeScript. Responsibilities include implementing features for GenAI services and collaborating on product development. Competitive salary range of $181,000 to $235,000 and robust benefits are offered.
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$181k-235k yearly 2d ago
Senior Physical IC Design Engineer: RTL to Tape-out
Broadcom Inc. 4.8
San Jose, CA jobs
A leading technology company is seeking a Physical IC Design Engineer in San Jose, California. The role involves executing various physical design tasks and requires a bachelor's degree in Electrical or Electronics Engineering with over 12 years of relevant experience. Strong scripting skills and expertise in EDA tools are essential. The position offers a competitive salary range of $141,300 - $226,000 along with comprehensive benefits including health insurance, 401(K) matching and more.
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$141.3k-226k yearly 4d ago
Senior ML Engineer - GenAI & RAG Platforms
Cisco Systems 4.8
Palo Alto, CA jobs
A global technology leader is seeking an experienced engineer to implement GenAI services and APIs enhancing Splunk products. Candidates should have over 5 years of backend systems experience, excel in Python or TypeScript, and possess knowledge of LLM APIs. This role offers competitive pay and a variety of benefits including medical insurance, retirement plans, and generous paid time off, with a salary range of $181,000 to $235,000 annually based in Palo Alto, California.
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$181k-235k yearly 2d ago
Staff ML Engineer - AI-Powered Observability Platform
Cisco Systems 4.8
San Jose, CA jobs
A global technology company is looking for a seasoned software engineer to enhance AI capabilities within their observability platform. Candidates should have a strong background in AI/ML systems, cloud computing, and robust technical leadership. This role is pivotal in driving innovation in data analysis and delivering scalable solutions. The ideal candidate will thrive in an agile environment and provide mentorship to junior engineers. Enjoy competitive salaries and benefits while contributing to impactful technology solutions.
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$151k-191k yearly est. 4d ago
Senior ML Engineer - GenAI & RAG Platforms
Cisco Systems 4.8
Sunnyvale, CA jobs
A leading technology company is seeking a skilled professional to implement GenAI services and APIs that enhance chat assistants and automation workflows. Candidates should have extensive experience in backend or distributed systems and be proficient in modern programming languages. Excellent collaboration skills with product management is crucial for delivering impactful GenAI experiences. The position offers competitive salary with benefits in the Sunnyvale area.
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$138k-175k yearly est. 2d ago
Senior ML Engineer, Real-Time Observability & AI
Cisco Systems 4.8
San Francisco, CA jobs
A leading technology firm in California is seeking an experienced software engineer to join its team. You will be responsible for building scalable cloud-based systems and applying the latest developments in AI technologies. The ideal candidate will possess a master's degree and extensive software engineering experience, preferably in AI/ML domains. Collaboration and technical leadership are key aspects of this role, promising impactful contributions towards advancing cloud solutions.
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$138k-175k yearly est. 4d ago
Senior NLP & Language AI Engineer
Cisco Systems 4.8
San Jose, CA jobs
A leading tech firm is seeking a recent graduate or final-year PhD/Master's student for a role focused on advancing NLP research within their Language AI features. Responsibilities include conducting rigorous research, collaborating with product managers, and innovating in AI solutions. Ideal candidates will have a strong background in machine learning and natural language processing, and experience with Python. This position is located in San Jose, California, and offers a competitive salary package.
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$138k-175k yearly est. 6d ago
Senior ASIC Emulation Engineer - SoC Prototyping
Meta 4.8
Sunnyvale, CA jobs
A leading technology company in Sunnyvale is seeking engineers to build ASIC/System on Chip (SoC) solutions for data center applications. The role involves emulation and prototyping, with responsibilities including delivering high-quality models and collaborating with various teams. The ideal candidate should have a bachelor's degree and over 6 years of experience in EDA tools and emulation technologies. Competitive compensation package includes annual salary ranging from $142,000 to $203,000.
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$142k-203k yearly 3d ago
Senior FPGA Design Engineer
Advanced Micro Devices 4.9
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
The Role
This role is an exciting opportunity in SBIO team to create FPGA hardware validation platforms and debugging complex issues involving both hardware and software. Collaborate with design and firmware teams to define validation plans and execute on FPGA prototyping platforms. This role requires a proven track record of successfully bringing complex FPGA designs from concept through production quality, with strong debugging and problem-solving capabilities.
The Person
Strong analytical and problem solving skills with a pronounced attention to detail
Strong communication, mentoring and leadership skills
Self-driven, Methodical and attention to detail in troubleshooting and problem-solving
Can work well with cross functional teams
Excellent verbal and written communication skills
Responsibility
Design, develop, and implement complex FPGA architectures using Xilinx devices (UltraScale, UltraScale+, Versal, etc.)
Create RTL designs using Verilog/SystemVerilog for high-performance applications
Perform FPGA prototype design, implementation, and bring‑up activities
Create comprehensive design documentation, specifications, and technical reports
Perform timing analysis, closure, and optimization using Vivado tools
Conduct board-level bring‑up and system integration testing
Debug complex hardware/firmware issues using logic analyzers, oscilloscopes, and other test equipment
Validate FPGA designs against specifications and performance requirements
Independently troubleshoot and resolve challenging technical issues
Work closely with hardware, software, and systems engineering teams
Participate in design reviews and technical discussions
Communicate project status, risks, and technical challenges to stakeholders
Preferred Skill Set & Experience
Extensive experience in field of FPGA hardware prototyping
Have worked with prototyping platforms such as Xilinx reference boards, Synopsys HAPS platforms etc
Experience with Xilinx Versal ACAP or UltraScale+ devices
Knowledge of FPGA synthesis tools and methodologies
Familiarity with Python/TCL scripting for design automation
Knowledge of FPGA-based system architecture and hardware/software co‑design
Familiarity with board design and hardware debugging tools (logic analyzers, oscilloscopes, protocol analyzers)
Fluent in System Verilog and a familiarity with simulation and debug
Familiarity with industry standard high-speed protocols such as USB and PCIE is a plus
EDUCATION
BS (or higher) degree in Electrical or Computer Engineering desired
LOCATION
Santa Clara, CA
This role is not eligible for visa sponsorship.
#LI‑SC3
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
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$126k-160k yearly est. 2d ago
Senior FPGA Design & Validation Engineer
Advanced Micro Devices 4.9
Santa Clara, CA jobs
A leading semiconductor company in Santa Clara is looking for an FPGA Hardware Validation Engineer to create and implement validation platforms while collaborating with design and firmware teams. Candidates should have extensive experience in FPGA prototyping and strong problem-solving skills, along with a BS in Electrical or Computer Engineering. The role involves complex architecture designs and debugging hardware/firmware issues. Join a culture of innovation driven by collaboration and inclusivity.
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$126k-160k yearly est. 2d ago
Senior Electronics Engineer - Ground Systems Integration Lead
Northrop Grumman Corp. (JP 4.7
San Diego, CA jobs
A leading aerospace and defense company is looking for a SeniorPrincipal Electronics Engineer - Hardware and Software Integration Lead in San Diego. This role involves leading the development of next-generation ground system solutions, managing software supplier interactions, and coordinating various engineering efforts. Candidates should have a strong background in STEM, relevant work experience, and active security clearance. The position requires on-site work but could offer hybrid options in the future.
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$92k-121k yearly est. 4d ago
Senior Silicon Design Engineer
Advanced Micro Devices 4.9
San Jose, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
Together, we advance your career.
THE ROLE
We are seeking a Senior Member of Technical Staff (SMTS) SoC Architect to join our SoC Architecture team. In this role, you will define and drive architecture for critical SoC functions across roadmap and custom devices. You will focus on chip pervasive components, while ensuring seamless integration with processor subsystems, interconnect, AI accelerators, and memory systems.
THE PERSON
You are passionate about complex SoC architecture and thrive in cross-functional environments. You have deep technical expertise, strong analytical skills, and the ability to balance performance, power, and area trade-offs. You communicate effectively across teams and are comfortable influencing architecture decisions for next-generation silicon.
KEY RESPONSIBILITIES
Define and develop SoC architecture for CPF components, including Analog IPs, clocking/reset, and silicon monitors.
Collaborate with processor, interconnect, AI, and memory subsystem architects to ensure cohesive system-level design.
Specify architecture requirements, conduct early-stage analysis, and create detailed specifications.
Drive PPA optimization and ensure scalability across roadmap and custom devices.
Partner with design, verification, and physical implementation teams to ensure functional correctness and timing closure.
Analyze trade-offs for performance, power, reliability, and manufacturability.
Influence strategies for security, safety, and reliability across CPF domains.
Strong communication and leadership skills to influence cross-functional teams.
PREFERRED EXPERIENCE
Strong background in SoC architecture, including processor subsystems, interconnect, memory systems, and AI accelerators.
Expertise in Analog IPs (IOs, PLLs, eFuses, monitors), clocking/reset architecture, and silicon lifecycle management.
Familiarity with SoC on-chip protocols (e.g., AXI) and system-level QoS.
Experience with low-power design techniques, boot/reset flows, and power management.
Knowledge of design methodologies, advanced process technologies, and associated challenges.
Proficiency in modeling and automation using Python, SystemC, or similar languages.
ACADEMIC & EXPERIENCE REQUIREMENTS
BS or MS or PhD in Electrical/Computer Engineering or related field.
Proven track record in delivering architecture for high-performance, low-power SoCs.
LOCATION: San Jose, California
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
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$126k-160k yearly est. 6d ago
Senior Silicon Systems Engineer: Power & Performance
Nvidia Corporation 4.9
Santa Clara, CA jobs
A technology industry leader in California is seeking a Product Definition Engineer to evaluate and optimize pre-production silicon. The successful candidate will work with multi-functional teams, driving new feature initiatives and designing performance-critical product features. Ideal candidates will have significant engineering experience and collaborative skills. The role offers a salary range of 168,000 - 264,500 USD depending on level, alongside equity and benefits.
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$141k-181k yearly est. 2d ago
Senior PCIe Engineer (Gen4/5/6)
Micron Technology, Inc. 4.3
San Jose, CA jobs
A leading global semiconductor company in San Jose is seeking a Senior Electrical PCIe Engineer to craft and verify next-generation PCIe components. The ideal candidate will have a BS or MS in Electrical Engineering, expertise in PCIe protocols, and at least 5 years of experience in related roles. You will develop firmware, define device behavior, and collaborate with teams to ensure high-performance PCIe subsystems. This position offers competitive pay and rich benefits.
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