Senior Verification Engineer jobs at Intel - 191 jobs

A leading technology firm in San Jose is seeking a Design Verification Engineer to develop advanced verification environments and methodologies. The role demands 12+ years of experience in ASIC verification, strong knowledge of System Verilog, and excellent communication skills. You will collaborate with design and verification teams to meet high-performance design requirements and analyze complex verification challenges. The company offers a competitive salary and comprehensive benefits package. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD/Xilinx programmable devices. THE PERSON: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware and firmware engineers to understand the new features to be verified Take ownership of block level verification tasks Define test plans, test benches, and tests using System Verilog and UVM Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes Review functional and code coverage metrics to meet the coverage requirements Develop and improve existing verification flows and environments PREFERRED EXPERIENCE: Strong understanding of computer architecture and logic design Knowledge of Verilog, system Verilog and UVM is a must Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification Working knowledge of C/C++ and Assembly programming languages Exposure to scripting (python preferred) for post-processing and automation Experience with gate level simulation, power and reset verification ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE Adaptive and Embedded Computing Group (AECG) seeks a Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high‑speed Crypto, Network‑on‑Chip (NoC), and cutting‑edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal‑based verification environments at both block and SoC‑level to achieve first‑pass silicon success. THE PERSON The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre‑Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities Lead the verification of high‑speed Crypto, Network‑on‑Chip (NoC), cutting‑edge DRAM Memory controller (LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal‑based verification environments at IP and SoC‑level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion‑based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. Preferred Experience Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Strong understanding of state of the art of verification techniques, including assertion and metric‑driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high‑performance IP and/or VLSI designs is a plus. Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate‑level simulation, power‑aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. Academic Credentials BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. #LI-CJ2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Senior Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network‑on‑Chip (NoC), and cutting‑edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal‑based verification environments at both block and SoC‑level to achieve first‑pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre‑Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities: Lead the verification of high‑speed Crypto, Network‑on‑Chip (NoC), cutting‑edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal‑based verification environments at IP and SoC‑level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion‑based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. Proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analysed and verified system‑level Performance and QoS (Quality of Service) requirements. Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including assertion and coverage‑driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high‑performance IP and/or VLSI designs is a plus. Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate‑level simulation, power‑aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. ACADEMIC CREDENTIALS: BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

A leading technology company is seeking recent graduates for an ASIC engineering role in San Francisco. You'll be part of a dynamic team, collaborating with experts in the field to develop innovative communications and network processing solutions. Candidates should have a Bachelor's degree or be nearing completion, familiar with hardware description languages, and understand ASIC design flow. Join a company that is shaping the future of technology. #J-18808-Ljbffr

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. Meet the Team The ASIC Group works closely with other development teams within Cisco, including marketing, system hardware, software, product engineering, and manufacturing. Through this collaboration, members of our group play a major role in defining, developing and bringing new products to market across Cisco's product line. Open-minded, driven, diverse and deeply creative people at Cisco craft the hardware that makes the internet work. Bring your knowledge of computers and networking and take it to a new level in any one of the following product categories including: cloud, social, mobile/wireless, video, VoIP, collaboration, web, Internet of Things, routing, switching, IPv6, data center, HPC, TelePresence and many more. Your work will affect billions globally. Your Impact Join our award-winning ASIC team, where you'll collaborate with top industry talent to design and deliver ground breaking communications and network processing silicon. You'll contribute to system and processor architecture, high-speed logic design and verification, digital signal processing, memory and custom library development, physical design, DFT, signal integrity, and advanced packaging. Work with the latest VLSI techniques and deep submicron technologies, owning projects from concept to in‑house physical implementation. Minimum Qualifications Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelor's degree program. Familiarity with hardware description languages (HDLs), such as Verilog or VHDL. Experience with RTL design and simulation tools (e.g., Synopsys, Cadence, Mentor Graphics). Exposure to scripting languages (e.g., Python, Perl, TCL) for automation. Familiarity with ASIC/SoC design flow including synthesis, place & route, and timing closure. Preferred Qualifications Experience with ASIC verification methodologies (e.g., UVM, SystemVerilog) Understanding of physical design and DFT (Design for Test) principles Familiarity with Linux-based development environments Ability to adapt to new technologies and problem‑solve sophisticated engineering challenges Excellent organizational, teamwork, and communication skills Why Cisco At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada Individual pay is determined by the candidate's hiring location, market conditions, job‑related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non‑exempt employees 1 paid day off for employee's birthday, paid year‑end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non‑exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full‑time employees Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non‑sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance‑based incentive pay on top of their base salary, which is split between quota and non‑quota components, subject to the applicable Cisco plan. For quota‑based incentive pay, Cisco typically pays as follows: 0.75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non‑quota‑based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $94,200.00 - $137,500.00 Non‑Metro New York state & Washington state: $84,000.00 - $122,200.00 For quota‑based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Employees in Illinois, whether exempt or non‑exempt, will participate in a unique time off program to meet local requirements. Cisco is an affirmative action and equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records. #J-18808-Ljbffr

A leading semiconductor company in California is seeking a Design Verification Engineer to join a high-performance design team. The role involves developing verification environments, designing verification components, and analyzing simulation failures. Candidates should have over 12 years of experience and a Bachelor's degree in a relevant field. Strong knowledge of System Verilog and UVM is required. Competitive salary and benefits offered. #J-18808-Ljbffr

A leading tech company in Silicon Valley seeks a Staff Silicon Design Verification Engineer. In this role, you will lead verification efforts for advanced designs including high-speed Crypto and DRAM Controllers, utilizing cutting-edge technologies. Ideal candidates will have strong leadership skills, a background in verification methodologies, and experience with UVM and simulation tools. This position offers opportunities for professional growth and impacts the future of computing, aiming for first-pass silicon success. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Together, we advance your career. SMTS SoC Architect THE ROLE We are seeking a SoC Architect to join our adaptive SoC Architecture team. This role is pivotal in defining and driving architecture for next‑generation Adaptive SoCs, with Processor subsystems, Interconnect, AI, GPU, video processing pipelines, and memory systems. THE PERSON You are a seasoned SoC architect with deep expertise in heterogeneous compute systems. You thrive in collaborative environments and bring a system‑level mindset to solving architectural challenges. You are passionate about performance, power, and scalability, and have a strong grasp of silicon design trade‑offs. You communicate effectively across engineering disciplines and influence architectural decisions with clarity and technical rigor. KEY RESPONSIBILITIES Drive architecture of key IPs including their PPA tradeoffs, Interconnect, and integration into SoC Define and optimize SoC control bus protocols, reset flows, clocking strategies, and power domains. Drive early‑stage architectural analysis, modeling, and specification development. Contribute to architectural innovation for Adaptive SoC Use‑cases in AI, GPU, video, and IO domains. Collaborate with planning, software and hardware cross‑functional teams to develop architecture solution. Collaborate with subsystem architects to ensure cohesive integration and system‑level performance. PREFERRED EXPERIENCE Proven experience in SoC architecture with Processor, Interconnects, and Memory subsystem. Expertise in AI accelerators, GPU integration, video processing pipelines, and IO subsystems. Expertise in SoC control bus design, reset architecture, clocking, and power management techniques. Experience with modeling and automation using Python, SystemC, or equivalent. Knowledge of advanced process technologies and associated design challenges. ACADEMIC & EXPERIENCE REQUIREMENTS BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field. Demonstrated success in delivering high‑performance, low‑power SoC solutions. Benefits offered are described: AMD benefits at a glance. Equal Opportunity Employment AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for a self‑motivated senior design engineer to be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry‑leading technologies to market. As a key contributor, you will focus on RTL design and validation of high‑speed interfaces such as chip‑to‑chip interconnect, both on system and on package, and highly configurable multi‑protocol PHYs. Continuous technical innovation to increase productivity, to heighten quality of results, and to foster career development is integral to the role. THE PERSON: You have a passion for digital design. You are a team player. You have strong analytical and problem‑solving skills. You are willing to learn and ready to take ownership of problems. KEY RESPONSIBILITIES: Perform RTL design of the digital components. Develop and validate timing constraints involving multiple clock domains while working with physical design to harden IP. Help lead and mentor other engineers to achieve project goals and organizational growth. Work with a functional (design) verification team to meet coverage and quality standards. Analyze/fix lint and CDC/RDC errors of the components. Guarantee quality/timely deliverables meeting project's schedule. Help to improve and automate design process. Support post‑silicon product bring‑up/debug. PREFERRED EXPERIENCE: Strong experience in designing digital components for high performance, low power SOC/FPGA. Design of digital circuits and components using Verilog/System Verilog. Creating and maintaining of timing constraints for complex multi‑clock designs. Debugging in digital and mixed‑signal simulation environment. Power optimization of digital designs. Multi‑clock domain designs. Experience/knowledge of high‑speed SerDes/Physical layer is a plus. Logic synthesis, timing closure, logical equivalence checking and ECOs. Scripting languages such as Perl, Tcl, or Python. Collaboration with verification team. Excellent verbal and interpersonal communication skills. Excellent technical communications. Ability to produce technical documentation. Exhibit strong ownership of tasks and responsibilities. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering with relevant industry experience. LOCATION: San Jose, California Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A technology industry leader in California is seeking a Product Definition Engineer to evaluate and optimize pre-production silicon. The successful candidate will work with multi-functional teams, driving new feature initiatives and designing performance-critical product features. Ideal candidates will have significant engineering experience and collaborative skills. The role offers a salary range of 168,000 - 264,500 USD depending on level, alongside equity and benefits. #J-18808-Ljbffr

A leading aerospace company is looking for a Senior Principal Engineer Software in San Diego, CA, to design and develop embedded software systems. Candidates should have a strong background in C/C++ and Python, with at least 8 years of relevant experience. This position requires collaboration in an Agile environment and an active Secret DoD Security Clearance. The salary range is $118,600 - $178,000, plus bonuses and benefits. #J-18808-Ljbffr

A leading aerospace and defense company in California is seeking a Senior Principal Embedded & Real Time Software Engineer. This role involves designing, developing, and testing software for critical systems, working in an Agile environment. Candidates should possess a Bachelor's degree in a STEM field with extensive experience in software development, particularly in C, C++, and Python. A Top Secret clearance is required. The position offers a competitive salary and opportunities for career advancement. #J-18808-Ljbffr

A leading aerospace and defense company in California is seeking a Senior Principal Embedded & Real Time Software Engineer. This role involves designing, developing, and testing software systems in a collaborative Agile environment. Candidates should have 8 years of experience in engineering, familiarity with programming languages like C and C++, and demonstrate capability in real-time applications. A Top Secret clearance is required, and the position offers competitive salary and relocation assistance. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. You will participate in design verification methodology definition as well as contribute to design verification infrastructure that facilitates maximum re-use of components, improves productivity, and guarantees to the maximum extent possible, bug-free designs. THE PERSON: You have a passion for digital design and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems KEY RESPONSIBILITIES: * Collaborate with architects, hardware and firmware engineers to understand the features to be verified * Take ownership of different verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL simulations and work with HW and FW development teams to verify fixes * Review functional and code coverage metrics to meet the coverage requirements * Develop and improve existing verification flows and environments * Provide technical support to other teams PREFERRED EXPERIENCE: * Proficient in IP level ASIC verification * Experience identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills * Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE) * Working knowledge of Formal Verification methods and apps ( FPV, CC, Sequence equivalence, etc.) * Proficient in debugging firmware and RTL code using simulation tools * Proficient in using UVM testbenches and working in Linux and Windows environments * Experienced with Verilog, System Verilog, C, and C++ * Developing UVM based verification frameworks and testbenches, processes and flows * Automating workflows in a distributed compute environment. * Good understanding and hands-on experience in the UVM concepts and SystemVerilog language * Good to have : prior experience with USB / PCIE / UFS Controllers. ACADEMIC CREDENTIALS: * Bachelors or Masters degree in Computer Engineering/Electrical Engineering LOCATION: Santa Clara, Folsom, CA #LI-TB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Senior Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network-on-Chip (NoC), and cutting-edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities: * Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance. * Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level. * Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. * Develop and execute comprehensive verification plans, including testbenches and test cases. * Collaborate with design, architecture, and software teams to define and implement verification strategies. * Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification. * Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: * Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. * Proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analyzed and verified system-level Performance and QoS (Quality of Service) requirements. * Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. * Require strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus. * Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. * Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. * Experience with gate-level simulation, power-aware verification is a plus. * Experience with silicon debug at the tester and board level, is a plus. ACADEMIC CREDENTIALS: * BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. #LI-CJ2 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network-on-Chip (NoC), and cutting-edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities: * Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance. * Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level. * Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. * Develop and execute comprehensive verification plans, including testbenches and test cases. * Collaborate with design, architecture, and software teams to define and implement verification strategies. * Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification. * Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: * Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. * Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. * Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus. * Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. * Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. * Experience with gate-level simulation, power-aware verification is a plus. * Experience with silicon debug at the tester and board level, is a plus. ACADEMIC CREDENTIALS: * BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. #LI-CJ2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an adaptive, self-motivative Design Verification (DV) engineer to join our growing PLL team. As a key contributor, you will be part of a leading team that drives and improves AMD's ability to deliver the highest quality, industry-leading technologies to the market. The Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: * The successful candidate will possess: * Excellent analytical and critical thinking skills along with attention to details * Must be an initiative-taker, able to drive tasks independently and efficiently to completion * Strong/effective communication skills * Enthusiastic team-first mentality * Ability to provide mentorship and guidance to junior engineers * Relevant academic background (M.Sc. degree preferred) and at least 8 years of progressive experience KEY RESPONSIBILITIES: * Analyze complex verification and digital design problems and propose verification / micro-architecture solutions * Develop RTL and Firmware validation. * Drive/develop ASIC verification flows and scripts. * Create Verification architecture. * Work with the RTL Design team to ensure functional correctness and coverage. * Support silicon bring-up and diagnostics. * Support Post-silicon debug, root cause bug, provide solution or workaround. PREFERRED EXPERIENCE: * Proven experience in design verification from specification to successful silicon. * Experience in PLL, high-speed interfaces such as DDR, PCIe and high-speed SERDES. * Experience in designs with multiple power domains. * Experience in designs with multiple clock domains. * Experience in behavior modeling for Analog Circuits. * Experience in industry-standard ASIC CAD tools for verification, simulation, synthesis, STA, CDC, UPF, power estimation, etc. ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: * Folsom, CA This role is not eligible for visa sponsorship. #LI-SL3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

We are seeking a highly accomplished **Silicon Design Verification Architect** to define, architect, and deliver end‑to‑end verification strategies for complex IPs, subsystems, and SoCs. In this role, you will lead the development of scalable, reusable verification infrastructures and methodologies, drive functional and security coverage closure, and ensure first‑pass silicon success across pre‑ and post‑silicon validation. This is a hands‑on technical leadership role requiring deep expertise in UVM‑based simulation, formal and multimodal verification, and verification infrastructure architecture, as well as close collaboration with design, architecture, software, and post‑silicon teams. **Key Responsibilities** + Define and own the verification architecture and strategy for IPs, subsystems, and full SoCs, ensuring optimal tradeoffs between completeness, performance, reuse, and scalability. + Architect, implement, and maintain advanced UVM and formal‑based verification environments, including configurable, reusable testbenches and verification components. + Design and integrate block‑level testbenches into chip‑level UVM environments, executing and validating complex IP and SoC integrations. + Develop comprehensive test strategies, testbench architectures, and verification plans aligned with design specifications, coverage goals, and silicon milestones. + Lead random and constrained‑random test generation, functional simulation, and regression strategies to uncover design gaps and corner‑case defects. + Drive coverage analysis, failure root‑cause analysis, and coverage closure, ensuring measurable verification completeness and signoff readiness. + Develop and execute low‑power and security validation strategies, including definition of security coverage models and deployment of security‑focused verification infrastructure. + Collaborate closely with design, architecture, analog, software, and post‑silicon teams to align verification intent across the full product lifecycle. + Support post‑silicon validation and debug, leveraging pre‑silicon environments and collateral to accelerate issue isolation and resolution. + Mentor and influence verification engineers across teams through best practices, design reviews, and technical leadership. Additional Skills + Excellent communication, technical writing, and organizational skills, with a strong record of cross‑functional collaboration. **Qualifications:** **Minimum Qualifications** + BS or MS in Electrical Engineering, Computer Science, or a related field, with 10+ years of industry experience in silicon design verification. + 8+ years of experience across IP‑level, subsystem‑level, and SoC‑level verification, with demonstrated ownership of complex verification architectures. + Strong expertise in simulation‑based verification methodologies, including UVM, assertion‑based verification, co‑simulation, and low‑power verification. + Advanced coding skills in SystemVerilog/UVM. **Preferred Qualifications** + Proven hands‑on experience developing highly configurable and reusable Verification IP (VIP) such as AMBA, PCIe, HBM, LPDDR, or similar complex protocols. + Advanced coding skills in SystemVerilog/UVM, C/C++, Python, and scripting/build systems such as Make, CMake, or Bazel. + Demonstrated history of delivering robust, scalable verification tools and infrastructure that enable high‑quality, on‑time silicon. **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, California, Santa Clara **Additional Locations:** **Business group:** Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.