Requirements Engineer jobs at JLL - 9898 jobs

San Francisco Bay Area, California, United States Hardware The Wireless SoC Radio Team designs state‑of‑art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed‑signal blocks from RF front‑end amplifiers to data converters, including baseband filters, baseband and RF phase‑locked loops, crystal oscillators, and bandgap references. Description As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next‑generation of wireless technologies into high‑volume production in advanced CMOS technology nodes. Responsibilities Detailed transistor‑level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking. Co‑work with designers on block level floorplanning. Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling. Minimum Qualifications BS and 3+ years of relevant industry experience. Preferred Qualifications Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub‑micron CMOS. Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. Solid understanding of RC delay, electromigration, and coupling. Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE. High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology. Knowledge of CADENCE layout tools. Scripting skills in PERL or SKILL. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $141,800 and $258,600, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr

San Francisco Bay Area, California, United States Software and Services Join our Headphone & Accessories team and drive innovation in the wireless audio experience space. We craft and seamlessly integrate technologies that enrich people's lives and deliver the best user-experience. Are you a dedicated software engineer ready to design, develop and build the next generation of wireless audio experience and personal device connectivity? If you're a strong software engineer and are passionate about building incredible Bluetooth solutions, we may have the job for you! Description Your main responsibility in this role will be to design and create user interfaces for various audio features and functionality on iOS and mac OS. The role will include working with design and engineering teams to prototype design options and creating final interfaces on devices. Responsibilities Main responsibility in this role will be to design and create user interfaces for accessories related to enrollment, HW specific functionality, audio features and functionality on iOS and mac OS. The role will include working with design and engineering teams to prototype design options and creating final interfaces on devices. Minimum Qualifications You have a MS/BS in Computer Science / relevant with 4+ years experience. You have strong development and coding skills. You have some background in developing UI. You have a wealth of experience in software development & you're driven to learn! You have experience developing and delivering multi-mode communications that convey a clear understanding of the unique needs of different audiences. Preferred Qualifications You thrive in a collaborative environment and can clearly communicate while driving multiple projects across teams. You enjoy taking on new opportunities and tough challenges with a sense of urgency, high energy, and enthusiasm. You build partnerships and work collaboratively with others to meet shared objectives. You consistently achieve results, even under tough circumstances. You handle conflict situations effectively, with a minimum of noise. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $126,800 and $220,900, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr

A leading technology company in Sunnyvale, California, is seeking a Machine Learning Engineer to design and implement cutting-edge conversational and generative AI systems. This role combines machine learning research and product engineering, requiring strong expertise in deep learning, natural language processing, and Python programming. Candidates should have relevant advanced degrees and hands-on experience with ML frameworks. Apple offers competitive compensation and a robust set of benefits including health coverage and stock options. #J-18808-Ljbffr

Amazon Leo is Amazon's low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity. Export Control Requirement Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Role Overview This position is part of the Satellite Attitude Determination and Control team. You will design and analyze the control system and algorithms, support development of flight hardware and software, help integrate the satellite in labs, participate in flight operations, and observe a constellation of satellites flow through the production line in the building next door. Key Responsibilities Design and analyze algorithms for estimation, flight control, and precise pointing using linear methods and simulation. Develop and apply models and simulations of the satellite and our constellation with various levels of fidelity. Perform component level environmental testing, functional and performance checkout, subsystem integration, satellite integration, and in‑space operations. Manage the spacecraft constellation as it grows and evolves. Continuously improve our ability to serve customers by maximizing payload operations time. Develop autonomy for Fault Detection and Isolation on board the spacecraft. A Day in the Life This is an opportunity to play a significant role in the design of an entirely new satellite system with challenging performance requirements. The large, integrated constellation brings opportunities for advanced capabilities that need investigation and development. The constellation size also puts emphasis on engineering excellence so our tools and methods, from conceptualization through manufacturing and all phases of test, will be state of the art as will the satellite and supporting infrastructure on the ground. You will find that Amazon Leo's mission is compelling, so our program is staffed with some of the top engineers in the industry. Our daily collaboration with other teams on the program brings constant opportunity for discovery, learning, and growth. About the Team Our team has lots of experience with various satellite systems and many other flight vehicles. We have bench strength in both our mission and core GNC disciplines. We design, prototype, test, iterate and learn together. Because GNC is central to safe flight, we tend to drive Concepts of Operation and many system level analyses. Basic Qualifications PhD, or Master's degree and 4+ years of quantitative field research experience. Experience investigating the feasibility of applying scientific principles and concepts to business problems and products. Experience analyzing both experimental and observational data sets. Preferred Qualifications Knowledge of R, MATLAB, Python or similar scripting language. Experience with agile development. Experience building web‑based dashboards using common frameworks. Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit ********************************************************* for more information. If the country/region you're applying in isn't listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign‑on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at ******************************** USA, WA, Redmond - 136,000. - 184,000.00 USD annually. #J-18808-Ljbffr

A global technology company in Seattle is seeking a skilled software engineer for the Machine Learning Applications team of AWS Neuron. The role requires expertise in developing and tuning performance for ML models, working collaboratively in a fast-paced environment. Ideal candidates will have over 3 years of software development experience and a strong background in programming languages. Competitive compensation includes medical benefits, equity, and a supportive culture aimed at career growth. #J-18808-Ljbffr

**Role Number:** 200628172-0240 At Apple, we work every single day to craft products that enrich people's lives. In this highly visible role, you will take ownership of the ESD and Latch-Up requirements of all ICs developed by and for Apple. Your mission is to ensure the silicon is designed to meet Apple's ESD specifications and manufacturing requirements. The role involves working closely with our diverse teams within Apple as well as external vendors. Occasional travel might be required. Do you love working on challenges that no one has solved yet? Are you excited to build Apple's products that strive for the highest expectations of quality, innovation and efficiency? We have an opportunity for an especially innovative ESD Designer with strong fundamentals! We are looking forward to having you join our fast growing team and help us deliver on these challenges while enjoying an amazing culture where you lead your career! **Description** Work in a cross-functional team that delivers high quality on-chip IPs immune to ESD/EOS and latchup events. Ensure ESD robust designs with minimum cost to mission-mode functions. **Minimum Qualifications** + BS and 10+ years of relevant industry experience **Preferred Qualifications** + MS and 8+ years relevant industry experience. + Deep understanding of transistor device characteristics. + Solid understanding of models used for testing ESD, including HBM, CDM, MM and IEC-61000-4-2. + Knowledge of state-of-the-art ESD circuit design techniques and topologies. + Hands-on experience with design/layout EDA tools, including Virtuoso, Calibre, Allegro, etc. + Knowledge of ESD checking tools like PERC and Pathfinder. + Experience with Si processes used for high voltage, RF, or advanced ASICs. + Experience with ESD/LUP test and characterization equipment. + Strong initiative, collaboration, and ownership of responsibilities, productive, able to meet challenging deadlines. + Excellent written and verbal communication skills. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

**Role Number:** 200*********** Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables. **Description** As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC Timing: Full chip and block level timing closure/constraints ownership throughout the entire project. You will be working with other specialists that are members of the SoC Design, SoC Design Verification, DFT, Architecture and Physical Design teams. Working with CAD and Flow teams to define and improve front-end design methodologies. Develop and maintain methodology and flows related to timing analysis. **Minimum Qualifications** + Bachelors Degree + 0 Years of Experience. **Preferred Qualifications** + Strong fundamentals in the area of Digital design + Familiarity with ASIC design timing concepts + Proficient in scripting languages (TCL, Python and Perl) + Exposure to STA tools (Primetime) , writing timing constraints and knowledge of timing corners / modes is a plus + Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks + Self-starter and highly motivated + Ability to communicate optimally across all internal groups Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

Are you passionate about advancing the boundaries of RF analog circuit integration in advanced technology nodes for wireless transceivers? Do you thrive on innovation and improving RF layout methodologies? As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous iterations and enrich user experiences worldwide. You will lay out detailed custom blocks, including floorplanning, placement, routing, and verification for high-frequency RF circuits, verifying and refining layouts through simulation to meet design requirements. You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design concepts, constraints, and opportunities for improvement. Upon identifying challenges, you will propose solutions to streamline layout tasks, collaborating with teams to specify and finalize methodologies. Experience in sophisticated DRC, ERC, LVS verification, and debugging. Prior experience in crafting custom layouts at the chip, block, and device levels, particularly for RF high-frequency circuits such as LNAs, mixers, VCOs, and PLLs is a plus. RF experience is helpful. BS with 3+ years of industry experience. Deep knowledge of sub-micron CMOS technologies (16nm, 7nm, and beyond) and proficiency with FinFET structures, guard-rings, deep N-wells, and PN junctions are required. Familiarity with sophisticated process effects such as LOD, WPE, and DFM is critical. Understanding trade-offs involving matching, parasitic effects, high-frequency routing, isolation, coupling, shielding, RC delay, EM, IR, ESD, and latch-up is vital.

Are you passionate about advancing the boundaries of RF analog circuit integration in advanced technology nodes for wireless transceivers? Do you thrive on innovation and improving RF layout methodologies? As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous iterations and enrich user experiences worldwide.You will lay out detailed custom blocks, including floorplanning, placement, routing, and verification for high-frequency RF circuits, verifying and refining layouts through simulation to meet design requirements. You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design concepts, constraints, and opportunities for improvement. Upon identifying challenges, you will propose solutions to streamline layout tasks, collaborating with teams to specify and finalize methodologies.Experience in sophisticated DRC, ERC, LVS verification, and debugging. Prior experience in crafting custom layouts at the chip, block, and device levels, particularly for RF high-frequency circuits such as LNAs, mixers, VCOs, and PLLs is a plus. RF experience is helpful.Array

**Role Number:** 200*********** The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references. We are working on new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. **Description** As an RFIC Layout Designer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. In this role, you will work closely with the RFIC design team to layout and verify custom RF and analog IP for complex SoC products. You will have a critical impact on developing Apple's state-of-the-art radios and getting them into hundreds of millions of products. **Minimum Qualifications** + 5+ year minimum related experience required. + Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS. + High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology. + Knowledge of Cadence layout tools. **Preferred Qualifications** + Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. + Solid understanding of RC delay, electromigration, and coupling. + Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE. + Excellent communication skills and able to work with cross-functional teams. + Scripting skills in PERL or SKILL. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

**Role Number:** 200*********** The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and band gap references. **Description** As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. **Minimum Qualifications** + BS and 10+ years of relevant industry experience. + FinFet experience. **Preferred Qualifications** + Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS. + Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. + Solid understanding of RC delay, electromigration, and coupling. + Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE. + High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology. + Knowledge of CADENCE layout tools. + Excellent communication skills. + Scripting skills in PERL or SKILL. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables. As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC Timing: Full chip and block level timing closure/constraints ownership throughout the entire project. You will be working with other specialists that are members of the SoC Design, SoC Design Verification, DFT, Architecture and Physical Design teams. Working with CAD and Flow teams to define and improve front-end design methodologies. Develop and maintain methodology and flows related to timing analysis. Strong fundamentals in the area of Digital design Familiarity with ASIC design timing concepts Proficient in scripting languages (TCL, Python and Perl) Exposure to STA tools (Primetime) , writing timing constraints and knowledge of timing corners / modes is a plus Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks Self-starter and highly motivated Ability to communicate optimally across all internal groups Bachelors Degree + 0 Years of Experience.

**Role Number:** 200*********** Are you passionate about advancing the boundaries of RF analog circuit integration in advanced technology nodes for wireless transceivers? Do you thrive on innovation and improving RF layout methodologies? As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous iterations and enrich user experiences worldwide. **Description** You will lay out detailed custom blocks, including floorplanning, placement, routing, and verification for high-frequency RF circuits, verifying and refining layouts through simulation to meet design requirements. You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design concepts, constraints, and opportunities for improvement. Upon identifying challenges, you will propose solutions to streamline layout tasks, collaborating with teams to specify and finalize methodologies. **Minimum Qualifications** + BS with 3+ years of industry experience. + Deep knowledge of sub-micron CMOS technologies (16nm, 7nm, and beyond) and proficiency with FinFET structures, guard-rings, deep N-wells, and PN junctions are required. + Familiarity with sophisticated process effects such as LOD, WPE, and DFM is critical. + Understanding trade-offs involving matching, parasitic effects, high-frequency routing, isolation, coupling, shielding, RC delay, EM, IR, ESD, and latch-up is vital. **Preferred Qualifications** + Experience in sophisticated DRC, ERC, LVS verification, and debugging. + Prior experience in crafting custom layouts at the chip, block, and device levels, particularly for RF high-frequency circuits such as LNAs, mixers, VCOs, and PLLs is a plus. + RF experience is helpful. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

**Role Number:** 200*********** The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references. **Description** As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. **Minimum Qualifications** + BS and 3+ years of relevant industry experience. + FinFet experience. **Preferred Qualifications** + Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS. + Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. + Solid understanding of RC delay, electromigration, and coupling. + Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE. + High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology. + Knowledge of CADENCE layout tools. + Excellent communication skills. + Scripting skills in PERL or SKILL. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

**Role Number:** 200*********** Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables. **Description** As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications. Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs. **Minimum Qualifications** + Bachelors Degree + 10 Years of Experience **Preferred Qualifications** + Strong fundamentals in the area of Digital design + Self-starter and highly motivated + Proficient in scripting languages (TCL and Perl) + Familiarity with ASIC design timing concepts + Exposure in STA tools (Primetime) is a plus + Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks + Familiarity in Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer) is desirable but not required + Knowledge of timing corners/modes, process variations and signal integrity related issues is a plus + Ability to commnicate optimally across all internal groups Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

A leading tech company is seeking a Business Intel Engineer III located in San Francisco, CA. The role involves managing metrics reporting, performing statistical modeling, and developing forecasting technologies. Candidates must have a Master's degree in a related field or equivalent experience, along with skills in SQL, ETL, and statistical analysis. This position offers a salary range of $159,099 to $176,300 annually, along with a comprehensive compensation package including benefits and equity incentives. #J-18808-Ljbffr

Union Relief Engineer-TemporaryJob ID257569Posted23-Jan-2026Service line GWS SegmentRole type Full-time Areas of InterestEngineering/MaintenanceLocation(s) San Francisco - California - United States of AmericaGlobal Workplace Solutions (GWS) Local is a hard services-led, tailored facility management solution. We self-perform hard services while partnering with best-in-class soft service providers to offer custom facility and project management solutions to our clients. We focus on empowering our team with a high-level of downstream accountability, resulting in an agile and efficient service delivery.In addition to our core facility and project management capabilities, our platform offers direct access to our Best-in-Class services including ESG, Security Consulting, Workplace Strategy, and Workplace Experience.As a CBRE Union Relief Engineer, you will be responsible for the operation and maintenance of mechanical, electrical, and plumbing equipment and systems for assigned properties.This job is part of the Engineering and Technical Services job function. They are responsible for providing support, preventive maintenance, and repairs on equipment and systems.What You'll Do:• Maintain and fix building heating equipment.• Repair plumbing fixtures. This includes water closets, urinals, flush valve assemblies, etc.• Perform preventive maintenance duties including changing filters, cleaning coils, flushing condensers, etc.• Inspect engine and fan room equipment, cooling towers, motors, house pumps, etc.• Perform fire and life safety inspections as per company and local requirements.• Respond immediately to emergency situations and customer concerns.• Apply in-depth knowledge of standard principles and techniques/procedures to accomplish complex assignments and provide innovative solutions.• Coach others and share in-depth knowledge of own job discipline and broad knowledge of several job disciplines within the function.• Lead by example and model behaviors that are consistent with CBRE RISE values. Work to build consensus and convince others to reach an agreement.• Impact a range of customer, operational, project, or service activities within own team and other related teams.• Work within broad guidelines and policies.• Explain difficult or sensitive information.What You'll Need:• High School Diploma, GED, or trade school diploma with 4-5 years of job-related experience. In lieu of a diploma, a combination of experience and education will be considered.• Prior shift leader or supervisory experience preferred.• Meet the physical requirements of this role including stooping, standing, walking, climbing stairs/ladders, and the ability to lift/carry heavy loads of 50 lbs. or more.• Ability to exercise judgment based on the evaluation of multiple sources of information.• Willingness to take a new perspective on existing solutions.• In-depth knowledge of Microsoft Office products. Examples include Word, Excel, and Outlook.• Organizational skills with an advanced inquisitive mindset Applicants must be currently authorized to work in the United States without the need for visa sponsorship now or in the future Why CBREWhen you join CBRE, you become part of the global leader in commercial real estate services and investment that helps businesses and people thrive. We are dynamic problem solvers and forward-thinking professionals who create significant impact. Our collaborative culture is built on our shared values - respect, integrity, service and excellence - and we value the diverse perspectives, backgrounds and skillsets of our people. At CBRE, you have the opportunity to chart your own course and realize your potential. We welcome all applicants.Applicant AI Use DisclosureWe value human interaction to understand each candidate's unique experience, skills and aspirations. We do not use artificial intelligence (AI) tools to make hiring decisions, and we ask that candidates disclose any use of AI in the application and interview process.These updates reflect our commitment to clarity, inclusivity, and a consistent candidate experience across all postings. I ask you to encourage your teams to begin incorporating the updated statements into all new job adverts immediately - this will help us maintain alignment with our brand tone and hiring values The pay range for this position is subject to an applicable Collective Bargaining Agreement. The negotiated rate for the Union Relief Engineer position is $76.93 per hour. Please refer to the Collective Bargaining Agreement regarding pay scale.**Equal Employment Opportunity:** CBRE has a long-standing commitment to providing equal employment opportunity to all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, pregnancy, age, citizenship, marital status, disability, veteran status, political belief, or any other basis protected by applicable law. **Candidate Accommodations:** CBRE values the differences of all current and prospective employees and recognizes how every employee contributes to our company's success. CBRE provides reasonable accommodations in job application procedures for individuals with disabilities. If you require assistance due to a disability in the application or recruitment process, please submit a request via email at recruitingaccommodations@cbre.com or via telephone at *************** (U.S.) and *************** (Canada).CBRE GWSCBRE Global Workplace Solutions (GWS) works with clients to make real estate a meaningful contributor to organizational productivity and performance. Our account management model is at the heart of our client-centric approach to delivering integrated real estate solutions. Each client is entrusted with a dedicated leader and is supported by regional and global resources, leveraging the industry's most robust platform. CBRE GWS delivers consistent, measurably superior outcomes for our clients at every stage of the lifecycle, and across industries and geographies.* Share Union Relief Engineer-Temporary with a friend via e-mail #J-18808-Ljbffr

At Capital One, we are creating responsible and reliable AI systems, changing banking for good. For years, Capital One has been an industry leader in using machine learning to create real-time, personalized customer experiences. Our investments in technology infrastructure and world-class talent - along with our deep experience in machine learning - position us to be at the forefront of enterprises leveraging AI. From informing customers about unusual charges to answering their questions in real time, our applications of AI & ML are bringing humanity and simplicity to banking. We are committed to continuing to build world-class applied science and engineering teams to deliver our industry leading capabilities with breakthrough product experiences and scalable, high‑performance AI infrastructure. At Capital One, you will help bring the transformative power of emerging AI capabilities to reimagine how we serve our customers and businesses who have come to love the products and services we build. Team Description The Intelligent Foundations and Experiences (IFX) team is at the center of bringing our vision for AI at Capital One to life. We work hand‑in‑hand with our partners across the company to advance the state of the art in science and AI engineering, and we build and deploy proprietary solutions that are central to our business and deliver value to millions of customers. Our AI models and platforms empower teams across Capital One to enhance their products with the transformative power of AI, in responsible and scalable ways for the highest leverage impact. Why this Role Matters We are building an enterprise Generative AI Platform that lets dozens of product teams compose powerful, safe and explainable AI capabilities - without wrestling with model minutiae or infra plumbing. You will design the agentic workflow framework, shared services such as memory, guardrails, vector search, SDKs and blueprints that translate foundation model power into production‑grade applications used by millions of users across multiple lines of businesses. In this role, you will Partner with a cross‑functional team of engineers, research scientists, technical program managers, and product managers to deliver AI‑powered products that change how our associates work and how our customers interact with Capital One. You will contribute to the north star platform architecture, continuously publishing and refining living diagrams and canonical APIs that cover agent orchestration, RAG pipelines, prompt libraries and multi‑tenant policy enforcement. A major emphasis is around standardizing and automating agentic workflows: you will evaluate agentic frameworks such as LangGraph, AutoGen, Semantic Kernel, CrewAI and LlamaIndex and then harden/blend patterns that best meet enterprise SLAs so that 90% of new apps adopt them. Developer experience is another cornerstone. You will contribute to crafting an end‑to‑end GenAI SDK, CLI and starter kits that let AI engineers spin up secure, observable agentic workflows in under minutes, shrinking prototyping to production timelines by 30%. Trust and safety remain paramount; you will help bring together a vision of central guardrail services - prompt firewalls, content‑filter hooks, red‑team harnesses and audit APIs - consumed by every application to ensure zero Sev4 incidents. You will collaborate with cross‑organization architects to drive end‑to‑end performance by optimizing orchestration - level batching, retrieval caching, heuristic tuning to achieve reductions in per‑token spend. You will accelerate innovation by incubating proof of concepts and driving RFCs such as hierarchical agent memory, multimodal guardrails, multimodal RAG. You'll own central Helm charts, operators and CRDs that auto‑scale agents to hit tenant SLAs. Finally you will coach and evangelize - hosting architecture office hours, mentoring Staff, Principal and Senior engineers, authoring technical design documents and blogs and representing Capital One at Tier1 AI conferences - to amplify platform vision across internal and external communities. Basic Qualifications Bachelor's degree in Computer Science, Engineering, or AI plus at least 8 years of experience developing AI and ML algorithms or technologies, or Master's degree plus at least 6 years of experience developing AI and ML algorithms or technologies. At least 8 years of experience programming with Python, Go, Scala, or Java. Preferred Qualifications 8+ years of experience deploying scalable and responsible AI solutions on cloud platforms (e.g. AWS, Google Cloud, Azure, or equivalent private cloud). 2+ years of experience supporting Agentic Frameworks (LangChain, CrewAI, Semantic Kernel (Microsoft), or AutoGen). 2+ years of experience with LLMOps (Google Cloud Vertex AI, Amazon SageMaker, Azure Machine Learning). 8+ years of experience designing mission‑critical machine learning platforms. 2+ years of experience architecting, designing, developing, integrating, delivering, and supporting complex AI systems. Demonstrated ability to lead and mentor multiple engineering teams and influence cross‑functional stakeholders up to the VP level. Experience developing AI and ML algorithms or technologies (e.g. LLM inference, similarity search and VectorDBs, guardrails, memory) using Python, C++, C#, Java, or Golang. Master's degree in Computer Science, Computer Engineering, or relevant technical field. Experience developing and applying state‑of‑the‑art techniques for optimizing training and inference software to improve hardware utilization, latency, throughput, and cost. Excellent communication and presentation skills, with the ability to articulate complex AI concepts to peers. Experience leading GenAI or LLM‑Powered application architectures in production. Deep understanding of Responsible AI, data privacy and multi‑tenant security patterns. Experience as a Staff‑plus or Distinguished IC engineer influencing 50+ engineers and C‑suite stakeholders. K8s mastery (multi‑region clusters, service mesh). Experience staying abreast of the latest AI research and AI systems and applying novel techniques in production. Capital One will consider sponsoring a new qualified applicant for employment authorization for this position. The minimum and maximum full‑time annual salaries for this role are listed below, by location. Please note that this salary information is solely for candidates hired to perform work within one of these locations, and refers to the amount Capital One is willing to pay at the time of this posting. Salaries for part‑time roles will be prorated based upon the agreed upon number of hours to be regularly worked. San Francisco, CA: $293,600 - $335,100 for Distinguished AI Engineer San Jose, CA: $293,600 - $335,100 for Distinguished AI Engineer Candidates hired to work in other locations will be subject to the pay range associated with that location, and the actual annualized salary amount offered to any candidate at the time of hire will be reflected solely in the candidate's offer letter. This role is also eligible to earn performance based incentive compensation, which may include cash bonus(es) and/or long term incentives (LTI). Incentives could be discretionary or non discretionary depending on the plan. Capital One offers a comprehensive, competitive, and inclusive set of health, financial and other benefits that support your total well‑being. Learn more at Capital One Careers website. Eligibility varies based on full or part‑time status, exempt or non‑exempt status, and management level. This role is expected to accept applications for a minimum of 5 business days. No agencies please. Capital One is an equal opportunity employer (EOE, including disability/vet) committed to non‑discrimination in compliance with applicable federal, state, and local laws. Capital One promotes a drug‑free workplace. Capital One will consider for employment qualified applicants with a criminal history in a manner consistent with the requirements of applicable laws regarding criminal background inquiries, including, to the extent applicable, Article 23‑A of the New York Correction Law; San Francisco, California Police Code Article 49, Sections 4901‑4920; New York City's Fair Chance Act; Philadelphia's Fair Criminal Records Screening Act; and other applicable federal, state, and local laws and regulations regarding criminal background inquiries. If you have visited our website in search of information on employment opportunities or to apply for a position, and you require an accommodation, please contact Capital One Recruiting at ************** or via email at RecruitingAccommodation@capitalone.com. All information you provide will be kept confidential and will be used only to the extent required to provide needed reasonable accommodations. For technical support or questions about Capital One's recruiting process, please send an email to **********************. Capital One does not provide, endorse nor guarantee and is not liable for third‑party products, services, educational tools or other information available through this site. Capital One Financial is made up of several different entities. Please note that any position posted in Canada is for Capital One Canada, any position posted in the United Kingdom is for Capital One Europe and any position posted in the Philippines is for Capital One Philippines Service Corp. (COPSSC). #J-18808-Ljbffr

A global technology company is looking for a seasoned software engineer to enhance AI capabilities within their observability platform. Candidates should have a strong background in AI/ML systems, cloud computing, and robust technical leadership. This role is pivotal in driving innovation in data analysis and delivering scalable solutions. The ideal candidate will thrive in an agile environment and provide mentorship to junior engineers. Enjoy competitive salaries and benefits while contributing to impactful technology solutions. #J-18808-Ljbffr