Keysight Technologies Internships

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Design Verification Engineer Intern to join our Memory Interface Chip team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities * Understand the architecture of the chip and functional blocks. * Develop/maintain verification environments for chip level verification and enhance/use the automated regression infrastructures. * Create testplan and develop test cases/sequences in UVM. * Debug functional issues in the DUT based on the good understanding of the architectural specification. * Closely work with Design/Architecture/Circuit team to identify and align with the Milestones and Quality metrics of the project. Qualifications * Major in EE, CS or related. * Proficient in Verilog, systemverilog and UVM. * Familiar with Linux environment and the industry's prevailing EDA tools. * Have better understanding of Verification methodology and concepts. * Have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release. * Have excellent communication skills (both written and oral) and cross-team/function collaboration capability. * Experienced in code coverage and functional coverage closure. * Strong problem-solving skills. About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow's systems. The US salary range for this full-time position is $24.96 to $46.35. Our salary ranges are determined by role, level and location. The successful candidate's starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/. #LI-HYBRID #LI-LH1

We can't predict what the future holds, but we know Texas Instruments will have a part in shaping it. At TI, Systems engineers focus deeply on understanding the technical needs, and future trends of an industry or end equipment, then create new products and innovative forward-looking product roadmaps to solve them. Systems Engineers are an integral part each phase of new product development at TI. In the early stages of product development, systems engineers interface with key stakeholders (customer decision-makers, application engineers, marketing, management, sales, IC design engineers, technology development) to negotiate specifications, perform trade-offs, understand the competitive landscape, and ultimately develop detailed technical definitions for new products. They then collaborate with the full IC development team (design, applications, test, product engineers) to deliver products to the market which are compelling, competitive, cost-conscious, manufacturable, and importantly, successful in growing TI's business. In this systems engineering intern role, you'll have the chance to: Develop, model, simulate, and optimize innovative MEMS transducers across multiple domains such as electric, acoustic, magnetic, etc. Drive the innovative concepts towards successful commercialization by working with product lines. Work with process experts to understand and optimize MEMS manufacturing process Create and maintain compact behavioral models for use in system simulations Assess, define, and negotiate MEMS device specifications based on system requirements Perform optimization based on the defined MEMS specifications. Gather user requirements, translate them to functional specifications, and implement solutions and enhancement projects Put your talent to work with us as a systems engineering intern - change the world, love your job! Preferred Qualifications: Extensive experience with MEMS modeling FEM tools (COMSOL, ANSYS) Deep understanding of the design, manufacturing and optimization of MEMS transducers Deep understanding of fundamental physics across multiple domains, including but not limited to electric, acoustic, magnetic, optic, etc. Solid understanding of MEMS fabrication processes Proficiency in multiphysics FEM modeling (e.g., COMSOL) Proficiency in signal processing tools (Matlab, Python) Understanding of and experience with schematic design, PCB layout, circuit debugging and system testing Strong hands-on capability to run experiments Ability to establish strong relationships with key stakeholders critical to success, both internally and externally Strong verbal and written communication skills to audiences of varied background Ability to simplify complex problems and navigate uncertainty Ability to quickly ramp on new systems and processes Demonstrated strong interpersonal, analytical and problem-solving skills Ability to work in teams and collaborate effectively with people in different functions Ability to take the initiative and drive for results Strong time management skills that enable on-time project delivery

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Detailed understanding of physical design automation flow and EDA tool functions. Running EDA tools in each technical area to qualify the flow automation and QA. Generating feedback for bug fixes and enhancements. Developing documentation for knowledge sharing and training. Tracking project schedules and documenting all phases of work. Skill Requirements: Understanding of ASIC design flow. Good knowledge of physical design automation flow, Tcl or Perl scripting , MS Office. VLSI design experience. RTL design using Verilog HDL is preferred. Good trouble-shooting skills. Education Requirements: BS or above We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. PLM Configuration Analyst Intern (HSV MFG) PLM Configuration Analyst Intern should have the ability to excel in a high-energy, small, focused team environment, drive solutions from rough requirements, and have a commitment to high product quality. This position requires a quick learner and demonstrates ability to work in a cross functional environment. A strong sense of shared responsibility and shared reward is required, as is the ability to make work fun and interesting. In this key role, you will be instrumental in ensuring that the Cadence Palladium and Protium product development and release to manufacturing process flows meet the company's demanding mission critical reliability and quality expectations. Position reports to: PLM Configuration Analysis Manager Location: San Jose, CA Responsibilities will include, but not be limited to the following: Follows standard practices and procedures in completing analysis or tasks. Works on assignments and problems of limited scope requiring judgment and initiative, using standard prescribed practices and procedures. Responsible for implementation of small, non-complex systems; minimal design and analysis work Minimum Requirements Enrolled in BS CS, CE, ECE, or equivalent. Able to read and work from schematics and device data sheets. Ability to learn new software Excellent verbal and written communications skills. Independent, hard-working, creative, focused organized, ability to work within a start-up team on multiple projects concurrently. Highly Desirable Knowledge/Experience: Computer skills to include MS Word, Excel, Access & generic Electronic Experience with PLM tools like Arena or Agile Experience with Silicon Expert Authorization to work in U.S. is required. We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is an amazing opportunity to work as a software engineering intern at a world leader in computational software. Our customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare. As a software engineering intern, you will help design and develop some of the most complex software tools used by designers across multiple verticals. We use advanced math, computer science, graph theory and machine learning to turn design concepts into reality. Responsibilities will include software development, debugging and fixing of software errors, implementing new features, along with writing and running tests. Position Requirements: Enrolled in a MS or BS program in computer science, electrical engineering, computer engineering, or a similar major. Strong understanding of software data structures, algorithms, and proficiency in object-oriented coding, preferably in C or C++. Exposure to Cadence products is a plus. The annual salary range for Cali fornia is $28.60 to $53.12 an hour . Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid holidays and 401(k) plan with employer match. We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. You will be a member of an expert R&D team creating technologies and products that enable static and dynamic transistor level analysis and characterization of the most advanced custom digital and mixed-signal circuits built for communication, IOT and AI markets. Your work will be focused on: - Enhancing and expanding the existing tools' architecture to cover transistor level modeling for timing analysis and characterization of memory designs. - Enhancements for analysis of transistor level effects dominant at lower technology nodes Desired Skills and Experience: - Currently pursuing BS or MS in Computer Science, Computer Engineering, Electrical Engineering - Industry experience developing and maintaining C++ based applications on a Unix or Linux environment - Experience with quality and software processes - Experience designing data structures, algorithms, and software engineering principles ****************** As a condition of employment with Cadence, newly hired employees will be required to provide Cadence with proof of full vaccination, unless legally entitled to an accommodation. ****************** We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are seeking a highly motivated MS student currently enrolled in a U.S. university for a 3 month internship with our Product Engineering team. This role offers a unique opportunity to work closely with the R&D team on Cadence's industry-leading Genus Synthesis Solution, contributing to the evolution of synthesis and place & route technologies. Key Responsibilities Collaborate with the Product Engineering team to evaluate and improve Genus, a logic synthesis tool used to optimize Power, Performance, and Area (PPA) for advanced digital ASICs. Analyze and validate new features within Genus, ensuring correctness and identifying optimal configurations. Explore and address challenges in physically aware synthesis, bridging the gap between logic synthesis and place & route. Support internal teams and customers by troubleshooting tool usage and providing first-line feedback to R&D. Contribute to the interoperability of Genus with other Cadence digital implementation tools. Assist in documenting Product Requirement Specifications (PRS) for new features based on internal and external feedback. Preferred Qualifications Currently pursuing an MS in Electrical Engineering, ECE or Computer Engineering with a focus on VLSI design. Academic or past work experience in EDA, logic synthesis, physical design, or timing closure is a plus. Familiarity with Cadence tools such as Genus and Innovus is a plus. Exposure to advanced process nodes (7nm and below) through coursework or projects. Strong understanding of HDLs (Verilog/SystemVerilog), logic design, and timing analysis. Proficiency in scripting languages such as Perl/Python, Tcl, or shell scripting. Experience or interest in AI applications and agentic frameworks is a plus. Strong analytical and debugging skills, with the ability to perform root-cause analysis and communicate findings effectively. This internship is ideal for students passionate about digital design and EDA, looking to gain hands-on experience in a fast-paced, innovation-driven environment. We're doing work that matters. Help us solve what others can't.

**We can't predict what the future holds, but we know Texas Instruments will have a part in shaping it.** At TI, Systems engineers focus deeply on understanding the technical needs, and future trends of an industry or end equipment, then create new products and innovative forward-looking product roadmaps to solve them. Systems Engineers are an integral part each phase of new product development at TI. In the early stages of product development, systems engineers interface with key stakeholders (customer decision-makers, application engineers, marketing, management, sales, IC design engineers, technology development) to negotiate specifications, perform trade-offs, understand the competitive landscape, and ultimately develop detailed technical definitions for new products. They then collaborate with the full IC development team (design, applications, test, product engineers) to deliver products to the market which are compelling, competitive, cost-conscious, manufacturable, and importantly, successful in growing TI's business. In this systems engineering intern role, you'll have the chance to: + Develop, model, simulate, and optimize innovative MEMS transducers across multiple domains such as electric, acoustic, magnetic, etc. + Drive the innovative concepts towards successful commercialization by working with product lines. + Work with process experts to understand and optimize MEMS manufacturing process + Create and maintain compact behavioral models for use in system simulations + Assess, define, and negotiate MEMS device specifications based on system requirements + Perform optimization based on the defined MEMS specifications. + Gather user requirements, translate them to functional specifications, and implement solutions and enhancement projects Put your talent to work with us as a systems engineering intern - change the world, love your job! **Why TI?** + Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. + We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI (*************************************** UI/CandidateExperience/en/sites/CX/pages/4012) + Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. **About Texas Instruments** Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com . Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, disability, genetic information, national origin, gender, gender identity and expression, age, sexual orientation, marital status, veteran status, or any other characteristic protected by federal, state, or local laws. If you are interested in this position, please apply to this requisition. **Preferred Qualifications:** + Extensive experience with MEMS modeling FEM tools (COMSOL, ANSYS) + Deep understanding of the design, manufacturing and optimization of MEMS transducers + Deep understanding of fundamental physics across multiple domains, including but not limited to electric, acoustic, magnetic, optic, etc. + Solid understanding of MEMS fabrication processes + Proficiency in multiphysics FEM modeling (e.g., COMSOL) + Proficiency in signal processing tools (Matlab, Python) + Understanding of and experience with schematic design, PCB layout, circuit debugging and system testing + Strong hands-on capability to run experiments + Ability to establish strong relationships with key stakeholders critical to success, both internally and externally + Strong verbal and written communication skills to audiences of varied background + Ability to simplify complex problems and navigate uncertainty + Ability to quickly ramp on new systems and processes + Demonstrated strong interpersonal, analytical and problem-solving skills + Ability to work in teams and collaborate effectively with people in different functions + Ability to take the initiative and drive for results + Strong time management skills that enable on-time project delivery **Base Range Info:** Base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. Your base pay will depend on your skills, qualifications, experience, and location. The base pay range for this role is shown below. **Base Range:** $31.00 - $45.00 per hour **ECL/GTC Required:** Yes

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join the Digital & Signoff Group (DSG) at Cadence and contribute to the development of the Genus Synthesis Solution, a state-of-the-art logic synthesis tool that optimizes Power, Performance, and Area (PPA) for advanced digital ASICs. This internship offers hands-on experience in software development for EDA tools, working closely with R&D and product engineering teams in a collaborative, innovation-driven environment. Responsibilities Design, implement, troubleshoot, and debug software programs on Unix/Linux platforms. Develop and enhance algorithms for logic synthesis and physical design flows. Validate new synthesis features and ensure correctness and optimal configurations. Assist with customer support by analyzing tool usage and providing feedback to R&D. Contribute to documentation, including Product Requirement Specifications (PRS) for new features. Required Qualifications Currently pursuing a PhD in Computer Science, Electrical Engineering, or Computer Engineering. Strong programming skills in C/C++; exposure to Python and Tcl is a plus. Solid understanding of data structures, algorithms, and object-oriented programming. Familiarity with logic synthesis, physical design, and timing analysis. Experience with Unix/Linux environments. Excellent analytical and problem-solving skills; strong communication abilities. The annual salary range for Cali fornia is $28.60 to $53.12 an hour . Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid holidays and 401(k) plan with employer match. We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. * Detailed understanding of physical design automation flow and EDA tool functions. * Running EDA tools in each technical area to qualify the flow automation and QA. * Generating feedback for bug fixes and enhancements. * Developing documentation for knowledge sharing and training. * Tracking project schedules and documenting all phases of work. Skill Requirements: * Understanding of ASIC design flow. Good knowledge of physical design automation flow, Tcl or Perl scripting , MS Office. * VLSI design experience. RTL design using Verilog HDL is preferred. * Good trouble-shooting skills. Education Requirements: * BS or above We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are seeking a highly motivated MS student currently enrolled in a U.S. university for a 3 month internship with our Product Engineering team. This role offers a unique opportunity to work closely with the R&D team on Cadence's industry-leading Genus Synthesis Solution, contributing to the evolution of synthesis and place & route technologies. Key Responsibilities * Collaborate with the Product Engineering team to evaluate and improve Genus, a logic synthesis tool used to optimize Power, Performance, and Area (PPA) for advanced digital ASICs. * Analyze and validate new features within Genus, ensuring correctness and identifying optimal configurations. * Explore and address challenges in physically aware synthesis, bridging the gap between logic synthesis and place & route. * Support internal teams and customers by troubleshooting tool usage and providing first-line feedback to R&D. * Contribute to the interoperability of Genus with other Cadence digital implementation tools. * Assist in documenting Product Requirement Specifications (PRS) for new features based on internal and external feedback. Preferred Qualifications * Currently pursuing an MS in Electrical Engineering, ECE or Computer Engineering with a focus on VLSI design. * Academic or past work experience in EDA, logic synthesis, physical design, or timing closure is a plus. * Familiarity with Cadence tools such as Genus and Innovus is a plus. * Exposure to advanced process nodes (7nm and below) through coursework or projects. * Strong understanding of HDLs (Verilog/SystemVerilog), logic design, and timing analysis. * Proficiency in scripting languages such as Perl/Python, Tcl, or shell scripting. * Experience or interest in AI applications and agentic frameworks is a plus. * Strong analytical and debugging skills, with the ability to perform root-cause analysis and communicate findings effectively. This internship is ideal for students passionate about digital design and EDA, looking to gain hands-on experience in a fast-paced, innovation-driven environment. We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. As an R&D intern, your focus area will be developing the next generation routing engine. You will work in a team environment to design, improve, and maintain core routing technology as part of Innovus Digital Implementation system. Routing algorithm knowledge is preferred to implement a robust and efficient routing engine. As an R&D engineer, your focus area will be developing the next generation routing engine. You will work in a team environment to design, improve, and maintain core routing technology as part of Innovus Digital Implementation system. Position Requirements: In progress with MS/Phd in Computer Engineering or Computer Science C/C++ knowledge Unix/Linux The annual salary range for Cali fornia is $28.60 to $53.12 an hour . Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid holidays and 401(k) plan with employer match. We're doing work that matters. Help us solve what others can't.

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Test Engineeing Intern to join our Engineering team in San Jose, CA. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a Test Engineering Intern, you will be reporting to the designated Engineering Manager or Sr Level Mentor and is a Full-Time position. The candidate will be joining a team to work on cutting edge memory and silicon IP technology shaping the future of data centers and high-performance systems. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities * Work with DFT and design team to define test plans for new products. * Develop test strategies with the design and validation engineering teams to ensure product performance during all product life cycle phases * Wafer-sort development * Bench test capability to correlate/debug the ATE TP. * Test plan documentation compiling the test instructions from DE and other teams. * Work with product engineering to attain target yield and test time * Have a complete test program ready in advance of first silicon * Bring-up and debug first silicon quickly in order to identify any potential design or yield issues * Optimize test programs for volume manufacturing so product cost is in-line with cost model * Identify areas of improvement in current production test programs * Generate user test methods for device characterization and production Qualifications * BS degree in Electrical/Electronics with some relevant experience * Knowledge with high-speed testing * Strong programming background (C, C++, PERL) * Knowledge of DFT (scan, IDDQ, JTAG) and analog test methodologies About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow's systems. Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership. The US salary range for this full-time position is $24.96 to $46.35. Our salary ranges are determined by role, level and location. The successful candidate's starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. + Detailed understanding of physical design automation flow and EDA tool functions. + Running EDA tools in each technical area to qualify the flow automation and QA. + Generating feedback for bug fixes and enhancements. + Developing documentation for knowledge sharing and training. + Tracking project schedules and documenting all phases of work. Skill Requirements: + Understanding of ASIC design flow. Good knowledge of physical design automation flow, Tcl or Perl scripting , MS Office. + VLSI design experience. RTL design using Verilog HDL is preferred. + Good trouble-shooting skills. Education Requirements: + BS or above We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This position is for a summer internship, who will be working with a mentor to develop and improve global placement and detailed placement QoR in Innovus Digital Implementation System. Strong problem solving, analysis, and programming skills are required. Position Requirements: The candidate will require a deep knowledge of most up-to-date placement technologies with MS or PhD in EE or CS. The relevant industry experience or graduate school research is preferred.We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are seeking a highly motivated MS student currently enrolled in a U.S. university for a 3 month internship with our Product Engineering team. This role offers a unique opportunity to work closely with the R&D team on Cadence's industry-leading Genus Synthesis Solution, contributing to the evolution of synthesis and place & route technologies. Key Responsibilities + Collaborate with the Product Engineering team to evaluate and improve Genus, a logic synthesis tool used to optimize Power, Performance, and Area (PPA) for advanced digital ASICs. + Analyze and validate new features within Genus, ensuring correctness and identifying optimal configurations. + Explore and address challenges in physically aware synthesis, bridging the gap between logic synthesis and place & route. + Support internal teams and customers by troubleshooting tool usage and providing first-line feedback to R&D. + Contribute to the interoperability of Genus with other Cadence digital implementation tools. + Assist in documenting Product Requirement Specifications (PRS) for new features based on internal and external feedback. Preferred Qualifications + Currently pursuing an MS in Electrical Engineering, ECE or Computer Engineering with a focus on VLSI design. + Academic or past work experience in EDA, logic synthesis, physical design, or timing closure is a plus. + Familiarity with Cadence tools such as Genus and Innovus is a plus. + Exposure to advanced process nodes (7nm and below) through coursework or projects. + Strong understanding of HDLs (Verilog/SystemVerilog), logic design, and timing analysis. + Proficiency in scripting languages such as Perl/Python, Tcl, or shell scripting. + Experience or interest in AI applications and agentic frameworks is a plus. + Strong analytical and debugging skills, with the ability to perform root-cause analysis and communicate findings effectively. This internship is ideal for students passionate about digital design and EDA, looking to gain hands-on experience in a fast-paced, innovation-driven environment. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. You will be a member of an expert R&D team creating technologies and products that enable static and dynamic transistor level analysis and characterization of the most advanced custom digital and mixed-signal circuits built for communication, IOT and AI markets. Your work will be focused on: - Enhancing and expanding the existing tools' architecture to cover transistor level modeling for timing analysis and characterization of memory designs. - Enhancements for analysis of transistor level effects dominant at lower technology nodes Desired Skills and Experience: - Currently pursuing BS or MS in Computer Science, Computer Engineering, Electrical Engineering - Industry experience developing and maintaining C++ based applications on a Unix or Linux environment - Experience with quality and software processes - Experience designing data structures, algorithms, and software engineering principles ******************As a condition of employment with Cadence, newly hired employees will be required to provide Cadence with proof of full vaccination, unless legally entitled to an accommodation.****************** We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Rambus, a premier chip and silicon IP provider, is seeking a bright and motivated internship (co-op) student in either an Engineering or Computer Science program for a 4 month or 8 month work term within the Firmware Engineering team in the Memory Interface Chips Business Unit. The student will work alongside some of the brightest inventors and engineers in the world to develop firmware and software solutions that make data faster and safer. During the internship, the student will join a Firmware Engineering team to work on cutting edge memory and silicon technology shaping the future of data centers and high-performance systems. The student will develop, test, and debug software for memory diagnostic applications and embedded CPUs in System-On-Chips (SoCs). The student will gain experience with processor-memory interfaces, DDR5, BIOS, Redfish, OpenBMC, as well as other third-party SW stacks. The student should have a strong interest in embedded software development and electronics, and be a self-starter with strong organizational, communication, teamwork, and debugging skills. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities * Design, implement, test, and debug software for embedded devices and systems, from requirements to deployment. * Write unit tests and feature tests for test automation. * Setup, maintain, and debug systems used for DDR5 memory diagnostic development. * Follow coding convention and best practices of the team, and conduct code reviews. Qualifications * C/C++ programming skills. * Ability to follow technical guidance from senior team members. * Excellent written and verbal communication skills. Desired Skills: * Previous embedded software courses and / or projects. * One or more previous co-op terms, preferably with embedded development experience. * Python scripting skills About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow's systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/. #LI-HYBRID #LI-GL1

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Looking for an individual with strong C++ and software development skills, and with interests in database or integrated circuit design to join the Virtuoso R&D Infrastructure team as a summer intern. The Virtuoso R&D Infrastructure team is responsible for the OpenAccess database, data translation, inter-process collaboration and communication, LLM based search and other infrastructure components of Virtuoso Studio. OpenAccess is an industry standard database used in the design of integrated circuits. Virtuoso Studio is the preeminent platform for full custom/analog design of integrated circuits including RF, mixed-signal, photonics, and advanced heterogenous designs. Candidates working toward a Master's Degree in Computer Science or Electrical Engineering are preferred but we will consider other candidates with sufficient experience. Understand: Get to know the Virtuoso Infrastructure team and their role. Understand the projects and products that the team is responsible for. Participate in the Cadence Virtuoso Infrastructure team's software development methodology. Responsibilities: Writing code to specification with guidance from software architects Running tests and performance benchmarks Participating in code reviews and other software development processes Job Requirements: Currently enrolled as BS or MS or Phd student majoring in Computer Science or Electrical Engineering Looking for strong C++, algorithms, and software development skills. Good written and verbal communication skills. Must be able to relocate to Headquarters in San Jose, CA We're doing work that matters. Help us solve what others can't.