Manufacturing Engineer jobs at Keysight Technologies - 188 jobs

Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do. Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers. Responsibilities Keysight Technologies is hiring full-time equipment technicians for a semiconductor manufacturing facility. This position is at our Santa Rosa, California site, located in the wine country, about one hour north of San Francisco. Santa Rosa is a medium-size city of 175,000 people, with a mild climate and many recreational opportunities. Keysight in Santa Rosa is a product development site and has many technically challenging jobs. We design and build test instruments for RF/microwave communications, 5G, and autonomous vehicles. Keysight culture values teamwork, collaboration, work/life balance, diversity and inclusivity. Keysight has been voted a Great Place to Work four years in a row. Job Description: Maintenance Technician to Support IC Manufacturing in Semiconductor Fab Work with R&D semiconductor equipment in Keysight's High Frequency Technology Center Wafer Fab. Maintain and repair electro-mechanical equipment that may use high vacuum, sub-micron precision, exotic chemistry, advanced imaging, and many other state-of-the-art manufacturing techniques. Work closely with process engineers and operators to aid in both volume production and R&D process development. Work with suppliers to select and purchase spare parts, and to coordinate service visits. Perform preventative maintenance and emergency repairs in a manufacturing environment. Work closely with our Equipment Engineering team to: Assist in the retirement of legacy tools Develop written maintenance procedures Install new process tools Develop PM and repair procedures and determine spare parts requirements Assist with implementing hardware improvements and automation projects. Qualifications Minimum Requirements: Maintenance experience with manufacturing equipment or other complex systems. Familiarity with Microsoft Office suite of tools and standard engineering practices. Strong personal and e-mail communication skills. Proven ability to manage multiple responsibilities simultaneously and solve complex problems independently. Ability to learn on the job and work with cutting edge technologies and processes. Desire to work in a highly technical organization with a very strong and inclusive team. Ideal candidates for this position would possess some of the following attributes: Previous experience maintaining semiconductor equipment or complex manufacturing hardware AS/BA/BS degree in Electronics, military electronics training, or strong electro-mechanical technical capability. Previous experience working across disciplines including mechanics, electronics, materials science, and software engineering. Experience with semiconductor manufacturing techniques is highly desired. Experience with high vacuum technology, deposition methods, different etching technologies and RF sources. Pay Range: USD $67,030.00 - USD $111,720.00 Year Note: For other locations, pay ranges will vary by region This role is eligible for Keysight Results Bonus Program US Employees may be eligible for the following benefits: Medical, dental and vision Health Savings Account Health Care and Dependent Care Flexible Spending Accounts Life, Accident, Disability insurance Business Travel Accident and Business Travel Health 401(k) Plan Flexible Time Off, Paid Holidays Paid Family Leave Discounts, Perks Tuition Reimbursement Adoption Assistance ESPP (Employee Stock Purchase Plan) Restricted Stock Units Visa Sponsorship is unavailable for this position Careers Privacy Statement***Keysight is an Equal Opportunity Employer.***

A leading technology company is seeking a GPU Physical Design Engineer to drive advanced clocking solutions. The role involves high-speed clock distribution and collaboration with cross-functional teams. Applicants should have a Bachelor's degree with significant industry experience, strong skills in circuit simulations, and experience in SOC Clock Implementation. This position offers competitive compensation and a hybrid work model allowing flexibility between on-site and off-site work. #J-18808-Ljbffr

A leading technology company is seeking a Physical IC Design Engineer in San Jose, California. The role involves executing various physical design tasks and requires a bachelor's degree in Electrical or Electronics Engineering with over 12 years of relevant experience. Strong scripting skills and expertise in EDA tools are essential. The position offers a competitive salary range of $141,300 - $226,000 along with comprehensive benefits including health insurance, 401(K) matching and more. #J-18808-Ljbffr

# **Welcome!**## .GPU Physical Design Engineer page is loaded## GPU Physical Design Engineerlocations: US, California, Folsom: US, California, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR0279213# **Job Details:**## Job Description:Are you interested in working in a fast-paced, leading-edge environment with endless possibilities of innovating and learning, then our Graphics Hardware IP Team (GHI) team has an opportunity for you. In GHI we are passionate about delivering best-in-class visual experiences that enable users to immerse themselves in a new visual future. Within GHI you will be part of a Special Circuits Horizontal team that is responsible for local and global clocking of large designs like GFX Imaging processors, Peripheral subsystems like PCIe, Type-C, Display, Media and SOCs etc. We are looking for Graphics Hardware Clocking/Engineer to join the team.**The primary responsibilities for this role will include, but are not limited to:*** Ownership of complex highspeed global and local clock distribution network to meet the Power and Performance targets of these differentiating designs.* Work with Architects, PnP and Execution teams to identify right solutions in a timely manner.## **Qualifications:****A successful candidate will have proven experience demonstrating the following skills and behavioral traits:*** Team player with good problem-solving skills.* Strong written and verbal communication skills.**Minimum Qualifications**:Minimum qualifications are required to be initially considered for this position.* Bachelor's in Electrical/ Electronics/Computer Engineering, Computer Science or related field with at least 10 years of industry experience. Or a Master's degree in the same fields with at least 8 years of industry experience.* Advanced knowledge of Spice level circuit simulations.* Advanced experience in global and local clocking topologies.* 6+ years of hands on SOC Clock Implementation experience.* Basic understanding of RV and FEV flows.* Basic Scripting knowledge.## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:US, California, Folsom## Additional Locations:US, California, Santa Clara## Business group:Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A**Benefits:**We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:Annual Salary Range for jobs which could be performed in the US: $161,230.00-227,620.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \* Job posting details (such as work model, location or time type) are subject to change. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking a Physical IC Design Engineer to drive next-generation AI and ML ecosystems through PCIe Switch Products. This role requires a strong background in Physical Design, including execution of design, verification, and timing closure. The ideal candidate must have a Bachelor's degree in Electrical or Electronics Engineering and at least 8 years of experience. The position offers a competitive salary range of $120,000 to $192,000, along with comprehensive benefits. #J-18808-Ljbffr

A leading technology company in San Jose is looking for a Physical IC Design Engineer to drive next-gen AI and ML ecosystems. The role requires 8+ years of experience and a Bachelor's degree in Electrical or Electronics Engineering. Responsibilities include execution of Physical Design, Synthesis, and collaborating with IC Design engineers. This position has a salary range of $120,000 - $192,000 and offers a comprehensive benefits package including health plans, 401(K) matching, and paid leave. #J-18808-Ljbffr

A leading technology firm located in San Jose is seeking a Physical IC Design Engineer to drive innovation in Artificial Intelligence and Machine Learning through their products. This position focuses on executing the physical design and verification of chip architectures. Candidates should possess a Bachelor's degree in Electrical Engineering or Electronics Engineering and have over 8 years of relevant experience. The role offers a competitive salary ranging from $120,000 to $192,000, plus various benefits including medical and retirement plans. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking an experienced Physical IC Design Engineer to join their Data Center Solutions Group. You will drive advancements in AI/ML ecosystems and manage data centers. The ideal candidate will have over 12 years of experience in physical design and proficiency in TCL/PERL scripting. A Bachelor's degree in Electrical or Electronics Engineering is required. This position offers a competitive salary and comprehensive benefits package, including health insurance and 401(k) matching. #J-18808-Ljbffr

A leading technology firm in San Jose is seeking a Physical Design Engineer to focus on the implementation and optimization of IC layouts for advanced technologies. The ideal candidate has extensive experience in physical layout, strong scripting skills in TCL and Python, and a solid background in electrical engineering. This role offers a competitive salary, bonus potential, and comprehensive benefits. #J-18808-Ljbffr

A leading electronic design automation company in California seeks an experienced SoC/ASIC Digital Design Engineer with a strong focus on Design for Test (DFT) methodologies. The ideal candidate will have substantial expertise in scan chain insertion, compression scan technologies, and automatic test pattern generation (ATPG), along with strong problem-solving skills and the ability to work collaboratively in a cross-functional team environment. This is a fantastic opportunity to contribute to essential technology projects. #J-18808-Ljbffr

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 6 - 15 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem‑solving skills are top‑notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You'll Be Doing: Designing, developing, and troubleshooting core algorithms for compiler. Collaborating with local and global teams to enhance runtime performance for verilog compiler. Engaging in pure technical roles focused on software development and architecture. Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation. Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting‑edge solutions. The Impact You Will Have: Driving technological innovation in chip design and verification. Enhancing the performance and quality of simulation tools used globally. Solving complex compiler optimizations problems to improve simulation performance. Collaborating with cross‑functional teams to achieve project milestones. Pioneering new software architectures that set industry standards. What You'll Need: Strong hands‑on experience in C/C++ based software development. Deep understanding of design patterns, data structures, algorithms, and programming concepts. Knowledge of ASIC design flow and EDA tools and methodologies. Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: Highly enthusiastic and energetic team player with excellent communication skills. Strong desire to learn and explore new technologies. Effective problem‑solver with a keen analytical mind. Experienced in working on Unix/Linux platforms. Adept at using developer tools such as gdb and Valgrind. The Team You'll Be A Part Of: You will be part of the performance team in Digital Simulation. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #J-18808-Ljbffr

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a strategic thinker and passionate innovator, ready to advance the state of the art in electronic design automation (EDA) software. You thrive in highly technical environments and excel at solving complex problems with creative, scalable solutions. Your background includes significant hands‑on experience with C++ in Linux, and you have a proven track record of developing sophisticated algorithms and data structures for large‑scale software projects. You understand the intricacies of digital chip design, including areas such as tech‑mapping, logic synthesis, place & route (P&R), logic and physical optimization. You enjoy collaborating with other experts, mentoring junior team members, and contributing to a culture of excellence and inclusivity. Autonomy and self‑direction are second nature to you, and you take pride in guiding projects from concept to completion. Your curiosity drives you to explore new technologies, and your analytical skills enable you to deliver impactful solutions that push the boundaries of what is possible in chip design automation. You are excited to join a team that values diversity, innovation, and continuous learning, and you are eager to make a lasting impact in a field that powers the future of technology. What You'll Be Doing: Designing and implementing advanced algorithms in C++ to optimize power, performance, and area (PPA) for the Fusion Compiler product. Developing and enhancing core EDA/CAD tools used by leading semiconductor companies globally. Collaborating with a highly experienced R&D team to solve complex technical challenges in digital implementation optimization. Exploring and integrating new technologies and methodologies into existing workflows. Contributing to all phases of the software development lifecycle, from concept and architecture to testing and deployment. Mentoring and guiding junior engineers, sharing knowledge and best practices to elevate team capabilities. The Impact You Will Have: Driving innovation in digital chip design automation, enabling customers to achieve industry‑leading PPA results. Shaping the future of EDA tools that power next‑generation technologies, from AI to autonomous vehicles. Accelerating time‑to‑market for cutting‑edge silicon solutions through robust, efficient, and scalable software. Empowering design teams worldwide to tackle increasingly complex design challenges with confidence. Setting new benchmarks for algorithmic excellence and software reliability in the EDA industry. Fostering a collaborative and inclusive culture that values continuous learning and sharing of expertise. What You'll Need: Expert‑level proficiency in C/C++ programming within a Linux environment. Deep understanding of data structures and algorithm development for large‑scale software projects. Prior experience in EDA/CAD tool development, specifically in areas such as tech‑mapping, logic synthesis, logic optimization, P&R, and Physical Optimization. Ability to autonomously resolve complex technical issues and select optimal solutions and methodologies. MS/Ph.D. in Computer Science, Electrical Engineering, or a related field, with 4+ years of relevant experience. Who You Are: A creative problem‑solver with strong analytical skills and attention to detail. A collaborative team player who communicates effectively and values diverse perspectives. Self‑motivated and proactive, with the ability to drive projects independently. An enthusiastic mentor and leader who enjoys sharing knowledge and supporting others. Adaptable and open‑minded, willing to learn new technologies and approaches. The Team You'll Be A Part Of: You will join the digital implementation optimization R&D team within Synopsys' EDA Group. The team is composed of seasoned software engineers and algorithm specialists dedicated to advancing the Fusion Compiler product. Together, you'll collaborate to deliver transformative solutions for chip design automation, working at the forefront of technology to enable customers' success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #J-18808-Ljbffr

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 6 - 15 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem‑solving skills are top‑notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You'll Be Doing: Designing, developing, and troubleshooting core algorithms for compiler. Collaborating with local and global teams to enhance runtime performance for verilog compiler. Engaging in pure technical roles focused on software development and architecture. Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation. Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting‑edge solutions. The Impact You Will Have: Driving technological innovation in chip design and verification. Enhancing the performance and quality of simulation tools used globally. Solving complex compiler optimizations problems to improve simulation performance. Collaborating with cross‑functional teams to achieve project milestones. Pioneering new software architectures that set industry standards. What You'll Need: Strong hands‑on experience in C/C++ based software development. Deep understanding of design patterns, data structures, algorithms, and programming concepts. Knowledge of ASIC design flow and EDA tools and methodologies. Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: Highly enthusiastic and energetic team player with excellent communication skills. Strong desire to learn and explore new technologies. Effective problem‑solver with a keen analytical mind. Experienced in working on Unix/Linux platforms. Adept at using developer tools such as gdb and Valgrind. The Team You'll Be A Part Of: You will be part of the performance team in Digital Simulation. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #J-18808-Ljbffr

Troubleshoot new or existing product problems, involving designs, materials, or processes. Designs, develops, and implements safe and cost-effective complex equipment and methods of assembly for all phases of manufacturing. Define process and methods for high volume manufacturing, which includes operations method sheet, routing, and sequencing. Perform virtual build and create sequences of assembly. Perform root cause investigation and recommend corrective action for operational problems, such as material use variances, bottlenecks, fixture issues during build or manufacturing process. Identify opportunities to improve manufacturing processes or resolve problems and follow through resolution to reduce costs, improve product quality, and cycle time. Reviews and develops designs that improve product manufacturability and assembly. Coordinate new product builds in pilot production manufacturing partnering closely with manufacturing and product engineers. Create and release engineering drawings & bill of materials (BOM) using Engineering Change Management process. Development of handoff package to allow product transition to high volume manufacturing. Bachelor's degree in Mechanical Engineering, Production Engineering, Industrial Engineering, or related field with 5+ years of experience; or Master's degree with 3+ years' experience; or equivalent experience. Skilled troubleshooting capabilities in the areas of electro/mechanical assemblies. Solid understanding of manufacturing processes. Proficient in Design for Manufacturing and Assembly (DFMA) with approach to structured problem-solving and decision-making. Proficient in software applications such as CAD modeling, Product Lifecycle Management (PLM), or Product Data Modeling (PDM) systems. Experience in Engineering Change Management Process. Working knowledge in Operation Method Sheets (OMS), process planning, and Bill of Materials (BOM) Management. Knowledge of Semiconductor equipment, Capital Equipment industry and its manufacturing processes. Effective communication and presentation skills, both written and verbal, in English. Statistical analysis skills including statistical process control and data analysis used in production setting. Knowledge in Design Failure Mode and Effect Analysis (DFMEA). Proven stakeholder management skills, with ability to influence both internal and external stakeholders or customers in technical matters.

Troubleshoot new or existing product problems, involving designs, materials, or processes. Designs, develops, and implements safe and cost-effective complex equipment and methods of assembly for all phases of manufacturing. Define process and methods for high volume manufacturing which includes operations method sheet, routing, and sequencing. Perform virtual build and create sequence of assembly. Perform root cause investigation and recommend corrective action for operational problems, such as material use variances, bottlenecks, fixture issues during build or manufacturing process. Identify opportunities to improve manufacturing processes or resolve problems and follow through resolution to reduce costs, improve product quality, and cycle time. Reviews and develops designs that improve product manufacturability and assembly. Coordinate new product builds in pilot production manufacturing partnering closely with manufacturing and product engineers. Create and release engineering drawings & bill of materials (BOM) using Engineering Change Management process. Development of handoff package to allow product transition to high volume manufacturing. Bachelor's degree in Mechanical Engineering, Production Engineering, Industrial Engineering, or related field with 5+ years of experience; or Master's degree with 3+ years' experience; or equivalent experience. Skilled troubleshooting capabilities in the areas of electro/mechanical assemblies. Solid understanding of manufacturing processes. Proficient in Design for Manufacturing and Assembly (DFMA) with approach to structured problem-solving and decision-making. Proficient in software applications such as CAD modeling, Product Lifecycle Management (PLM), or Product Data Modeling (PDM) systems. Experience in Engineering Change Management Process. Working knowledge in Operation Method Sheets (OMS), process planning, and Bill of Materials (BOM) Management. Knowledge of Semiconductor equipment, Capital Equipment industry and its manufacturing processes. Effective communication and presentation skills, both written and verbal, in English. Statistical analysis skills including statistical process control and data analysis used in production setting. Knowledge in Design Failure Mode and Effect Analysis (DFMEA). Proven stakeholder management skills, with ability to influence both internal and external stakeholders or customers in technical matters.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Are you looking to re-enter the workforce as a Physical Design Application Engineer after taking a career break for caregiving? Who is eligible to apply: Please ONLY consider applying if you are a Physical Designer and (IMPORTANT) who has been out of the workforce for caregiving for a period of at least two years and have a minimum of three years of Physical Design work experience. This role is not open to new college grads or interns. Please check our career site for those roles.Cadence is offering an opportunity to qualified candidates who meet our eligibility criteria to participate in a 16-week paid returnship program. You will be entered in a tailored program designed to jump start your skills through training, hands on projects and customer interaction. You will have an opportunity to update your resume, build connections and participate in fun events as you re-enter the workforce. In this program, you will work with best in class EDA tools, collaborate with R&D and the Sales team in a dynamic, innovative environment. Learn processes that are in the forefront of technology, how a company like Cadence works as well as experience how teams solve problems. We are seeking individuals with experience in Digital Synthesis, Place and Route and Signoff Analysis. Where is this returnship located: San Jose, CA What opportunity is offered: Candidates will find opportunities to be in the Application Engineering field spanning across Digital Synthesis, Place and Route and Signoff Analysis. How long is this returnship: 16 weeks Company Description: At Cadence, our core values are more than just words, they are the way we work, laugh, debate, care, question, and innovate together. We are One Cadence-One Team. Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation (EDA) company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Our team's shared passion for solving the world's toughest technical challenges and drive to do meaningful work makes us proud to be part of Cadence. Our unique culture has been recognized on FORTUNE Magazine's 100 Best Companies to Work For list and garnered accolades from the Great Place To Work Institute around the globe. #LI-MA1 The annual salary range for California is $59,500 to $110,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Are you looking to re-enter the workforce as a Physical Design Application Engineer after taking a career break for caregiving? Who is eligible to apply: Please ONLY consider applying if you are a Physical Designer and (IMPORTANT) who has been out of the workforce for caregiving for a period of at least two years and have a minimum of three years of Physical Design work experience. This role is not open to new college grads or interns. Please check our career site for those roles. Cadence is offering an opportunity to qualified candidates who meet our eligibility criteria to participate in a 16-week paid returnship program. You will be entered in a tailored program designed to jump start your skills through training, hands on projects and customer interaction. You will have an opportunity to update your resume, build connections and participate in fun events as you re-enter the workforce. In this program, you will work with best in class EDA tools, collaborate with R&D and the Sales team in a dynamic, innovative environment. Learn processes that are in the forefront of technology, how a company like Cadence works as well as experience how teams solve problems. We are seeking individuals with experience in Digital Synthesis, Place and Route and Signoff Analysis. Where is this returnship located: San Jose, CA What opportunity is offered: Candidates will find opportunities to be in the Application Engineering field spanning across Digital Synthesis, Place and Route and Signoff Analysis. How long is this returnship: 16 weeks Company Description: At Cadence, our core values are more than just words, they are the way we work, laugh, debate, care, question, and innovate together. We are One Cadence-One Team. Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation (EDA) company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Our team's shared passion for solving the world's toughest technical challenges and drive to do meaningful work makes us proud to be part of Cadence. Our unique culture has been recognized on FORTUNE Magazine's 100 Best Companies to Work For list and garnered accolades from the Great Place To Work Institute around the globe. #LI-MA1 The annual salary range for California is $59,500 to $110,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.

Category Engineering Hire Type Employee Job ID 12583 Base Salary Range $157000-$235000 Remote Eligible No Date Posted 21.08.2025 This position requires access to or use of information, which is subject to export restrictions, including the International Traffic in Arms Regulations (ITAR). All applicants for this position must be "U.S. Persons" within the meaning of the ITAR. "U.S. Persons" include U.S. Citizens, U.S. Lawful Permanent Residents (i.e. 'Green Card Holders'), Political Asylees, Refugees or other protected individuals as defined by 8 U.S.C. 1324b(a)(3). This role is required to work onsite in our Sunnyvale CA location. We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced engineer with a deep understanding of the RTL to GDSII flow. You thrive on solving complex technical issues and enjoy working closely with customers to enhance their experience with cutting-edge technology. With your strong background in synthesis, physical design, and static timing analysis, you excel in diagnosing and resolving technical challenges. You are an excellent communicator, capable of conveying technical concepts clearly and effectively to both technical and non-technical stakeholders. Your scripting skills in Perl, Tcl, and Python, along with your knowledge of CAD automation methods, make you a valuable asset to any team. You are motivated to work collaboratively with internal teams and customers to drive product adoption and satisfaction. What You'll Be Doing: * Providing technical and engineering insight to support and improve the usability, applicability, and adoption of Synopsys products. * Diagnosing, troubleshooting, and resolving complex technical issues on customer installations. * Deploying and training customers on new implementations and capabilities. * Reviewing and acting upon product feedback and solutions performance from customers and other application partners. * Working directly with R&D to develop and implement the technical roadmap, specifications, and validation for improvements and enhancements. * Partnering with customer technical managers and Sales to identify business challenges and develop effective technical solutions for new accounts. The Impact You Will Have: * Enhancing customer satisfaction by ensuring seamless product deployment and support. * Driving product adoption and utilization through effective technical training and support. * Contributing to the technical roadmap and product improvements based on customer feedback. * Supporting the sales team in acquiring new accounts by providing technical expertise. * Improving product performance and reliability through collaborative efforts with R&D. * Strengthening customer relationships by addressing and resolving technical challenges promptly. What You'll Need: * 7+ years of RTL to GDSII full flow experience or knowledge. * In depth experience debugging complex engineering issues related to STA, DRC/DRV and PPA optimization * Exceptional interest and knowledge of Advanced Node & Design methodologies. * Proven aptitude and motivation to work with internal and customer groups. * Excellent verbal and written presentation/communication skills. * Hands-on experience in synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis. * Knowledge of ASIC implementation domains outside of RTL2GDS including RTL coding, Verification, formal checking is a plus. * Good scripting skills (Python, Tcl, Perl); working knowledge of CAD automation methods. Who You Are: * A collaborative team player who thrives in a dynamic environment. * An excellent communicator with the ability to convey complex technical concepts effectively. * A proactive problem-solver with a keen eye for detail. * Customer-focused, with a passion for delivering exceptional service and support. * A continuous learner, always seeking to expand your technical knowledge and skills. The Team You'll Be A Part Of: You will be part of a highly skilled and dedicated team of engineers focused on providing exceptional technical support and solutions to our customers. Our team collaborates closely with R&D, Sales, and Customer Success to drive product innovation, adoption, and satisfaction. We value continuous learning, open communication, and a customer-centric approach in everything we do. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #LI-SV1 At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

Category Engineering Hire Type Employee Job ID 13867 Base Salary Range $109000-$163000 Remote Eligible No Date Posted 20/12/2025 At Synopsys, we drive the innovations that shape the way the world connects and computes. Our technology powers cutting-edge silicon in applications from mobile and AI to autonomous systems and advanced computing. Join us to help customers achieve breakthrough performance using our leading EDA tool suite. We are seeking a Physical Design Engineer with strong technical skills in digital implementation and optimization. In this role you will work with engineering teams and customers to deliver solutions that drive timing closure, power and area optimization, and robust RTL-to-GDS flows using Synopsys tools. You Are You are an ASIC/physical design engineer with 2-4 years of hands-on experience in digital implementation flows. You understand full RTL-to-GDS design flows and are comfortable applying state-of-the-art methodologies to achieve timing closure and quality signoff. You have solid scripting skills to automate flows and customize solutions, and you communicate clearly with internal teams and customers to solve complex design challenges. What You'll Be Doing * Execute RTL-to-GDSII digital implementation flows, including logic synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off quality closure. * Work with customers and internal teams to troubleshoot and optimize implementation challenges, propose solutions, and deliver highly-tuned PPA results. * Utilize Synopsys tools such as Fusion Compiler, PrimeTime, and DSO.ai/FusionAI in digital implementation and static timing analysis. * Develop and enhance automation scripts and flows using TCL, Python, Perl, or other scripting languages. * Perform static timing analysis (STA), debug timing violations, and implement ECOs to improve performance and timing closure. * Drive DRC/LVS/Signoff quality closures at advanced technology nodes. * Collaborate with customers, product teams, and research groups to share best practices and feedback to improve tool flows. What You'll Need * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. * 2-4 years of hands-on experience in digital physical design or backend implementation. * Experience with full RTL-to-GDS flows, including place & route methodologies, STA, timing closure, and signoff strategies. * Proficiency with Synopsys tools such as Fusion Compiler, PrimeTime, and familiarity with AI-assisted optimization tools (e.g., DSO.ai/FusionAI) is highly desirable. * Solid scripting skills in TCL, Python, Perl, or equivalent for flow automation. * Strong analytical ability to dissect complex timing, PPA, and design challenges. * Familiarity with unix/linux environments and engineering workflows. * Excellent communication skills and ability to work in collaborative team and customer-facing environments. Who You Are * A proactive self-starter who takes ownership of technical solutions and delivery. * Comfortable interfacing with customers and internal teams to understand requirements and deliver effective outcomes. * Able to adapt to evolving methodologies and rapidly learn emerging tool capabilities in EDA. * Detail-oriented and organized, capable of balancing multiple priorities in a fast-paced environment. The Team You'll Be Part Of Join a dynamic Applications Engineering team dedicated to customer success and powerful EDA solutions. You'll work closely with fellow engineers, researchers, and tool developers to enable high-performance physical design solutions and push the boundaries of what's possible in semiconductor design. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.