Mechanical Engineer jobs at Lam Research - 41 jobs

Responsible for mechanical engineering design and support in the Sabre Electrofill Product Group for projects tied directly to the plating cell. Exercises good judgement in mechanical design methods and evaluation criteria Completes tasks independently and recognizes when direction is needed Understand and organize highly configurable assemblies with 100s of feature options such as the Sabre cup assembly to efficiently control proliferation, compatibility and future iterations Skillful using 3D CAD tools, preferably Creo and/or NX 8 years of related experience with a Bachelor's degree in Mechanical Engineering; or 6 years and a Master's degree; or 3 years with a PhD. Exercises good judgement in mechanical design methods and evaluation criteria Completes tasks independently and recognizes when direction is needed Understand and organize highly configurable assemblies with 100s of feature options such as the Sabre cup assembly to efficiently control proliferation, compatibility and future iterations Skillful using 3D CAD tools, preferably Creo and/or NX 8 years of related experience with a Bachelor's degree in Mechanical Engineering; or 6 years and a Master's degree; or 3 years with a PhD. Knowledge of the Sabre and Sabre 3D product line and/or the fundamentals of electroplating and the semiconductor industry at large is a plus. Knowledge of Design for Manufacturability, especially for metal machining, plastics machining, elastomeric seals, and coating commodities Experience teaming with process engineering to provide technical guidance in evaluating hardware solutions Experience collaborating with suppliers to test ideas, gather manufacturability feedback, and to maintain focus on timely executing to deliverables Understanding of statistics and variability to ensure long-term part reliability Able to develop accurate problem statements and evaluate solution options Able to perform computational modeling, mainly for structural mechanics and fluid dynamics

Support the full life cycle of mechanical and electro-mechanical systems from concept to productization including conceptualization, designing, CAD modeling, development, and test/validation. Conduct detailed analysis including fluid and gas flow dynamics (CFD), heat transfer, and stress analysis to drive design decisions Design intricate mechanical components using variety of metals, ceramics, quartz, plastics, and advanced coatings. Collaborate with suppliers and internal teams to ensure solutions can be manufactured with high-quality, cost-optimized, and to requirements. Perform failure analysis to solve difficult performance and reliability problems. Bachelor's degree in Mechanical Engineering or related field with 5+ years of related experience; or Master's degree with 3+ years' experience; or a Ph. D. without experience; or equivalent work experience. Proficient in 3D CAD tools such as Creo, Siemens NX, or SolidWorks. Some experience or education in metallurgy, material science, chemical engineering, or related fields. Excellent communication, both written and verbal, and technical presentation skills. Experience in leading projects, or problem solving while managing time and multiple priorities. Experience in semiconductor industry is a plus but not a requirement.

KLA is a global leader in diversified electronics for the semiconductor manufacturing ecosystem. Virtually every electronic device in the world is produced using our technologies. No laptop, smartphone, wearable device, voice-controlled gadget, flexible screen, VR device or smart car would have made it into your hands without us. KLA invents systems and solutions for the manufacturing of wafers and reticles, integrated circuits, packaging, printed circuit boards and flat panel displays. The innovative ideas and devices that are advancing humanity all begin with inspiration, research and development. KLA focuses more than average on innovation and we invest 15% of sales back into R&D. Our expert teams of physicists, engineers, data scientists and problem-solvers work together with the world's leading technology providers to accelerate the delivery of tomorrow's electronic devices. Life here is exciting and our teams thrive on tackling really hard problems. There is never a dull moment with us. Group/Division With over 40 years of semiconductor process control experience, chipmakers around the globe rely on KLA to ensure that their fabs ramp next-generation devices to volume production quickly and cost-effectively. Enabling the movement towards advanced chip design, KLA's Global Products Group (GPG), which is responsible for creating all of KLA's metrology and inspection products, is looking for the best and the brightest research scientist, software engineers, application development engineers, and senior product technology process engineers. The Film and Scatterometry Technology (FaST) Division provides industry leading metrology solutions for worldwide semiconductor IC manufacturers. The FaST Division portfolio of metrology products includes hardware and software solutions for optical film thickness, optical critical dimension (CD), composition, and resistivity measurement systems. These products are essential for the IC manufacturers as they provide critical metrology capabilities for the development and implementation of their advanced IC processes. The FaST division is committed to support our customers to achieve performance entitlement of our solution and we effectively partner with our customers from their early research and development phase to the high volume in-line manufacturing implementation specific for their process needs. The division consists of a global team located in US, Israel, China, and India. Job Description/Preferred Qualifications Company Overview Calling the adventurers ready to join a company that's pushing the limits of nanotechnology to keep the digital revolution rolling. At KLA, we're making technology advancements that are bigger and tinier than the world has ever seen. Who are we? We research, develop, and manufacture the world's most advanced inspection and measurement equipment for the semiconductor and nanoelectronics industries. We enable the digital age by pushing the boundaries of technology, creating tools capable of finding defects smaller than a wavelength of visible light. We create smarter processes so that technology leaders can manufacture high-performance chips, the kind in that phone in your pocket, the tablet on your desk and nearly every electronic device you own faster and better. We're passionate about creating solutions that drive progress and help people do what wouldn't be possible without us. The future is calling. Will you answer? Group/Division With over 40 years of semiconductor process control experience, chipmakers around the globe rely on KLA to ensure that their fabs ramp next-generation devices to volume production quickly and cost-effectively. Enabling the movement towards advanced chip design, KLA's Global Products Group (GPG), which is responsible for creating all of KLA's metrology and inspection products, is looking for the best and the brightest research scientist, software engineers, application development engineers, and senior product technology process engineers. The Film and Scatterometry Technology (FaST) Division provides industry leading metrology solutions for worldwide semiconductor IC manufacturers. The FaST Division portfolio of metrology products includes hardware and software solutions for optical film thickness, optical critical dimension (CD), composition, and resistivity measurement systems. These products are essential for the IC manufacturers as they provide critical metrology capabilities for the development and implementation of their advanced IC processes. The FaST division is committed to support our customers to achieve performance entitlement of our solution and we effectively partner with our customers from their early research and development phase to the high volume in-line manufacturing implementation specific for their process needs. The division consists of a global team located in US, Israel, China, and India. Responsibilities Lead medium-sized projects e.g. H2H, PLC, alpha characterization, beta testing, and gap analysis. Create and evaluate characterization and field test plans. Respond to customer requests and perform complex problem diagnosis and problem resolution. Develop and document new applications of existing and pre-release products, including BKMs. Develop written procedures, standards, training material, and other technical documentation. Review and evaluate quality of data in other related technical documents. Layer owner on complex demos. Serve as Applications Representative for PLC projects. Preferred Qualifications Ph.D. degree, Masters with 2-4 years, or Bachelors with 3-5 years experience or equivalent combination of education and experience in engineering applications. Deeper understanding of each of the previous areas, plus: * Thoroughly understands engineering principles and techniques related to project activities. * Show a high degree of proficiency in several other related technical areas. * Ability to recognize system-wide issues and design accordingly. * Strong working knowledge of testing techniques * Strong working knowledge of various applications. * Ability to independently resolve complex problems. * Strong presentation skills. * Strong project management skills. KLA is an Equal Opportunity Employer. Applicants will be considered for employment without regard to age, race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability, or any other characteristics protected by applicable law. Minimum Qualifications Doctorate (Academic) Degree and 0 years related work experience; Master's Level Degree and related work experience of 3 years; Bachelor's Level Degree and related work experience of 5 years Base Pay Range: $97,600.00 - $165,900.00 Annually Primary Location: USA-OR-Hillsboro-Beaverton-KLA KLA's total rewards package for employees may also include participation in performance incentive programs and eligibility for additional benefits including but not limited to: medical, dental, vision, life, and other voluntary benefits, 401(K) including company matching, employee stock purchase program (ESPP), student debt assistance, tuition reimbursement program, development and career growth opportunities and programs, financial planning benefits, wellness benefits including an employee assistance program (EAP), paid time off and paid company holidays, and family care and bonding leave. Interns are eligible for some of the benefits listed. Our pay ranges are determined by role, level, and location. The range displayed reflects the pay for this position in the primary location identified in this posting. Actual pay depends on several factors, including state minimum pay wage rates, location, job-related skills, experience, and relevant education level or training. We are committed to complying with all applicable federal and state minimum wage requirements where applicable. If applicable, your recruiter can share more about the specific pay range for your preferred location during the hiring process. KLA is proud to be an Equal Opportunity Employer. We will ensure that qualified individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us at ************************** or at *************** to request accommodation. Be aware of potentially fraudulent job postings or suspicious recruiting activity by persons that are currently posing as KLA employees. KLA never asks for any financial compensation to be considered for an interview, to become an employee, or for equipment. Further, KLA does not work with any recruiters or third parties who charge such fees either directly or on behalf of KLA. Please ensure that you have searched KLA's Careers website for legitimate job postings. KLA follows a recruiting process that involves multiple interviews in person or on video conferencing with our hiring managers. If you are concerned that a communication, an interview, an offer of employment, or that an employee is not legitimate, please send an email to ************************** to confirm the person you are communicating with is an employee. We take your privacy very seriously and confidentially handle your information.

KLA is a global leader in diversified electronics for the semiconductor manufacturing ecosystem. Virtually every electronic device in the world is produced using our technologies. No laptop, smartphone, wearable device, voice-controlled gadget, flexible screen, VR device or smart car would have made it into your hands without us. KLA invents systems and solutions for the manufacturing of wafers and reticles, integrated circuits, packaging, printed circuit boards and flat panel displays. The innovative ideas and devices that are advancing humanity all begin with inspiration, research and development. KLA focuses more than average on innovation and we invest 15% of sales back into R&D. Our expert teams of physicists, engineers, data scientists and problem-solvers work together with the world's leading technology providers to accelerate the delivery of tomorrow's electronic devices. Life here is exciting and our teams thrive on tackling really hard problems. There is never a dull moment with us. Group/Division With over 40 years of semiconductor process control experience, chipmakers around the globe rely on KLA to ensure that their fabs ramp next-generation devices to volume production quickly and cost-effectively. Enabling the movement towards advanced chip design, KLA's Global Products Group (GPG), which is responsible for creating all of KLA's metrology and inspection products, is looking for the best and the brightest research scientist, software engineers, application development engineers, and senior product technology process engineers. The Film and Scatterometry Technology (FaST) Division provides industry leading metrology solutions for worldwide semiconductor IC manufacturers. The FaST Division portfolio of metrology products includes hardware and software solutions for optical film thickness, optical critical dimension (CD), composition, and resistivity measurement systems. These products are essential for the IC manufacturers as they provide critical metrology capabilities for the development and implementation of their advanced IC processes. The FaST division is committed to support our customers to achieve performance entitlement of our solution and we effectively partner with our customers from their early research and development phase to the high volume in-line manufacturing implementation specific for their process needs. The division consists of a global team located in US, Israel, China, and India. Job Description/Preferred Qualifications Company Overview Calling the adventurers ready to join a company that's pushing the limits of nanotechnology to keep the digital revolution rolling. At KLA, we're making technology advancements that are bigger and tinier than the world has ever seen. Who are we? We research, develop, and manufacture the world's most advanced inspection and measurement equipment for the semiconductor and nanoelectronics industries. We enable the digital age by pushing the boundaries of technology, creating tools capable of finding defects smaller than a wavelength of visible light. We create smarter processes so that technology leaders can manufacture high-performance chips, the kind in that phone in your pocket, the tablet on your desk and nearly every electronic device you own faster and better. We're passionate about creating solutions that drive progress and help people do what wouldn't be possible without us. The future is calling. Will you answer? Group/Division With over 40 years of semiconductor process control experience, chipmakers around the globe rely on KLA to ensure that their fabs ramp next-generation devices to volume production quickly and cost-effectively. Enabling the movement towards advanced chip design, KLA's Global Products Group (GPG), which is responsible for creating all of KLA's metrology and inspection products, is looking for the best and the brightest research scientist, software engineers, application development engineers, and senior product technology process engineers. The Film and Scatterometry Technology (FaST) Division provides industry leading metrology solutions for worldwide semiconductor IC manufacturers. The FaST Division portfolio of metrology products includes hardware and software solutions for optical film thickness, optical critical dimension (CD), composition, and resistivity measurement systems. These products are essential for the IC manufacturers as they provide critical metrology capabilities for the development and implementation of their advanced IC processes. The FaST division is committed to support our customers to achieve performance entitlement of our solution and we effectively partner with our customers from their early research and development phase to the high volume in-line manufacturing implementation specific for their process needs. The division consists of a global team located in US, Israel, China, and India. Responsibilities Lead medium-sized projects e.g. H2H, PLC, alpha characterization, beta testing, and gap analysis. Create and evaluate characterization and field test plans. Respond to customer requests and perform complex problem diagnosis and problem resolution. Develop and document new applications of existing and pre-release products, including BKMs. Develop written procedures, standards, training material, and other technical documentation. Review and evaluate quality of data in other related technical documents. Layer owner on complex demos. Serve as Applications Representative for PLC projects. Preferred Qualifications Ph.D. degree, Masters with 2-4 years, or Bachelors with 3-5 years experience or equivalent combination of education and experience in engineering applications. Deeper understanding of each of the previous areas, plus: • Thoroughly understands engineering principles and techniques related to project activities. • Show a high degree of proficiency in several other related technical areas. • Ability to recognize system-wide issues and design accordingly. • Strong working knowledge of testing techniques • Strong working knowledge of various applications. • Ability to independently resolve complex problems. • Strong presentation skills. • Strong project management skills. KLA is an Equal Opportunity Employer. Applicants will be considered for employment without regard to age, race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability, or any other characteristics protected by applicable law. Minimum Qualifications Doctorate (Academic) Degree and 0 years related work experience; Master's Level Degree and related work experience of 3 years; Bachelor's Level Degree and related work experience of 5 years Base Pay Range: $97,600.00 - $165,900.00 AnnuallyPrimary Location: USA-OR-Hillsboro-Beaverton-KLAKLA's total rewards package for employees may also include participation in performance incentive programs and eligibility for additional benefits including but not limited to: medical, dental, vision, life, and other voluntary benefits, 401(K) including company matching, employee stock purchase program (ESPP), student debt assistance, tuition reimbursement program, development and career growth opportunities and programs, financial planning benefits, wellness benefits including an employee assistance program (EAP), paid time off and paid company holidays, and family care and bonding leave. Interns are eligible for some of the benefits listed. Our pay ranges are determined by role, level, and location. The range displayed reflects the pay for this position in the primary location identified in this posting. Actual pay depends on several factors, including state minimum pay wage rates, location, job-related skills, experience, and relevant education level or training. We are committed to complying with all applicable federal and state minimum wage requirements where applicable. If applicable, your recruiter can share more about the specific pay range for your preferred location during the hiring process. KLA is proud to be an Equal Opportunity Employer. We will ensure that qualified individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us at ************************** or at *************** to request accommodation. Be aware of potentially fraudulent job postings or suspicious recruiting activity by persons that are currently posing as KLA employees. KLA never asks for any financial compensation to be considered for an interview, to become an employee, or for equipment. Further, KLA does not work with any recruiters or third parties who charge such fees either directly or on behalf of KLA. Please ensure that you have searched KLA's Careers website for legitimate job postings. KLA follows a recruiting process that involves multiple interviews in person or on video conferencing with our hiring managers. If you are concerned that a communication, an interview, an offer of employment, or that an employee is not legitimate, please send an email to ************************** to confirm the person you are communicating with is an employee. We take your privacy very seriously and confidentially handle your information.

Foundry Services** Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. **Position Overview** The Aerospace, Defense & Government (ADG) Memory Design Application Engineer provides specialized technical support to Intel Foundry Services customers on memory compiler generation and integration challenges. This critical role ensures successful customer tape-outs by resolving complex memory IP integration issues, driving quality improvements in memory collaterals, and delivering comprehensive technical guidance on memory design methodologies for advanced semiconductor applications. **Key Responsibilities** **Memory IP Technical Support & Integration** + Provide comprehensive technical support to Intel Foundry Services customers on memory compiler generation and integration issues + Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, Memory IP providers, and EDA vendors on foundational IP integration issue resolution + Drive resolution of customer issues related to memory IP collaterals, ensuring seamless integration and optimal performance **Technical Content Development & Training** + Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams + Drive quality improvements in design kits, Memory IP collaterals, and documentation to remove barriers to successful customer design tape-outs + Develop best practice guidelines for memory integration across advanced process technologies and customer applications **Memory Design Methodology & Problem Solving** + Lead debugging and problem-solving activities in collaborative team environments + Provide technical expertise on memory compiler design, generation, and optimization + Support customers through complex memory design challenges and advanced integration requirements + Drive methodology improvements to enhance memory design productivity and reliability **Customer Engagement & Technical Excellence** + Deliver customer-facing technical support with focus on memory design and integration solutions + Ensure maximum customer satisfaction through expert guidance on memory IP implementation + Support aerospace, defense, and government customers with specialized memory requirements and security considerations **Core Competencies** + Self-driven and results-oriented with capability to effectively manage multiple complex tasks + Effective communicator with strong interpersonal and leadership capabilities, fostering collaboration across cross-functional teams and providing constructive feedback **Qualifications:** The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates **Minimum Qualifications** + US Citizenship required + Ability to obtain a US Government Security Clearance + Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study + 3+ years of experience with Memory design or Memory Compiler development and implementation **Preferred Qualifications:** + Active US Government Security Clearance with a minimum of Secret level + Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study + Proficient in common memory types, including SRAM, Register Files (RF), and ROM, with a solid understanding of CMOS digital circuit design principles + Knowledgeable in both behavioral and physical modeling of memory architectures, supporting accurate simulation and verification + Hands-on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and anti FUSE and MBIST + Experience with IP development is a strong plus + Proficient in scripting languages like Perl/Tcl/Python, and power-aware RTL and UPF flow is a plus + Experience in ASIC or SoC development **What We Offer** + Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications + Direct customer engagement and technical leadership in advanced memory design + Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio + Competitive compensation + Professional development in memory design methodologies and foundry services + Direct impact on national security through advanced memory semiconductor solutions **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Arizona, Phoenix **Additional Locations:** US, California, Santa Clara, US, Oregon, Hillsboro **Business group:** The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

About Intel Foundry Services Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. Position Overview The Aerospace, Defense & Government (ADG) Memory Design Application Engineer provides specialized technical support to Intel Foundry Services customers on memory compiler generation and integration challenges. This critical role ensures successful customer tape-outs by resolving complex memory IP integration issues, driving quality improvements in memory collaterals, and delivering comprehensive technical guidance on memory design methodologies for advanced semiconductor applications. Key Responsibilities Memory IP Technical Support & Integration * Provide comprehensive technical support to Intel Foundry Services customers on memory compiler generation and integration issues * Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, Memory IP providers, and EDA vendors on foundational IP integration issue resolution * Drive resolution of customer issues related to memory IP collaterals, ensuring seamless integration and optimal performance Technical Content Development & Training * Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams * Drive quality improvements in design kits, Memory IP collaterals, and documentation to remove barriers to successful customer design tape-outs * Develop best practice guidelines for memory integration across advanced process technologies and customer applications Memory Design Methodology & Problem Solving * Lead debugging and problem-solving activities in collaborative team environments * Provide technical expertise on memory compiler design, generation, and optimization * Support customers through complex memory design challenges and advanced integration requirements * Drive methodology improvements to enhance memory design productivity and reliability Customer Engagement & Technical Excellence * Deliver customer-facing technical support with focus on memory design and integration solutions * Ensure maximum customer satisfaction through expert guidance on memory IP implementation * Support aerospace, defense, and government customers with specialized memory requirements and security considerations Core Competencies * Self-driven and results-oriented with capability to effectively manage multiple complex tasks * Effective communicator with strong interpersonal and leadership capabilities, fostering collaboration across cross-functional teams and providing constructive feedback Qualifications: The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates Minimum Qualifications * US Citizenship required * Ability to obtain a US Government Security Clearance * Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study * 3+ years of experience with Memory design or Memory Compiler development and implementation Preferred Qualifications: * Active US Government Security Clearance with a minimum of Secret level * Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study * Proficient in common memory types, including SRAM, Register Files (RF), and ROM, with a solid understanding of CMOS digital circuit design principles * Knowledgeable in both behavioral and physical modeling of memory architectures, supporting accurate simulation and verification * Hands-on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and anti FUSE and MBIST * Experience with IP development is a strong plus * Proficient in scripting languages like Perl/Tcl/Python, and power-aware RTL and UPF flow is a plus * Experience in ASIC or SoC development What We Offer * Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications * Direct customer engagement and technical leadership in advanced memory design * Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio * Competitive compensation * Professional development in memory design methodologies and foundry services * Direct impact on national security through advanced memory semiconductor solutions Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

**Do Something Wonderful!** Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel (*************************************** or the links below! + Life at Intel (**************************************************************** + Intel Global Diversity and Inclusion Responsibilities include, but are not limited to: + Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). + Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). + Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). + Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. + Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation. + Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. + Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. + Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high-quality integration of the IP block. + Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. + Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE. **Qualifications:** You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. **Minimum Qualifications:** Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 3+ years of relevant experience - or - Master's degree in the same fields with 2+ years of relevant experience - or - PhD in the same fields with 1+ years of relevant experience Relevant work experience should be of the following: + Experience with DFT Array Test including MBIST or Scan/ATPG or DFT Verification Preferred Qualifications: + Expertise in Tessent DFT tool + Expertise in Primetime especially in DFT constraints + Expertise in Quality checks such as Lint, VCLP, CDC/RDC, LEC, Spyglass DFT **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, California, Santa Clara **Additional Locations:** US, Oregon, Hillsboro, US, Texas, Austin **Business group:** At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below! * Life at Intel * Intel Global Diversity and Inclusion Responsibilities include, but are not limited to: * Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). * Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). * Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). * Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. * Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation. * Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. * Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. * Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high-quality integration of the IP block. * Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. * Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 3+ years of relevant experience * or - Master's degree in the same fields with 2+ years of relevant experience * or - PhD in the same fields with 1+ years of relevant experience Relevant work experience should be of the following: * Experience with DFT Array Test including MBIST or Scan/ATPG or DFT Verification Preferred Qualifications: * Expertise in Tessent DFT tool * Expertise in Primetime especially in DFT constraints * Expertise in Quality checks such as Lint, VCLP, CDC/RDC, LEC, Spyglass DFT Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Oregon, Hillsboro, US, Texas, Austin Business group: At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Intel's Discrete Graphics Engineering (DGE) organization develops cutting-edge discrete graphics products for gaming and AI. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role You will be responsible for designing and/or integrating IP for a discrete graphics SoC. You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation of discrete graphics SoC products, including: + Creating a design to produce key assets that help improve product KPIs for discrete graphics products + Working with SoC Architecture and platform architecture teams to establish silicon requirements + Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule + Creating micro architectural specification document for the design. + Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs. + Driving vendor's methodology to meet world class silicon design standards + Architecting area and power efficient low latency designs with scalabilities and flexibilities + Power and Area efficient RTL logic design and DV support + Running tools to ensure lint-free and CDC/RDC clean design, VCLP + Synthesis and timing constraints + Having achieved multiple tape-outs reaching production with first pass silicon + Ability to drive and improve digital design methodology to achieve high quality first silicon Hands on experience with FPGA emulation, silicon bring-up, characterization and debug + Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule + Strong verbal and written communication skills Good understanding of verilog and system verilog, synthesizable RTL + Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis + Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post silicon power correlation + Background in computer architecture + Bus fabric, including, but not limited to APB/AHB/AXI + Power management with multiple power domains, UPF, Power state tables. + Knowledge of lint tools, CDC and RDC tools, timing constraints, fishtail. + Knowledge of connectivity tools. + Understanding of key SoC design elements, arbiters, async FIFOs, DMAs, basic Controllers. + Comprehension of asynchronous clock crossing means and methodologies + Proven track record of bringing logic designs into high volume production + Ability to work well in a team and be productive under ambitious schedules + Should be self-motivated and well organized **Qualifications:** + BS+5 Years of relevant industry experience **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, California, Santa Clara **Additional Locations:** US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro **Business group:** The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

**Do Something Wonderful!** Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and have a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. **Who We Are** The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers' lives? If so, come join us to do something wonderful. **Who you are** The role's responsibilities include but are not limited to: + Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. + Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. + Conduct verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. + Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. + Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. + Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, lowpower synthesizable CPU. + Optimizes CPU design to improve product level parameters such as power, frequency, and area. + Participates in the development and improvement of physical design methodologies and flow automation. **Qualifications:** Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of relevant industry job experience, internship experience, and/or schoolwork/classes/research. **Minimum qualifications:** + Bachelors' degree in Computer/Electrical Engineering or related field with 8+ years of relevant experience + **-OR-** Master Degree in Computer/Electrical Engineering or related field 6+ years of relevant experience + - **OR-** PhD Degree in Computer/Electrical Engineering or related field 5+ years of relevant experience Must have experience in some or most of the following: + Synthesis, Placement (PnR), Routing, CTS (clocks), PostRoute Optimization, Verification and Sign-off, PrimeTime, Timing ECOs **Preferred qualification** + Strongly prefer individuals who have gone through multiple Tape-in Cycles and contribute as a senior member of the team. + Experience in physical design EDA tools, Perl and Tcl Programming, Low power and high performance design principals, familiarity with Verilog and CPU architecture. **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Texas, Austin **Additional Locations:** US, Oregon, Hillsboro **Business group:** The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

We are seeking a highly skilled Clocking Design Engineer to join our dynamic team. You will be part of the clock team supporting Intel's flagship CPU designs in the most advanced process nodes. In this role, you will be involved in clocking architecture definition, design and implementation of custom clock global network, development of clock tree synthesis flow, as well as custom clock circuit design and clock library cell design. This is a cross-functional role that requires interfacing and collaborating with other teams such as architecture, physical design, full chip integration, RTL, circuits, validation, design automation team and EDA vendors, in a high-paced atmosphere. **Key Responsibilities:** + Implement custom clock distribution network for high frequency flagship CPU designs + Develop clock tree synthesis flow and deliver custom clock solutions for high frequency flagship CPU designs + Design custom circuits and library cells related to clock distribution **Qualifications:** You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. **Minimum Qualifications:** + Bachelor´s degree in electrical engineering, computer engineering related STEM field and 4+ years of experience and/or Master´s degree and 3+ years of experience and/or PhD and 2+ years of experience, during which the candidate has demonstrated experience in: + Physical design and advanced process technologies and circuit implementation + Static timing analysis, clock tree synthesis, and clock-related timing parameters + Use of industry-standard scripting and automation within EDA tool flows **Preferred Qualifications:** + 3+ years of experience in: + Backend design and/or integration on leading edge process nodes + High frequency clock distribution design and implementation, custom circuits and clock tree synthesis **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Texas, Austin **Additional Locations:** US, Oregon, Hillsboro **Business group:** Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Do Something Wonderful! Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and have a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Who We Are The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers' lives? If so, come join us to do something wonderful. Who you are The role's responsibilities include but are not limited to: * Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. * Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. * Conduct verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. * Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. * Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. * Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, lowpower synthesizable CPU. * Optimizes CPU design to improve product level parameters such as power, frequency, and area. * Participates in the development and improvement of physical design methodologies and flow automation. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of relevant industry job experience, internship experience, and/or schoolwork/classes/research. Minimum qualifications: * Bachelors' degree in Computer/Electrical Engineering or related field with 8+ years of relevant experience * -OR- Master Degree in Computer/Electrical Engineering or related field 6+ years of relevant experience * -OR- PhD Degree in Computer/Electrical Engineering or related field 5+ years of relevant experience Must have experience in some or most of the following: * Synthesis, Placement (PnR), Routing, CTS (clocks), PostRoute Optimization, Verification and Sign-off, PrimeTime, Timing ECOs Preferred qualification * Strongly prefer individuals who have gone through multiple Tape-in Cycles and contribute as a senior member of the team. * Experience in physical design EDA tools, Perl and Tcl Programming, Low power and high performance design principals, familiarity with Verilog and CPU architecture. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: US, Oregon, Hillsboro Business group: The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

We are seeking a highly skilled Clocking Design Engineer to join our dynamic team. You will be part of the clock team supporting Intel's flagship CPU designs in the most advanced process nodes. In this role, you will be involved in clocking architecture definition, design and implementation of custom clock global network, development of clock tree synthesis flow, as well as custom clock circuit design and clock library cell design. This is a cross-functional role that requires interfacing and collaborating with other teams such as architecture, physical design, full chip integration, RTL, circuits, validation, design automation team and EDA vendors, in a high-paced atmosphere. Key Responsibilities: * Implement custom clock distribution network for high frequency flagship CPU designs * Develop clock tree synthesis flow and deliver custom clock solutions for high frequency flagship CPU designs * Design custom circuits and library cells related to clock distribution Qualifications: You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: * Bachelor´s degree in electrical engineering, computer engineering related STEM field and 4+ years of experience and/or Master´s degree and 3+ years of experience and/or PhD and 2+ years of experience, during which the candidate has demonstrated experience in: * Physical design and advanced process technologies and circuit implementation * Static timing analysis, clock tree synthesis, and clock-related timing parameters * Use of industry-standard scripting and automation within EDA tool flows Preferred Qualifications: * 3+ years of experience in: * Backend design and/or integration on leading edge process nodes * High frequency clock distribution design and implementation, custom circuits and clock tree synthesis Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: US, Oregon, Hillsboro Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Intel's Discrete Graphics Engineering (DGE) organization develops cutting-edge discrete graphics products for gaming and AI. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role You will be responsible for designing and/or integrating IP for a discrete graphics SoC. You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation of discrete graphics SoC products, including: * Creating a design to produce key assets that help improve product KPIs for discrete graphics products * Working with SoC Architecture and platform architecture teams to establish silicon requirements * Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule * Creating micro architectural specification document for the design. * Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs. * Driving vendor's methodology to meet world class silicon design standards * Architecting area and power efficient low latency designs with scalabilities and flexibilities * Power and Area efficient RTL logic design and DV support * Running tools to ensure lint-free and CDC/RDC clean design, VCLP * Synthesis and timing constraints * Having achieved multiple tape-outs reaching production with first pass silicon * Ability to drive and improve digital design methodology to achieve high quality first silicon Hands on experience with FPGA emulation, silicon bring-up, characterization and debug * Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule * Strong verbal and written communication skills Good understanding of verilog and system verilog, synthesizable RTL * Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis * Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post silicon power correlation * Background in computer architecture * Bus fabric, including, but not limited to APB/AHB/AXI * Power management with multiple power domains, UPF, Power state tables. * Knowledge of lint tools, CDC and RDC tools, timing constraints, fishtail. * Knowledge of connectivity tools. * Understanding of key SoC design elements, arbiters, async FIFOs, DMAs, basic Controllers. * Comprehension of asynchronous clock crossing means and methodologies * Proven track record of bringing logic designs into high volume production * Ability to work well in a team and be productive under ambitious schedules * Should be self-motivated and well organized Qualifications: * BS+5 Years of relevant industry experience Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Foundry Services** Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. **Position Overview** The Aerospace, Defense & Government (ADG) IP Enablement Application Engineer provides comprehensive technical support to Intel Foundry Services customers on IP integration challenges. This dynamic role requires a versatile engineer who engages with IP design teams and internal/external customers across all phases of IP development - from architecture through post-silicon validation and debug. The position embodies customer obsession by quickly resolving issues and providing hands-on debug across all design domains. **Key Responsibilities** **IP Integration & Customer Support** + Provide comprehensive technical support to Intel Foundry Services customers on IP integration issues, working independently with design teams and customers to solve complex challenges remotely or onsite + Fully own assigned IPs and work with internal and external customers to help them integrate Intel IPs into SoCs, providing expert technical support throughout the integration process + Drive resolution of customer issues related to IP collaterals generation, logic design verification, IP release, and integration in SoC environments **Cross-Functional Collaboration & IP Development** + Work with cross-functional teams to develop SoC and IP integration methodologies and best practices + Engage with IP development teams to ensure all IP collaterals are generated and provided according to customer requirements and industry standards + Collaborate with internal teams across Intel and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on foundational IP integration issue resolution **Customer Requirements & Training** + Engage in upfront identification and documentation of customer requirements, working with IP design teams to disposition and address requests + Prepare comprehensive customer training materials and provide training on IP architecture, specifications, and fuse/register settings to enable effective debug + Create application notes, documentation, and deliver technical training presentations to customers and internal teams **Quality & Process Improvement** + Drive quality improvements in design kits and documentation, assisting in removing barriers to successful customer design tape-outs + Support debugging and problem-solving activities in collaborative team environments + Contribute to methodology improvements that enhance IP integration productivity and customer satisfaction **Core Competencies** + Strong technical problem-solving and debugging capabilities + Ability to work independently and manage customer relationships effectively + Excellent communication skills for technical training and customer support + Willingness to travel to customer sites as required **Qualifications:** The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates **Minimum Qualifications** + US Citizenship required + Ability to obtain a US Government Security Clearance + Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study + 2+ years of experience in SOC IP Integration + 3+ years of combined experience in RTL design and DFT using Verilog/System Verilog + Experience in ASIC or SoC development **Preferred Qualifications:** + Active US Government Security Clearance with a minimum of Secret level + Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study + Experience with one or more industry standard IO interfaces including (ADPLL, GPIO, Digital Thermal Sensors, DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc.) + Experience with VCS, Verdi, Spyglass or equivalent tools + Experience with IP integration and design flow challenges within the context of subsystems and SOCs + Experience with IP development + Experience in scripting languages like such as Perl/Tcl/ and Python **What We Offer** + Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications + Direct customer engagement and technical leadership in advanced memory design + Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio + Competitive compensation + Professional development in memory design methodologies and foundry services + Direct impact on national security through advanced memory semiconductor solutions **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Arizona, Phoenix **Additional Locations:** US, California, Santa Clara, US, Oregon, Hillsboro **Business group:** The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Foundry Services** Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. **Position Overview** We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role supports Aerospace, Defense, and Government (ADG) customers in achieving successful tape-outs while ensuring the highest quality standards through comprehensive DFT solutions and customer engagement. **Key Responsibilities** **Customer Technical Support & Collaboration** + Provide comprehensive DFT tool/flow/methodology support to address customer issues and challenges, ensuring successful tape-outs and maximum customer satisfaction + Work closely with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors to resolve complex technical issues + Deliver customer-facing technical support and guidance on DFT implementation strategies **DFT Methodology & Quality Leadership** + Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations + Collaborate with RTL and Hard IP designers on DFT/DFM implementation methodology and work with physical designers on DFT/DFM physical implementation, validation, and timing signoff + Develop and optimize DFT insertion flows for advanced CMOS processes and multi-die designs **Technical Content Development & Training** + Develop application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams + Create best practice guidelines and methodology documentation for DFT implementation across various design complexities + Support knowledge transfer and capability building for both internal teams and customer organizations **Essential Skills & Attributes** + Customer-Focused: Strong customer-oriented attitude and mindset with commitment to customer success + Self-Motivated: Self-driven and results-oriented with ability to manage multiple complex tasks effectively + Collaborative: Excellent teamwork skills to drive innovative solutions for customer design implementation challenges + Analytical: Strong analytical problem-solving capabilities for complex DFT challenges + Communication: Effective communication skills with experience in collaboration, active listening, and providing constructive technical feedback **Qualifications:** The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. **Minimum Qualifications** + US Citizenship required + Ability to obtain US Government Security Clearance + Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field + 3+ years of experience with advanced CMOS processes (22nm and below) + 3+ years of combined experience in the following: implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at both ASIC design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC level + 2+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting) **Preferred Qualifications** + Active US Government Security Clearance with a minimum of Secret Level. + Post-graduate degree in Electrical/Computer Engineering or STEM-related field + Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability + Proficiency with major EDA tools for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation and ATPG validation for single die and multi-die designs + Experience building/developing quality DFT/DFX insertion flow and ATPG validation flow + Experience providing technical direction to engineering teams and customer support + Customer-facing experience in technical roles + Experience with state-of-the-art process technology (7nm and below) and PDK-based technology evaluation **What We Offer** + Opportunity to work with cutting-edge DFT technologies for aerospace, defense, and government applications + Direct customer engagement and technical leadership in advanced semiconductor design + Access to Intel's most advanced foundry technologies and comprehensive EDA tool suites + Competitive compensation + Professional development in DFT methodologies and foundry services + Direct impact on national security through advanced semiconductor technology solutions **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Arizona, Phoenix **Additional Locations:** US, California, Santa Clara, US, Oregon, Hillsboro **Business group:** The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

About Intel Foundry Services Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. Position Overview The Aerospace, Defense & Government (ADG) IP Enablement Application Engineer provides comprehensive technical support to Intel Foundry Services customers on IP integration challenges. This dynamic role requires a versatile engineer who engages with IP design teams and internal/external customers across all phases of IP development - from architecture through post-silicon validation and debug. The position embodies customer obsession by quickly resolving issues and providing hands-on debug across all design domains. Key Responsibilities IP Integration & Customer Support * Provide comprehensive technical support to Intel Foundry Services customers on IP integration issues, working independently with design teams and customers to solve complex challenges remotely or onsite * Fully own assigned IPs and work with internal and external customers to help them integrate Intel IPs into SoCs, providing expert technical support throughout the integration process * Drive resolution of customer issues related to IP collaterals generation, logic design verification, IP release, and integration in SoC environments Cross-Functional Collaboration & IP Development * Work with cross-functional teams to develop SoC and IP integration methodologies and best practices * Engage with IP development teams to ensure all IP collaterals are generated and provided according to customer requirements and industry standards * Collaborate with internal teams across Intel and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on foundational IP integration issue resolution Customer Requirements & Training * Engage in upfront identification and documentation of customer requirements, working with IP design teams to disposition and address requests * Prepare comprehensive customer training materials and provide training on IP architecture, specifications, and fuse/register settings to enable effective debug * Create application notes, documentation, and deliver technical training presentations to customers and internal teams Quality & Process Improvement * Drive quality improvements in design kits and documentation, assisting in removing barriers to successful customer design tape-outs * Support debugging and problem-solving activities in collaborative team environments * Contribute to methodology improvements that enhance IP integration productivity and customer satisfaction Core Competencies * Strong technical problem-solving and debugging capabilities * Ability to work independently and manage customer relationships effectively * Excellent communication skills for technical training and customer support * Willingness to travel to customer sites as required Qualifications: The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates Minimum Qualifications * US Citizenship required * Ability to obtain a US Government Security Clearance * Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study * 2+ years of experience in SOC IP Integration * 3+ years of combined experience in RTL design and DFT using Verilog/System Verilog * Experience in ASIC or SoC development Preferred Qualifications: * Active US Government Security Clearance with a minimum of Secret level * Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study * Experience with one or more industry standard IO interfaces including (ADPLL, GPIO, Digital Thermal Sensors, DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc.) * Experience with VCS, Verdi, Spyglass or equivalent tools * Experience with IP integration and design flow challenges within the context of subsystems and SOCs * Experience with IP development * Experience in scripting languages like such as Perl/Tcl/ and Python What We Offer * Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications * Direct customer engagement and technical leadership in advanced memory design * Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio * Competitive compensation * Professional development in memory design methodologies and foundry services * Direct impact on national security through advanced memory semiconductor solutions Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Developing physics-based models for Thermal/CFD/Chemistry applications for components in semiconductor capital equipment industry. Experience in commercial software like ANSYS Fluent, Star CCM+, or COMSOL, etc. , is highly desirable. Strong ability in closed-form solutions and analytical methods development and understanding fundamentals in fluid mechanics. Utilizing DOE, Optimization, and statistical methods and data driven modeling to correlate Simulation data to experimental data. Predict, measure, and analyze the experimental data for uncertainty Quantification & propagation, sensitivity analysis, statistical inference for model calibration, decision making under uncertainty. Multi-scale modeling from nano, meso to macro levels Provide written reports and oral presentation of results to design teams and management. Work directly with mechanical, electrical, process and software engineers to define design requirements, goals and objectives of design, CIP, testing and simulation plans. Strong written and oral communication. Self-starter to start own initiatives and projects for continuous improvement in capabilities and design. Put your running shoes on: In this job you'll work in a highly dynamic and rapidly changing environment within a team of interdisciplinary experts driving to solutions to the most challenging business needs. PhD in Mechanical Engineering or closely related field with strong emphasis in Computational Fluid Dynamics, Heat transfer, Chemistry, or related fields with >6 years of experience in a related industry, e. g. , semiconductor, gas turbine, aerospace, automotive, etc. Ability to work with a team to drive product development and design decisions. Propose design concepts and own decisions. Strong ability and understanding of AI/ML concepts and hybrid physics-based AI/ML modeling software. Building and maintaining codes of AI/ML models with either simulation or test data. Experience with machine learning algorithms and tools (e. g. , TensorFlow, PyTorch, Scikit Learn etc. ) and deep learning. Coding ability to supplement commercial software for specific applications as needs arise. Knowledge of chemistry, semiconductor metrology methods, and hardware designs in a vacuum environment is also a plus. General understanding of uncertainty quantification, Bayesian optimization and probabilistic machine learning is required. Ability to effectively communicate and build relationships to interact, inform, influence, and communicate with key stakeholders at all levels across the company. Strong critical thinking skills demonstrated through problem-solving, attention to detail and innovation. Strong analytical skills demonstrated through First Principles Thinking, statistical Analysis and Physics-based Insights

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned ASIC Design Engineer with a robust background in design automation and a keen understanding of the intricate challenges in advanced semiconductor development. Your commitment to excellence is matched by your passion for leveraging technology to solve real-world problems, and you thrive in environments that encourage collaboration, continuous learning, and innovation. With a strong foundation in electronic engineering and advanced programming skills-especially in Python, Perl, and TCL-you are adept at architecting resilient solutions within UNIX/Linux environments. Your experience extends to Agile software methodologies, enabling you to adapt quickly to evolving project requirements and deliver high-quality results. Your curiosity propels you to stay abreast of the latest tools and AI frameworks, and you excel at integrating emerging technologies into complex workflows. You have a proven history of leading and executing multifaceted projects, demonstrating initiative and fostering a culture of mentorship and knowledge sharing. Your analytical mindset, clear communication, and adaptability make you a trusted advisor and resource within teams. Above all, you are driven by the desire to make a tangible impact in the world of chip design and automation, eager to contribute to innovative projects that set new industry standards. What You'll Be Doing: * Developing and applying Agile software engineering methods, theories, and research techniques to solve complex technical problems within the ASIC design automation domain. * Planning, executing, and overseeing technical projects related to the architecture and development of advanced application software for design automation. * Defining and selecting innovative approaches for implementing software engineering applications and ASIC design specifications. * Preparing detailed design specifications, conducting comprehensive technical investigations, and presenting findings to stakeholders. * Collaborating closely with team members on task-oriented projects and cross-functional initiatives to accelerate design workflows. * Networking with senior internal and external experts to share knowledge and best practices in design automation and software development. * Mentoring and guiding junior peers, fostering a collaborative and inclusive environment that encourages continuous learning. The Impact You Will Have: * Accelerating and automating design activities across R&D and circuit design teams, improving overall productivity and innovation velocity. * Enhancing the efficiency and effectiveness of design communities through the deployment of advanced software tools and automation frameworks. * Driving innovation in chip design and verification by implementing state-of-the-art solutions that push the boundaries of what's possible. * Contributing directly to the development and integration of high-performance silicon chips and software content used in leading-edge applications. * Facilitating seamless integration of IP across various projects, ensuring robust and scalable design automation tools are in place. * Enabling teams to deliver reliable, high-quality results by establishing best practices in design automation and software engineering. What You'll Need: * MS or PhD in Computer Science or Electrical Engineering with at least 10+ years of direct industry experience. * Expertise in programming languages such as Python, Perl, and TCL, with a demonstrated ability to develop robust automation solutions. * Hands-on experience with Custom Compiler/Virtuoso, circuit and layout automation, and version control systems such as Git and Perforce. * Strong familiarity with test-driven development, unit testing, and functional testing methodologies. * Advanced proficiency in UNIX/Linux environments, with the ability to optimize workflows and troubleshoot complex issues. * Working knowledge of a major AI framework or demonstrated experience using AI to accelerate software development processes. Who You Are: * A proactive learner with a keen interest in exploring new technologies and methodologies. * An excellent problem solver with strong analytical and investigative skills. * A collaborative team player who builds productive working relationships and communicates effectively. * A self-starter capable of executing projects from start to completion with minimal supervision. * A sophisticated professional with advanced knowledge and wide-ranging experience in design automation and software engineering. The Team You'll Be A Part Of: You will join the Design Automation Team, which provides the design community with software tools to accelerate and automate design activities. This team is integral to our R&D and circuit design efforts, working on cutting-edge projects that push the boundaries of technology. You'll collaborate with leading experts, contribute to impactful solutions, and be part of a culture that values innovation, diversity, and continuous improvement. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S. Apply Now Save