Mechanical engineer jobs in Hollister, CA - 1,704 jobs

A leading semiconductor company in San Jose is seeking a Staff Power Module Design Engineer. You'll develop innovative power module products and collaborate with industry experts. The role requires a strong educational background in Power Electronics and significant experience in switching power converter design. This position offers competitive pay within a vibrant engineering team, fostering professional growth and mentorship opportunities. #J-18808-Ljbffr

A leading semiconductor company in Santa Clara is looking for an FPGA Hardware Validation Engineer to create and implement validation platforms while collaborating with design and firmware teams. Candidates should have extensive experience in FPGA prototyping and strong problem-solving skills, along with a BS in Electrical or Computer Engineering. The role involves complex architecture designs and debugging hardware/firmware issues. Join a culture of innovation driven by collaboration and inclusivity. #J-18808-Ljbffr

A leading technology company is seeking a Senior Generative AI Software Engineer to drive the evolution of cutting-edge AI models and infrastructure. You will refactor research code, build model-serving endpoints, and ensure code quality across teams. Candidates should be proficient in Python and PyTorch with over 10 years of experience. This position offers competitive salary ranges between $224,000 and $425,500 depending on level and experience. #J-18808-Ljbffr

Physical Design Engineer Job at Apple, Cupertino, CAJob Description Physical Design Engineer Department: Hardware Imagine what you can do here. Apple is a place where extraordinary people gather to do their best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Description Apple Inc. has the following available in Cupertino, California, and various unanticipated locations throughout the USA. Responsible for physical design and implementation of partitions. Build partition architecture and drive physical aspects early in the design cycle. Physically implement design partitions (from netlist to tape-out) for a highly complex System-on-Chip (SoC) utilizing state-of-the-art process technology. Work on partition-level place and route (P&R) implementation, including floor planning, clock and power distribution, timing closure, physical and electrical verification. Complete netlist to GDSII implementation for partitions meeting schedule and design goals. Oversee timing, physical, and electrical verification, and drive the signoff closure for the partitions. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. The base pay range for this role is between $151,091 - $214,500/year, depending on skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees have the opportunity to participate in Apple's stock programs, receive benefits including medical and dental coverage, retirement benefits, discounts, free services, educational reimbursement, and potential bonuses or relocation assistance. Learn more about Apple Benefits. Minimum Qualifications Master's degree or foreign equivalent in Electrical Engineering or related field. 2 years of relevant experience. 1 year of experience with each of the following: Encounter Design System tool, QRC, Calibre, Voltus, Primetime. Preferred Qualifications N/A Apple is an equal opportunity employer committed to inclusion and diversity. We promote equal opportunity for all applicants regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics. Note: Apple benefits, compensation, and employee stock programs are subject to eligibility and other terms. This job posting appears to be active and does not indicate it is expired. #J-18808-Ljbffr

Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams Chip/Block Level Floorplanning and pin assignment Review top-level/block-level clock specifications for completeness and feasibility Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing) Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification) Presentations and Customer Interaction in customer meetings Necessary Qualifications: BSEE, with 9+ years of experience or equivalent experience. MSEE preferred. Experience in ASIC Physical Design; Experience in an SoC product development organization with tapeouts at 28nm/16nm design nodes. Hands-on Experience with implementation EDA tools like ICC2/Innovus. Scripting (Perl/Tcl/Python) is required. Good understanding of ASIC frontend design. Experience in both Flat and Hierarchical layouts. Strong problem‑solving skills and ability to analyze and resolve physical design issues related to library, timing constraints or CAD tools is required. Experience with power analysis and IR‑drop tools (primepower/Redhawk) and Static Timing Analysis (Primetime). Experience with Physical Verification and fix PV errors in layout. Expert handling of Verilog HDL based Netlists, Physical design libraries. Team player with good interpersonal and communication skills; ability to explain processes and answer customer questions during meetings. Compensation: $190,000.00 - $200,000.00 per year MAKING THE INDUSTRY'S BEST MATCHES DBSI Services is widely recognized as one of the industry's fastest growing staffing agencies. Thanks to our longstanding experience in various industries, we have the capacity to build meaningful, long‑lasting relationships with all our clients. Our success is a result of our commitment to the best people, the best solutions and the best results. Our Story: Founded in 1995 Privately Owned Corporation Managing Partner Business Model Headquartered in New Jersey US Based Engineers Only Methodology and Process Driven Top performing engineers are the foundation of our business. Our priority is building strong relationships with each employment candidate we work with. You can trust our professional recruiters to invest the time required to fully understand your skills, explore your professional goals and help you find the right career opportunities. #J-18808-Ljbffr

Altera .# **Job Details:**### ## **Job Description:****About the Role:**As a Physical Design Engineer at Altera, you will play a critical role in the backend implementation flow - from RTL/netlist through GDSII/tape-out for FPGA/SoC devices. You will collaborate with architecture, logic design, DFT, CAD/EDA, and manufacturing teams to achieve performance, power, and area (PPA) goals, with a particular emphasis on programmable logic structures, block and full-chip integration, and the unique demands of FPGA technologies (e.g., configurable logic blocks, routing fabrics, I/O rings, on-chip power domains).**Key Responsibilities:*** Execute physical design implementation tasks (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist to GDSII.* Apply PPA optimization techniques (performance/timing closure, power reduction, area efficiency) across block-level and full-chip hierarchies.* Collaborate with front-end design, architecture, and CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets, and DFT insertions are met.* Develop and enhance physical design flows, methodologies, scripts, and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR, and reduce manual intervention.* Participate in timing, power, EM/IR integrity, signal/power noise, and DRC/LVS/ERC verification for sign-off readiness.* Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization.* Debug physical design issues and interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.**$127,400 - $184,400 USD**We use artificial intelligence to screen, assess, or select applicants for the position.### ## **Qualifications:****Minimum Qualifications:**Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 6+ years of experience in:* Hands-on digital/SoC physical design (synthesis through P&R and sign-off).* Industry-standard EDA tools (e.g., Synopsys IC Compiler/Fusion, Cadence Innovus/Encounter, PrimeTime, STAR-RCX, Calibre) for high-speed digital ASIC/SoC implementation.* Scripting/programming (TCL, Python, Perl, shell) for flow automation and productivity enhancement.* Physical design flow: floorplanning, CTS, placement, routing, power domain gating, clock domain crossing, multi-power domain design, timing closure, ECOs, and DRC/LVS/DFM resolution.* Power/IR analysis, signal/power integrity reporting, and corrective action planning.* Interfacing with front-end teams (RTL, architecture), CAD/EDA tool teams, and manufacturing/packaging teams.**Preferred Qualifications:*** Experience with advanced process nodes (7nm, 5nm or smaller) or FPGA/programmable logic device flows.* Familiarity with FPGA architecture: routing fabrics, programmable logic blocks (PLBs), on-chip networks, I/O rings, static/dynamic reconfiguration.* Expertise in low-power design methodologies, power grid design, power gating, multi-voltage domain implementation, and power sign-off flows.* Prior exposure to full-chip integration flows (block-to-chip convergence) and high-frequency (1 GHz+) timing closure.* Experience in high-volume manufacturing environments, including yield and DFM/DFY considerations.* Experience mentoring or leading small physical design sub-teams or owning major P&R blocks.### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr

A leading robotics company is seeking a Senior Platform Software Engineer in San Jose, CA, to develop cutting-edge vehicle software for autonomy in agriculture and off-road environments. This position offers a salary range of $140,000 - $200,000 per year. The ideal candidate will have extensive experience in C++, Python, and ROS 2, alongside a strong background in headless Linux systems. This high-impact role involves creating a robust robotic application and optimizing performance for embedded environments. #J-18808-Ljbffr

About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical designs, and will help Etched as we work to improve iteration speed on physical design. Representative projects Supervise the outsourcing of physical design to a 3rd party service Deeply understand what is involved in physical design Running Physical Design flows to close blocks, support ASIC infrastructure, automate Physical Design flows, improve CAD infrastructure Drive dashboards that show the convergence of projects related to Physical Design Optimize tool flows, working with EDA vendors to incorporate the latest features Accountable for block level closure Requirements 2+ years of previous experience with PD Tools, flow, and design methodology from RTL synthesis to GDSII sign-off Experience with back-end design and timing closure on 3nm-7nm Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis Deeply creative and able to think from first principles Desired qualifications: Familiarity with transformer models and machine learning. Familiarity with Cadence or Synopsys automated RTL-to-GDSII flows Ability to program with Python or another scripting language. We encourage you to apply even if you do not believe you meet every single qualification. Benefits: Full medical, dental, and vision packages, with generous premium coverage Housing subsidy of $2,000/month for those living within walking distance of the office Daily lunch and dinner in our office Relocation support for those moving to West San Jose Compensation Range $150,000 - $275,000 How we're different: Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. #J-18808-Ljbffr

A global technology company is looking for a seasoned software engineer to enhance AI capabilities within their observability platform. Candidates should have a strong background in AI/ML systems, cloud computing, and robust technical leadership. This role is pivotal in driving innovation in data analysis and delivering scalable solutions. The ideal candidate will thrive in an agile environment and provide mentorship to junior engineers. Enjoy competitive salaries and benefits while contributing to impactful technology solutions. #J-18808-Ljbffr

Reports to: Managing Principle Mechanical Engineer, R&D Workplace Type: Hybrid, on-site in Santa Cruz an average of 4-days per week Capstan Medical:Creating a new standard for minimally invasive structural heart treatment Who we are: At Capstan Medical, we're driven by an unwavering commitment to transforming the treatment of heart valve disease. By merging surgical robotics with catheter-based technology and next generation implants, we've pioneered a patient-optimized approach to repair and replace heart valves. Our innovative technology offers a significantly less invasive alternative to traditional open-heart surgery while ensuring precise and reliable placement of the heart valve implant. With these advancements, we may be able to provide patients with a solution to their heart valve disease while significantly reducing recovery time and minimizing the risk of complications. With a dedicated team of heart valve device experts and robotics engineers, we are fully committed to developing a comprehensive and transformative solution that will positively impact the lives of individuals affected by this condition. Capstan Medical is uniquely positioned in Santa Cruz. This gives us access to the amazing technical talent of the Bay Area, but in an environment that we feel is conducive to doing our best creative work. Our office is adjacent to large tracts of open space with bicycle trails straight from the office doors offering access to the hills and beaches of Wilder Ranch State Park for road/mountain bicycle riding, hiking, and surfing. Come join us and become part of a team revolutionizing heart valve treatment! The Opportunity: We are building a novel medical robotic application, bringing together an exciting set of hardware and software into an elegant product. We are looking for someone who can take a mechanical system of the robot design from initial concept all the way to product. What You'll Do: Collaborate with Manufacturing and Clinical teams on designs, incorporating this input into quick and effective design iterations. Lead and set direction for system and subsystem architectures and mechanical design efforts while owning cross-functional mechanical deliverables and technical strategy Participate in building and bringing up prototype robotic systems and support all things mechanical in their pre-clinical lab use. Lead alignment of complex technical topics and hardware architecture across the Mechanical Engineering team and broadly across the R&D organization and Capstan. Document and communicate learnings on design manufacturability and reliability to the broader hardware team, mentoring others in best practices and scalable design approaches Document and communicate your work through design reviews and as appropriate released documents as part of the product development process Identify gaps and pitch in as needed to ensure that the team meets their goals and objectives, driving alignment across teams when priorities conflict Strengthen the team by providing leadership and mentorship on best practices and design strategies as they grow in their abilities to develop performant, scalable, and elegant designs. Be a valuable partner with feedback and collaboration in brainstorming and design reviews. What You'll Need: BS in Mechanical Engineering or related engineering discipline, or equivalent work experience Expecting 12+ years of relevant experience (medical device experience preferred) Comfort working with high levels of ambiguity and an ability to convert that into tangible outcomes Experience with designing, manufacturing transfer, and shipping of medical device capital equipment or equivalent complexity systems Deep expertise in areas particular to robotic system design: kinematics, mechanisms, bearings, gears, sensors, actuators. Experience with medical device (or equivalent) development process, design control, design verification, and regulatory processes Ability to work in a hybrid work environment, working onsite in Santa Cruz on average 4 days a week Ways To Stand Out: Experience with the full commercial lifecycle from concept through reacting to and addressing field issues with your designs. Skills with Python or Matlab for data analysis, simulation, and interacting with robotic equipment. Excessive nerdiness about manufacturing, mechanisms, robots, or any other adjacencies. Leadership experience. While this role is as an individual contributor, it is a position of significant technical and thought leadership within the company. Why Join Us: We offer a fun, fast-paced, collaborative environment where you will be working on transformational technologies in the cardiac healthcare space. We offer outstanding benefits with medical, dental, and vision covered at 100% for you and your family, as well as flex time off. We thrive in our work-hard, play-hard environment. Bring your bike or running shoes if you'd like or just be ready to enjoy a fun office outing. We enjoy time inside the office and out! We are an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, sex, sexual orientation, gender identity, veteran status, and disability, or other legally protected status. #J-18808-Ljbffr

Cupertino, California, United States Hardware At Apple we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. In this role, we will be at the center of a PHY design effort working with architecture, CAD, timing, and logic design teams, with a critical impact on delivering outstanding PHY designs. You will be required to do physical designs of outstanding PHY design. Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block/chip level static timing constraints. Build full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration. Minimum Qualifications Bachelors of Science in Electrical Engineering and 3+ years experience preferred. Preferred Qualifications The ideal candidate will have deep design experience in high PHY and/or SOC designs Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route Experience in developing and implementing Power-grid and Clock specifications Strong understanding of all aspects of Physical construction, Integration and Physical Verification Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard Physical Design & Synthesis tools Deep Understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $147,400 and $272,100, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . #J-18808-Ljbffr

A global semiconductor company in San Jose is seeking a Principal Power Module Design Engineer. This role involves new product development in power electronics, requiring at least a master's or Ph.D. in Power Electronics and 5+ years of experience in related design. Applicants should possess strong skills in switching power converter design and analog circuit design. The position offers competitive compensation, a collaborative environment, and opportunities for professional growth. #J-18808-Ljbffr

A leading technology firm in Santa Clara is seeking a Robotics Deep Learning Expert to push the boundaries of robotics. You will work on imbuing humanoid robots with advanced capabilities, requiring strong skills in algorithm development and deep learning frameworks. The salary range is competitive, reflecting your experience and position level, and additional benefits and equity are offered. Join a team that thrives on creativity and challenge. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE We are seeking a Senior Member of Technical Staff (SMTS) SoC Architect to join our SoC Architecture team. In this role, you will define and drive architecture for critical SoC functions across roadmap and custom devices. You will focus on chip pervasive components, while ensuring seamless integration with processor subsystems, interconnect, AI accelerators, and memory systems. THE PERSON You are passionate about complex SoC architecture and thrive in cross-functional environments. You have deep technical expertise, strong analytical skills, and the ability to balance performance, power, and area trade-offs. You communicate effectively across teams and are comfortable influencing architecture decisions for next-generation silicon. KEY RESPONSIBILITIES Define and develop SoC architecture for CPF components, including Analog IPs, clocking/reset, and silicon monitors. Collaborate with processor, interconnect, AI, and memory subsystem architects to ensure cohesive system-level design. Specify architecture requirements, conduct early-stage analysis, and create detailed specifications. Drive PPA optimization and ensure scalability across roadmap and custom devices. Partner with design, verification, and physical implementation teams to ensure functional correctness and timing closure. Analyze trade-offs for performance, power, reliability, and manufacturability. Influence strategies for security, safety, and reliability across CPF domains. Strong communication and leadership skills to influence cross-functional teams. PREFERRED EXPERIENCE Strong background in SoC architecture, including processor subsystems, interconnect, memory systems, and AI accelerators. Expertise in Analog IPs (IOs, PLLs, eFuses, monitors), clocking/reset architecture, and silicon lifecycle management. Familiarity with SoC on-chip protocols (e.g., AXI) and system-level QoS. Experience with low-power design techniques, boot/reset flows, and power management. Knowledge of design methodologies, advanced process technologies, and associated challenges. Proficiency in modeling and automation using Python, SystemC, or similar languages. ACADEMIC & EXPERIENCE REQUIREMENTS BS or MS or PhD in Electrical/Computer Engineering or related field. Proven track record in delivering architecture for high-performance, low-power SoCs. LOCATION: San Jose, California Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

Altera .# **Job Details:**### ## **Job Description:****About the Role:**For decades, Altera has been at the forefront of programmable logic technology. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries.Join us in our journey to becoming the world's #1 FPGA company!Altera is seeking a **Senior Design Automation Engineer** to join our Design Methodology Automation and Infrastructure Team.The Design Methodology Automation and Infrastructure Team is responsible for building and maintaining the core automation infrastructure that supports Altera's FPGA design flows-from RTL to GDSII. In this senior role, you will drive the architecture, development, and optimization of highly automated, reliable, and scalable flow systems that enhance design productivity and accelerate development cycles for next-generation FPGA products. You will influence technical direction, mentor junior engineers, and collaborate closely with cross-functional teams to deliver world-class automation solutions.**Key Responsibilities:*** Architect next-generation unified FPGA/SoC design methodologies spanning Front-End, handoff to Backend, Design Verification, Design-For-Test (DFT), Design Data Management/Release flows, and FPGA-specific flows such as Design Intent and Configuration Management.* Develop and integrate state-of-the-art EDA solutions, including ML/AI-enhanced tools, flows, and methodologies-sourced externally or developed internally-to create sustainable, scalable automation solutions for multiple chip design programs.* Collaborate with design automation technical leads, design domain leads, and domain managers to define and drive new design automation architectures from concept through full production deployment across upcoming product programs.* Partner with EDA vendors to evaluate, explore, and extend tool capabilities that improve design quality, shorten turn-around time, and enhance design optimization.* Architect, develop, deploy, and maintain advanced design automation flows and methodologies for digital and/or analog design at scale.* Lead evaluation, integration, and enhancement of EDA tools, driving improvements in design productivity, efficiency, and quality across multiple design teams.* Design and implement robust automation frameworks that reduce manual effort, increase reproducibility, and improve overall design throughput.* Identify workflow bottlenecks across design, verification, CAD, and methodology teams and lead cross-functional initiatives to streamline FPGA design execution.* Provide deep technical expertise in scripting, tool customization, and flow development for advanced semiconductor design needs.* Drive continuous innovation in design automation infrastructure through adoption of new methodologies, technologies, and optimizations.* Collaborate with internal and external EDA vendors, owning issue resolution, feature requests, and deployment of next-generation capabilities.* Mentor and provide technical leadership to junior engineers within the Design Automation organization.#LI-MD1**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.$142,600 - $206,500 USDWe use artificial intelligence to screen, assess, or select applicants for the position.### ## **Qualifications:****Minimum Qualifications:**Bachelor's or Master's in Computer Science, Electrical Engineering, or equivalent, with a minimum of 10 years of experience in IC Design or Design Automation and experience in the following:* Extensive experience with industry-standard EDA tools and hands-on expertise in design methodologies across multiple domains, such as Front-End Logic Design flows, Design Intent and FPGA-specific flows, Design Verification flows, and Design-for-Test (DFT) flows (with Back-End flow knowledge considered a plus).* Strong programming skills in Python, Tcl, C-shell, C, C++, or similar languages.* Familiarity with ML/AI applications and algorithms and their use in EDA or design methodology optimizations.* Proven leadership skills for driving collaborative, cross-functional projects, with strong communication and influencing abilities### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr

A leading technology company in San Jose is looking for a recent graduate or PhD candidate for an AI/ML development role. The position requires backend development skills in Go or Python and understanding of LLM infrastructure. Candidates should be ready to collaborate with cross-functional teams, optimizing models for real-world deployment. This role offers competitive salary ranges based on location, benefiting from Cisco's extensive employee perks and growth opportunities. #J-18808-Ljbffr

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology. Description In Physical Design, you will be at the center of design effort collaborating with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs and knowledge of basic chip architecture, back end chip design flow, physical synthesis, floor‑planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would include: Working with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. Completing netlist to GDS2 implementation for partition(s) meeting schedule and design goals. Timing, physical and electrical verification and driving the signoff closure for the partitions. Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution. Minimum Qualifications Basic understanding of logic gates. Preferred Qualifications Previous internship/co‑op, project work or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design. Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields. Experience with Verilog, VHDL, Python, Perl, TCL and/or SPICE. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $126,800 and $190,900, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr

A leading semiconductor company in San Jose seeks a Senior Engineer in Product Engineering to manage new product introductions and production support. Candidates should have a Master's degree in Electrical Engineering and two years of relevant experience. Responsibilities include interfacing with manufacturing, conducting failure analyses, and implementing process improvements. This role offers competitive pay and benefits, including healthcare coverage and a performance-based bonus. #J-18808-Ljbffr

A leading technology company in San Jose, California is seeking a Physical Design Engineer to play a critical role in backend implementation for FPGA/SoC devices. You will be responsible for tasks such as floorplanning, PPA optimization, and collaboration with diverse teams. The ideal candidate will have a Bachelor's degree in Electrical Engineering and over 6 years of hands-on experience. Join us to help develop innovative technology solutions. #J-18808-Ljbffr