MediaTek jobs - 1,646 jobs

MediaTek is seeking a talented and experienced technical leader with expertise in advanced packaging technologies, specifically 2.5D/3D. This role involves close collaboration with cross-functional teams, including IP, ASIC Design, Package Design, Signal Integrity, Power Integrity, Thermal, product engineering, Test engineering, etc. The goal is to develop innovative packaging solutions for automotive, datacenter/HPC, and computing applications. The ideal candidate will be instrumental in developing key packaging technologies, establishing third-party relationships, and addressing challenges in areas such as 2.5D/3D package integration, including but not limited to CoWoS, EMIB, SoIC, HBM, FCBGA, and HBPOP. The candidate should demonstrate ownership, high standards, strategic thinking, and customer obsession. Role and Responsibilities • Collaborate with internal teams, external customers, and key partners to develop advanced packaging solutions from concept to mass production • Coordinate with package design, substrate, and assembly partners to select materials and BOM, ensuring manufacturability and meeting electrical, mechanical, thermal, and system-level requirements • Lead and coordinate projects across design, engineering, supply chain, manufacturing, and quality assurance to ensure successful execution • Establish and maintain strong relationships with suppliers, customers, and internal teams to meet project requirements and resolve supply chain or manufacturing issues • Monitor and report on project progress, supply chain performance, and manufacturing metrics to senior management #LI-NL1 * Expertise in 2.5D/3D package architecture and advanced packaging technologies such as CoWoS, EMIB, SoIC, CoW, WoW, POP, etc. • Working knowledge of package design, electrical signal integrity, power integrity, thermal, and thermomechanical principles, with a fundamental understanding of 2.5D/3D package challenges • Experience with wafer level processes, package assembly processes, and substrate technology. • Strong supply chain and quality management skills, including BOM management, procurement, logistics, and inventory • Understanding of legacy packaging technologies, package failure mechanisms, and quick problem-solving skills • Ability to develop and maintain strong relationships with key enablement partners and customers, ensuring smooth communication and alignment on project requirements, product quality, reliability, system, and operational needs • Excellent communication skills • 10-15% international travel required Salary range: $180,000 - $250,000 Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Paid time off (PTO), Parental leave, 401K and more. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. #LI-NL1

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are seeking an engineer with strong hands‑on experience in FPGA build flows, design qualification, and developing infrastructure for platform regressions. This role is focused on developing robust smoke tests, functional test cases, and qualification workloads used to validate both FPGA designs and the associated platform software/toolchain flows. THE PERSON: The successful candidate will architect and implement daily and nightly regression pipelines, integrate them into a unified infrastructure, and ensure continuous quality and reliability of FPGA based platform design flows at scale. This role sits at the intersection of FPGA engineering, software automation, and infrastructure‑level validation. KEY RESPONSIBILITIES: FPGA Design & Build Flow Own FPGA compile/build flows (synthesis, place & route, timing closure, bitstream generation). Develop and maintain reference FPGA designs for build flow validation. Diagnose issues across RTL, constraints, tools, and platform dependencies. Platform Qualification & Toolchain Validation Develop targeted test cases for FPGA build flows, toolchain stability, and edge cases. Build scripts and automation for software stack validation (drivers, runtimes, APIs). Validate tool and environment changes, partner with vendors and internal teams on root cause and fixes. Define scalable design qualification criteria and coverage. Regression Infrastructure Design and maintain automated daily/nightly regression systems for FPGA and software toolchain validation. Enable distributed, scalable runs across on‑prem or cloud resources. Automate result collection, triage, and failure classification. Infrastructure & CI/CD Integration Integrate FPGA regressions into the unified infrastructure and CI/CD pipelines. Interface with shared services (e.g., build orchestration, monitoring, logging). Enable standardized reporting, dashboards, and notifications for regression health. PREFERRED EXPERIENCE: Large-scale FPGA farm or datacenter‑style validation. Monitoring/logging tools (e.g., Grafana, Prometheus, ELK). Operating unified build/validation infrastructures across multiple teams. Hardware bring‑up or silicon pre‑/post‑silicon validation. Cross‑functional and geographically distributed team collaboration. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA This role is not eligible for Visa sponsorship Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading technology company located in California seeks an experienced product marketer to join its team. This role involves leading go-to-market strategies for the CUDA-X libraries, creating compelling content, and engaging with various stakeholders. Ideal candidates will have over 12 years of experience in technology marketing and a solid understanding of NVIDIA's platforms, along with strong public speaking skills. Competitive salary offered up to $287,500 plus equity. #J-18808-Ljbffr

Amlogic, a leading multinational fabless semiconductor company producing System on Chip (SoC) solutions for Smart TVs and other consumer devices, is seeking a senior corporate attorney to join our headquarters office in Mountain View, California. This attorney will be the second U.S.-based attorney, reporting to the U.S.-based general counsel and joining a growing team of attorneys and compliance specialists who are in Shanghai. The ideal candidate will be comfortable working with internal and external clients in various countries, adapting to an ever-changing geopolitical environment, and maintaining a generalist mindset while focusing on contracts and compliance. This attorney will be working with salespeople and customers around the globe, providing legal advice to internal clients not only in the U.S., but also in our offices in South Korea, Japan, Taiwan, Singapore, India, the United Kingdom, and Serbia, and working with our in-house legal team in China. This is a great opportunity for a lawyer to maintain expertise in commercial contracting and compliance while developing skills and expertise over a broad range of matters. Work Location: Hybrid, with three days a week in our Mountain View, California office. Standard working hours are based on the Pacific Time Zone. Responsibilities: Draft, review, and negotiate a variety of agreements, including sales and services agreements, inbound and outbound IP and software licensing agreements, NDA's, procurement agreements, and various other agreements, and monitor existing agreements Provide guidance on compliance matters and develop and implement compliance programs. Counsel internal clients on a range of legal topics, including intellectual property, commercial law, competition, and other legal and regulatory areas. Collaborate with the global legal team to develop and implement best practices and policies in the areas of contracting, licensing, and compliance. Assist with other matters as they arise: data privacy, export control, employment law, entity management, corporate governance, litigation. Requirements: J.D. degree and license in at least one U.S. state bar (preferably California or New York). 7+ years of experience at a top law firm or similar in-house role. Ability to multi-task in a fast-paced environment. Keen attention to detail, ability to work independently and as part of a team, and excellent organizational skills. Willingness to learn and adapt to new challenges. Comfortable working in areas where the law is unsettled, rapidly changing, or unfamiliar. Good judgment with an understanding of when to ask for guidance or input, and how to spot and solve issues. Cooperative attitude and an affinity for working with others to get the job done. Exceptional written and verbal communication skills. Experience working in or with high-tech companies. Nice to Have: Semiconductor industry experience CIPP/US/E/CN Amlogic is an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. Amlogic is an E-Verify employer. We will use E-Verify to confirm the employment eligibility of all new hires.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE We are seeking a Senior Finance Manager to join the Adaptive and Embedded Computing Group (AECG) finance team, reporting to the Director of AECG finance. The candidate will be a key finance partner to the AECG General Manager, providing critical support in budgeting, planning, and consolidation activities specifically focused on OpEx and CapEx. In this position, you will work closely with the AECG BU senior leadership team and other stakeholders to provide valuable financial insights and guidance. THE PERSON The ideal candidate should be an experienced finance leader, have a bias for action, high sense of teamwork, and ability to speak up and make recommendations in a fast‑moving environment. This individual coaches and develops teams, embraces continuous improvement, and approaches challenges with a proactive mindset. KEY RESPONSIBILITIES Partner with senior leadership team to lead development of Annual Operating Plan and long‑term financial plan, including operating expense, headcount, and capital expenditures. Drive discussions on financial targets, resource allocation and perform scenario analysis to facilitate the decision‑making process. Lead and manage a team of financial analysts, overseeing budgeting and analysis activities while providing ongoing coaching and mentorship to ensure high performance and growth. Work closely with business unit leaders on monthly and quarterly forecast updates. Serve as a trusted finance partner to help business partners deliver financial targets. Drive monthly NRE (Non‑Recurring Engineering) program level updates, with a solid understanding of NRE accounting; gather inputs from program managers and track changes across versions. Prepare and disseminate timely and accurate financial information to allow the business to plan, forecast, and make decisions using controlled and consistent data. Continuously evaluate and enhance financial processes, tools, and methodologies to streamline budgeting, planning, and consolidation activities. Provide value‑added management decision support, driving key business goals, identify major trends and corresponding business issues. PERFERRED EXPERIENCE Progressive experience in financial analysis, budgeting, and planning, ideally within the semiconductor or related technology sector Deep expertise in OpEx/CapEx management, accounting standards, and financial reporting Prior experience managing and developing a team of financial analysts Advanced skills in financial modeling, forecasting, and ERP tools (SAP/SAC) Demonstrated financial leadership supporting business and engineering teams Strong analytical ability to interpret complex data, identify trends and communicate insights. Excellent interpersonal and communication skills; effective collaborator and influencer across functions. Proven self‑starter who thrives in fast‑paced, dynamic environments and manages multiple priorities independently. Eager, proactive learner with a positive team‑oriented approach. ACADEMIC CREDENTIALS Bachelor's degree in finance, accounting or equivalent MBA or CPA preferred This role is not eligible for visa sponsorship. #LI‑SD1 #LI‑Hybrid Benefits offered are described. AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

A leading technology company is seeking a Principal / Senior GPU Software Performance Engineer in San Jose, CA. This role involves optimizing GPU workloads for training performance, enhancing throughput, and resolving bottlenecks in distributed systems. The ideal candidate will have strong skills in GPU performance engineering and experience with deep learning frameworks, particularly PyTorch. This position offers a chance to work in a collaborative environment focused on innovation and inclusivity. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE: Be part of AMD's analog/mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDR5, DDR5, gDDR6, HBM2/HBM3, chip‑to‑chip,…) and chip‑to‑chip Gbps proprietary PHY IP solutions. Responsibilities include THE PERSON: The ideal candidate has experience leading others in technical settings. You also have excellent communication, writing, and presentation skills. KEY RESPONSIBLITIES: Definition, review and sign‑off on IP top level and component level specifications AMS components circuit and layout design Supervise pre‑silicon layout, post‑silicon characterization and debug. Support product bring‑up and debug, and Sign‑off on test‑plans and characterization reports. Interface with SOC teams, system HW/SW teams, and global manufacturing teams. PREFERRED EXPERIENCE: Experience in high speed serial and/or parallel mixed signal PHY/IO designs Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking. Hand‑on design experience in multi‑Gbps serial (PCIe, USB, …), parallel high BW memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3, gDDR5/gDDR6, …) and chip‑to‑chip links PHY IPs such as UCIe. Experience in mixed signal design circuit blocks such as digital/analog DLLs, duty cycle corrector, clock and data recovery, clock mixer, … Experience in low power design techniques for high speed/custom digital circuit (e.g. CMOS/CML high speed design for counters, dividers, …) design and analysis including transistor level timing sign‑off Solid understanding of power, area and performance trade‑offs in mixed signal IP design Design Experience in FinFET advanced CMOS process nodes 7nm and below coupled with a solid understanding of transistor device performance and fundamentals Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools Work with project‑manager, system architects, IC designers and physical designers to guarantee quality/timely deliverables meeting project's schedule and technical requirements Track record of successfully taking designs to production Excellent written and verbal communication skills able to operate without direct supervision but also work cross‑functionally, cross‑geographies collaborating and being part of a multi‑disciplinary team in a dynamic/fast paced environment. Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge ACADEMIC CREDENTIALS: BS, MS or PhD in Electrical Engineering, Computer Engineering or related equivalent LOCATION: San Jose, California This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available. This posting is for an existing vacancy. #J-18808-Ljbffr

A leading technology firm in California seeks a Director of Treasury Systems and Automation to oversee payment systems and drive automation initiatives. The ideal candidate has 15+ years of treasury experience and strong leadership abilities. This role involves managing system upgrades, integrations, and ensuring accurate transactions. Competitive salary range from $232,000 to $356,500 with a comprehensive benefits package. #J-18808-Ljbffr

A technology industry leader in California is seeking a Product Definition Engineer to evaluate and optimize pre-production silicon. The successful candidate will work with multi-functional teams, driving new feature initiatives and designing performance-critical product features. Ideal candidates will have significant engineering experience and collaborative skills. The role offers a salary range of 168,000 - 264,500 USD depending on level, alongside equity and benefits. #J-18808-Ljbffr

MediaTek's Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies that power the world's most advanced data centers. We are a dynamic group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions. Our team collaborates closely to push the boundaries of technology, ensuring optimal performance, power efficiency, and scalability for data center applications. Join our Data Center team and be a part of the technological revolution that is shaping the future of data centers. If you are passionate about innovation and have the expertise to drive strategic technology development, we would love to hear from you. The Data Center Chassis Lead will be responsible for architecting, adopting and designing chip/chiplet chassis building blocks for data center silicon. Key responsibilities include reviewing chassis building blocks, collaborating with chassis domain lead for architecting the version for data center, working with SoC/Chip/Chiplet design lead for integration requirement, execution plan and implementation, providing improvements based on analysis results, and conducting thorough quality design verification and documentation. * MS in Electrical Engineering/Computer Engineering or or related field. • 5+ years of experience in designing transistor-level digital circuits. • 3+ years of experience in hands on experience in architecting and designing chassis for data center silicon. • Strong knowledge in SoC/Chip/Chiplet chassis: clock and reset, power and thermal management, out-of-band management, platform security, RAS, debug & test, eFuse control and distribution, and etc. • Expert on designing with Verilog, SystemVerilog, Perl and Tcl script. • Proficiency with EDA tools like VCS, Design compiler, and so on. • Prior experience in all Front End activities and quality checks (eg: Lint, CDC...) • Good understanding and working knowledge in other domains like DV and DFT, timing closure • Able to provide timing constraints and work with PD teams to ensure RTL meets timing • Strong debugging and scripting skills (Perl, Python, Tcl...) Salary range: $190,000- $270,000. Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.

• Develop advanced algorithm and architecture for high speed electrical / optical SerDes. • Model the algorithm in Matlab / Python / C++ for performance evaluation. • Optimize algorithm and architecture for PPA. • Support bit-true cycle-true modeling, design verification, and post-silicon validation. • Collaborate with worldwide design teams. * Deep understanding of digital signal processing (DSP) and communication theory. • Proficiency in Matlab / Python / C++ for system modeling. • Experience with CDR, equalization, compensation, cancellation, sequence detection, error coding, etc. in wireline and optical systems is a plus. • Experience with analog circuit design or RTL design is a plus. • Team player with strong communication skills. • MS or higher degree in EE / CS or related field. Salary range: $150,000- $255,000 Employee may be eligible for performance bonus, short- and long-term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience, and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Vacation Time, Sick leave, Parental leave, 401K and more. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. #LI-NL1

A technology company is seeking a Manager for System Test Engineering located in Santa Clara, California. In this role, you will lead a team to refine manufacturing test solutions and improve test strategies for various product segments. The ideal candidate has over 6 years of experience in post silicon validation and at least 2 years in management. Strong skills in Python and bash scripting are preferred. Competitive salary and generous benefits package are offered. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD/Xilinx programmable devices. THE PERSON: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware and firmware engineers to understand the new features to be verified Take ownership of block level verification tasks Define test plans, test benches, and tests using System Verilog and UVM Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes Review functional and code coverage metrics to meet the coverage requirements Develop and improve existing verification flows and environments PREFERRED EXPERIENCE: Strong understanding of computer architecture and logic design Knowledge of Verilog, system Verilog and UVM is a must Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification Working knowledge of C/C++ and Assembly programming languages Exposure to scripting (python preferred) for post-processing and automation Experience with gate level simulation, power and reset verification ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

MediaTek USA is looking for applicants who have solid experience in application engineering with strong technical program management experience. The candidate will play a key technical support role in support for our Wi-Fi 7 and Bluetooth combo products in the CE market including TV, Smart Speakers, Streaming Sticks. Applicant will be responsible for supporting MediaTek chipsets at the customer site with close collaboration with our internal R&D team to drive cross functional teams for failure / root cause analysis and implement corrective action measures across MediaTek. Ability to adapt to a dynamic and rapidly changing environment requiring efficient and timely decision making. Strong communication skills toward internal stakeholders and customers and the ability to lead and develop new processes and ideas. MediaTek has many successful CE products in the market and we keep looking for talents with solid systematic analysis and project leading skills. Welcome to join and grow with us. Requirements • Computer science or engineering related background • Willingness and ability to learn computer networking and Wi Fi technology. • Can do mentality and solid issue solving methodology. Not afraid to take on challenges or face obstacles. • Passionate and persistent to strive exceeding customer expectations and ensure priority in satisfying our customers • Shows integrity and leadership with tasks in-hand. Relentlessly focus on delivering result once committed. Preferred Requirements • Any one of below capability is a plus to us • Knowledge of embedded SW for Linux, OpenWrt/, prprl Wrt, RDK-B • Strong background in networking protocols including TCP, /UDP, VLAN, NAT • Experienced with wired and wireless throughput testing including Chariot, ACE Channel Emulators, Veriwave, and Octoscope (Keysight, Anritsu) • Familiar with Wi-Fi rate adaptation, Wi-Fi Direct, HostAPD, WPA Supplicant, Wi-Fi Aware is a plus • Familiarity with H/W interfaces such as PCIe, RGMII, I2S, UART, USB, etc • Knowledge of Security Requirements: WPA2, 802.11i, 802.1X, VPN (IPsec, L2TP) • Wireless Technology: Wi-Fi 802.11a/b/g/n, 802.11ax, 802.11be, Bluetooth 5.2 • Wired Technology: 802.3 Ethernet (100/1000/2500BASE-T), 802.3af PoE, DOCSIS 3.0, GPON a plus • Experience working with US/EU broadband internet service providers • Effectively communicate customer requirements to R&D teams with multiple regions between international sites. • Technical project management experience is a plus • Strong business communication capability both in written and verbal is a must Salary range: $ 180K- $ 260K Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Paid time off (PTO), Parental leave, 401K and more. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. #LI-AK1

A leading technology company located in San Jose is seeking an engineer specialized in FPGA build flows and software automation. The candidate will own FPGA compile/build processes, develop robust regression pipelines, and ensure quality throughout the design and validation phases. An ideal candidate will possess strong experience in toolchain validation and collaboration across teams. This position offers an innovative environment focused on advancing technology and collaboration within a diverse team. #J-18808-Ljbffr

MediaTek Incorporated is a global fabless semiconductor company that enables nearly 2 billion connected devices a year. We are a market leader in developing innovative systems-on-chip (SoC) for mobile device, home entertainment, connectivity and IoT products. MediaTek is the number one Wi-Fi supplier across broadband, retail routers, consumer electronics devices and gaming, and its Wi-Fi 6 chipsets are powering the latest networking equipment for faster computing experiences. Our dedication to innovation has positioned us as a driving market force in several key technology areas, highly including power-efficient mobile technologies, automotive solutions and a broad range of advanced multimedia products such as smartphones, tablets, digital televisions, 5G, Voice Assistant Devices (VAD) and wearables. MediaTek empowers and inspires people to expand their horizons and achieve their goals through smart technology, more easily and efficiently than ever before. We work with the brands you love to make great technology accessible to everyone, and it drives everything we do. Summary: We are seeking highly skilled Physical Design Technical Leaders to join our team. The ideal candidates will have extensive experience in physical design and flow development, with a strong background in advanced nodes and low-power design techniques. As a Physical Design Technical Leader, you will guide customers, drive the development and execution of physical design flows, and collaborate with various teams to optimize methodologies and ensure high-quality tape-outs. Job Description: Guide customers in selecting optimal EDA tools, implementation flows, and methodologies. Perform and review physical design checks to ensure customer tape-out quality meets MediaTek's standards. Drive the development and execution of the physical design flow from RTL to GDSII. Possess deep knowledge of floor planning, placement, routing, timing closure, IR/EM analysis and fixing, DRC, and LVS. Collaborate with various teams, including but not limited to design, flow, implementation, EDA vendors, and IT/infrastructure, to optimize flow and methodology. Develop and maintain in-house methodologies and flows. Requirements: 10+ years of experience in physical design and flow development. Experience with advanced nodes (e.g., 4nm, 3nm, 2nm). Familiarity with design for testability methodologies. Deep knowledge of low-power design and implementation techniques. Salary range: $175,000- $255,000 Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Paid time off (PTO), Parental leave, 401K and more. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. #LI-NL1

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Video Systems, HW Architecture General Summary The Machine Learning Hardware Accelerator team is seeking an experienced and talented Hardware Design & Architecture Lead. This role will drive the definition and analysis of next‑generation ML hardware accelerator architectures, with a special emphasis on vision applications for mobile and emerging products. Key Responsibilities Architect high‑performance, power‑efficient ML hardware accelerator designs, especially for computer vision workloads (e.g., image classification, object detection, video analytics). Analyze and optimize hardware for performance, power, and area (PPA) tradeoffs. Define hardware micro‑architecture for efficient implementation of ML algorithms. Lead HW IP development, working closely with RTL design, verification, synthesis and physical design teams to improve PPA. Collaborate closely with global hardware, software, and systems teams to deliver best‑in‑class ML solutions. Work with cross‑functional teams (HW design, verification, SW, systems, marketing, product planning) to align architecture with product goals. Use models, simulators, profilers, and real hardware to justify architectural decisions quantitatively. Apply knowledge of CPUs, GPUs, DSPs, memory, and bandwidth analysis to ML hardware design. Communicate results and technical issues effectively with leads and peers. Invent and file patents for innovative hardware solutions. Minimum Qualifications Experience in hardware development for ML, multimedia, or accelerator technologies (vision, imaging, video, display, audio, etc.). Experience in system or chipset development for SoC products, preferably in the mobile market. Familiarity with OS principles and HW/SW interaction. Experience with SoC bus, interconnect, and memory technologies. MS Degree required with 15+ years industry experience in one or more of the following areas: Architecture/micro‑architecture of ML or multimedia cores. Experience with ML frameworks and accelerator standards (e.g., TensorFlow Lite, ONNX). VLSI design and verification (Verilog/SystemVerilog/HLS). C/C++/SystemC programming. Hands‑on experience with simulators and performance/power models. Scripting & automation skills. Preferred Qualifications Deep domain knowledge in ML for vision (image/video processing, neural network architectures for vision). Experience collaborating with global teams across multiple time zones and cultures. Experience working with synthesis and physical design teams for HW IP development and PPA improvement. Excellent communication, documentation, and presentation skills. Demonstrated technical and people leadership. Minimum Qualifications: Bachelor's degree in Computer or Electrical Engineering, Computer Science, or related field and 8+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. Master's degree in Computer or Electrical Engineering, Computer Science, or related field and 7+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. PhD in Computer or Electrical Engineering, Computer Science, or related field and 6+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. Pay range and Other Compensation & Benefits: $228,400.00 - $342,600.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

MediaTek's Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies that power the world's most advanced data centers. If you are passionate about innovation and have the expertise to drive strategic technology development, we would love to hear from you. We are seeking an independent and innovative Modeling Engineer to join our advanced pathfinding team. In this role, you will drive the development and integration of software and hardware models supporting fast prototyping and architectural exploration for next-generation silicon solutions. You will leverage emulation tools (including Gem5 and related platforms), performance modeling frameworks, and high-level programming to enable rapid iteration and data-driven decision-making for new technology directions. * Education: Bachelor's or Master's degree in Computer Engineering, Computer Science, or a related field. · Experience: 4+ years modeling experience in silicon architecture, emulation, or performance engineering; direct work on pathfinding, advanced prototyping, or architectural studies is desirable. · Proficiency with SW emulation tools (Gem5, QEMU, Simics, or other platforms a plus). · Strong command of C/C++ programming; SystemC is a plus. · Familiarity with cache and memory hierarchy modeling, interconnects, and simulation-based performance analysis. · Ability to work independently, set technical direction, and deliver results on aggressive schedules. · Soft Skills: Analytical mindset, problem solving skills, clarity in communication and technical reporting, comfort with ambiguity and iterative learning. · Bonus Skills: (1) Scripting in Python or shell for environment automation (running experiments, parsing results). (2) Experience with hardware/firmware co-modeling, hybrid co-simulation, or FPGA-based rapid prototyping. (3) Knowledge of computer architecture, low-level software, or firmware development. Salary range: $190,000- $270,000. Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. #LI-YS1

1. Develop innovative MAC and above protocol features for next generation Wi-Fi, Bluetooth, and other connectivity technologies to enable new applications and services. 2. Responsible for standards development via proposing protocol mechanisms at international standards organizations (e.g., IEEE 802.11, Wi-Fi Alliance, Bluetooth SIG), with focus on high efficiency and low power. 3. Work with SW and HW RD teams in system architecture, module & algorithm design, as well as generation of patents. 4. Provide technology development guidance to business development and marketing teams in developing technology roadmaps as well as support technical marketing activities 1. PHD with 7+ or MS with 10+ years of experience in Electrical Engineering, Computer Science or related Communication System engineering. 2. Research and IP development track record in the wireless communications standards area related to 802.11n/ac/ad/ax/ay or Bluetooth 4/5, BLE, Mesh, Direction Finding. 3. Wireless product development experience in the form of system architecture, system performance analysis, firmware/software design and development. 4. Track record of technical leadership experience in MAC and PHY wireless protocols standards development in organizations such as IEEE 802.11 and BT-SIG. 5. Excellent written and presentation skills. Salary range: $175,000- $255,000 Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation Time, Parental leave, 401K and more. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. #LI-NL1