Design Verification Engineer jobs at MediaTek

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering Role: * Familiarity with RTL design in Verilog and System Verilog * Develop verification methodology, ensuring scalable and portable environment across simulation and emulation. * Develop test plan to verify Hardware building blocks, Design macros and Standard interfaces (PCIE, DDR, USB, I2C, SPI, etc) . * Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals * Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches * Develop verification methodology, ensuring scalable and portable environment across simulation and emulation. * Develop and maintain emulation environment to collect metrics related to emulation environment. Will need to be in San Diego full time, 5 days a week Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. Must be a U.S. citizen and eligible to receive a U.S. Government security clearance Required Qualifications: * 5+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture * 5+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flows Relevant experience of 2-3+ yrs in any of the mentioned domain - Design/Verification/ Implementation Preferred Qualifications: One or more of the following preferred: * Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc. * Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology * Good understanding of chip-level functional model building * Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C * Knowledge of Behavioral and Structural models and familiarity with simulation environments * Experience customizing and debugging make-based build flows and working with Xilinx's Vivado tools * Experience with cm tools such as Git and Gerrit. * Experience in formal / static verification methodologies will be a plus * Experience with emulation platforms - Palladium, Zebu, Veloce, FPGAs. * Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog. * Experience with C/C++ DPI transactors and monitors. * Develop and maintain emulation environment to collect metrics related to emulation environment. * Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors. * Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations. * Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. * Experience with debugging tools such as JTAG and lab test equipment such as logic analyzers, oscilloscopes, signal generators, etc. * Experience with GLS, and scripting languages such as Perl, Python is a plus * Linux OS proficiency The ideal candidate would be a self-starter with strong initiative, discipline, motivation, and a focus on quality. The candidate must be a team player and be flexible and open to a variety of task assignments within the team. Minimum Qualifications: * Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $115,600.00 - $173,400.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers.

Company: Qualcomm Atheros, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Job Responsibilities * Own block level verification for wireless connectivity designs and meet coverage goals * Own the test-bench, coding guidelines, best practices and enable reuse of block level UVM test-benches at chip level. * Come up with a comprehensive verification strategy encompassing simulations, formal verification, HW/SW reuse and simulation performance. * Work with cross functional IP teams for Integration verification * Work with design team to understand Spec and come up comprehensive test plan for quality Verification Required skill sets: * 2+ years ASIC design, verification, or related work experience. * Experience in UVM, System Verilog, SOC/Subsystem/IP DV, Debugging and problem solving Preferred Qualifications * 3+ yrs. of ASIC Verification experience * 2+ yrs. of working experience in UVM * Experience with scripting languages. * Experience with building at least one test bench using UVM from scratch * Good amount of experience in Digital Logic design techniques, SoC architecture, including ARM CPUs, communications peripherals, multi-domain clocking, power management, AMBA bus protocols such as AHB and AXI * Knowledge of low power, processor verification and GLS flows is plus point * Experience with testbench automation, industry standard bug tracking, and regression mechanisms, code and functional coverage-driven verification closure and be able to set up and deploy verification strategies based on directed testing, randomization, assertions, and architectural performance testing to achieve coverage. * Strong in problem solving * Strong team player and communicator Minimum Qualifications: * Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $126,700.00 - $190,100.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD/Xilinx programmable devices. THE PERSON: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: * Collaborate with architects, hardware and firmware engineers to understand the new features to be verified * Take ownership of block level verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes * Review functional and code coverage metrics to meet the coverage requirements * Develop and improve existing verification flows and environments PREFERRED EXPERIENCE: * Strong understanding of computer architecture and logic design * Knowledge of Verilog, system Verilog and UVM is a must * Familiarity with common security protocols and algorithms, including hashing, digital signatures, and encryption standards like AES and SHA. * Strong understanding of computer architecture and logic design * Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification * Working knowledge of C/C++ and Assembly programming languages * Exposure to scripting (python preferred) for post-processing and automation * Experience with gate level simulation, power and reset verification ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Graphic Memory Controller(GMC) is an IP that delivers into all SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for a design verification engineer in the Dram Controller IP at AMD's Santa Clara, CA Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. This is a highly visible position in a growing team. Leadership opportunity is available. We are seeking a highly skilled Formal Verification Expert to join our talented team as a Staff Engineer and technical lead. This role is crucial to ensuring IP quality through rigorous formal verification processes. THE PERSON: The successful candidate will play a key role in developing verification strategies, leading formal verification team, and collaborating across departments to ensure the highest quality standards. KEY RESPONSIBILITIES: * Lead formal verification team to ensure IP quality and project execution. * Develop and implement comprehensive formal verification plans, including constraint/assertion property development, model development, inconclusive issue resolve and sign off, etc.. * Collaborate with IP architects, hardware designer, verification engineers, and other stakeholders to design efficient formal verification strategies. * Mentor and guide junior engineers in formal verification techniques and best practices. * Communicate results and progress effectively to cross-functional teams, providing insights and actionable recommendations. * Drive continuous improvement in formal verification processes and contribute to the advancement of the organization's verification capabilities. PREFERRED EXPERIENCE: * Proven experience in formal verification and simulation, model checking, and theorem proving applied to complex IP or systems. * Proficiency in formal verification tools such as VC-Formal or JasperGoal * Strong understanding of hardware description languages (e.g., VHDL, Verilog) and/or programming languages (e.g., System verilog, C, C++, Python). ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Santa Clara, CA #LI-SL3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are seeking a seasoned Lead Design Verification Engineer with expertise in verifying networking chip. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead verification teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: We are seeking an experienced and hands-on Lead Design Verification Engineer to drive the verification strategy, methodology, and execution for our next-generation high-performance networking chip. The ideal candidate will have deep expertise in SoC/ASIC verification, strong knowledge of networking protocols and architectures, and a proven ability to lead verification teams in a fast-paced environment. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: * Ownership of verification strategy for one or more major IP blocks or subsystems within a complex networking ASIC. * Architect and implement testbenches using UVM/SystemVerilog, ensuring maximum coverage and quality. * Develop and maintain test plans, coverage models, and scoreboards to ensure comprehensive verification of all design features. * Lead and mentor a team of DV engineers - drive reviews, define milestones, and ensure high-quality deliverables. * Collaborate closely with design, architecture, and software teams to define verification requirements and debug issues across the full chip. * Develop and maintain automation and regression infrastructure, including CI/CD integration. * Drive coverage closure and signoff for IP and SoC-level verification. * Contribute to methodology improvements, verification IP reuse, and best practices across the DV organization. * Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements * Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: * Proven line management experience, including hiring, mentoring, and performance management of DV engineers. * Demonstrated ability to build and lead high-performing verification teams, setting goals and driving execution across projects. * Experience with chip-level verification for networking ASICs, switches, or routers. * Familiarity with traffic generators, packet-level verification, and network protocol stacks. * Knowledge of SystemC, C testbenches, or hardware/software co-verification. * Exposure to emulation or FPGA prototyping environments (e.g., Palladium, Veloce). * Prior experience leading cross-site or multi-IP verification efforts. * Strong communication, collaboration, and leadership skills with the ability to influence technical direction across disciplines. ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in related discipline preferred LOCATION: Santa Clara, CA #LI-BW1 #LI-hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements. The engineer will be responsible for a variety of advanced verification tasks such as: verification environment development using modern verification techniques (System Verilog and UVM); designing verification components such as UVM agents, and behavioral models; implementing coverage and assertions using System Verilog; and developing random & directed test cases against the specification. This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing coverage results. Candidate must be a highly productive individual contributor with a demonstrated technical capability in system and sub-block level verification. Job Requirements: A Bachelor's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent 12+ year's relevant industry work experience. Experience in verifying designs at system level and block level. Fluent knowledge of RTL verification methodologies including System Verilog. Strong experience in ASIC design verification flows and DV methodologies Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills. Strong and independent design debugging capability. Strong verbal and written communication skills. Must be comfortable working in a team environment with verification team and design team members. Demonstrated ability to analyze and resolve complex verification trade-off scenarios. Must have legal authorization to work in the US The candidate should have expertise in some (or preferably all) of the following areas: Experience with hardware design and debug, C++/SystemC and other programming languages are a strong plus. Experience working with Emulators and FPGA based prototyping is a plus. Familiarity with overall chip design methodologies and tools Knowledge of CPU, DDR, Bus Protocol, Network Protocol or DSP design preferred Additional Job Description: Compensation and Benefits The annual base salary range for this position is $141,300 - $226,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. The Role: This is a great opportunity to be part of the next generation GPU chip development team at AMD Santa Clara for ASIC Physical Design engineer. You will join us as Sr. Staff Engineer / Principal Member of Technical Staff. KEY RESPONSIBILITIES: Senior level lead engineer driving PPA improvements in both pre-silicon and post-silicon design phase Drive cross-functional teams (technology, CAD tools, platform characterization , binning practices and design methodology) and optimize margining practices across boundaries to deliver best in class performance/watt Improve low voltage margining methodology and design practices to improve Vmin and performance/watt for low power GFXIP Drive design practices to improve boost frequency for GFXIP Drive silicon correlation and deliver systematic improvements to improve silicon to STA on high performance Graphics IP PREFERRED EXPERIENCE: Over 18 years' experience with BSEE/BSCS or 15+ years of MSEE or MSCE in ASIC Physical Design from RTL to GDSII Excellent analytical and problem-solving skills along with attention to details Strong RTL analysis skills including Verilog, Timing Analysis and library understanding Strong knowledge in design margining methodology, low voltage design, silicon - STA correlation Hands on experience in taping out 5nm, 7nm, 14nm and/or 16nm SOC Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics Strong communication, Time Management, and Presentation Skills Must be a self-starter, and be able to independently and efficiently drive tasks to completion Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player ACADEMIC CREDENTIALS: Bachelor's or Master's Degree in Electrical Engineering, Computer Science, or equivalent is preferred. #LI-PH1 Requisition Number: 181183 Country: United States State: California City: Santa Clara Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. ASIC Physical Design Engineer THE ROLE: The position will involve working with a very experienced physical design team of AMD graphics core and is responsible for delivering the physical design of blocks to meet challenging goals for frequency, power and other design requirements for AMD next generation graphics processors in a fast-paced environment on cutting edge technology. THE PERSON: Physical design Engineer with strong analytical thinking and problem-solving skills with excellent attention to detail. The candidates should have excellent communication skills, very good team player and ability to drive, lead and mentor team of engineers for project execution. KEY RESPONSIBILITIES: Physical design of complex GPU multi-millions gate design and achieve required performance, area and power targets Work with RTL design to analyze potential bottlenecks for frequency, resolve LOL and timing issue upfront in the project cycle to achieve frequency targets Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Innovus, genus PREFERRED EXPERIENCE: 10+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in leading team of Engineers for design closure Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Experience in RTL design and LOL reduction is preferred Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. Proficient in perl, python, tcl etc ACADEMIC CREDENTIALS: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Orlando FL, Santa Clara CA, Folsom CA, Austin TX, Boston, #LI-PH1 Requisition Number: 176681 Country: United States State: California City: Santa Clara Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate's responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred. THE PERSON: High energy candidates with strong written and verbal communication skills, and structured, well-organized work habits will be successful. Team and goal oriented are essential. KEY RESPONSIBILITIES: * Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff * Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency. * Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA checks. * collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows. * Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts) PREFERRED EXPERIENCE: * Worked with EDA tools that enable RTL quality checks * Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. * Experience with analyzing the timing reports and identifying both the design and constraints related issues. * Ability to multitask, grasp new flows/tools/ideas. * Experience in improving the methodologies. * Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. * Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT) * Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters * Strong analytical and problem-solving skills ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA This role is not eligible for visa sponsorship. #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ Staff ASIC Design Engineer - AI Engineer- 152880 THE ROLE: AMD-Xilinx is seeking a capable and motivated RTL/ASIC design engineer to be part of front-end design team of next generation AI Engine/ML processors. THE PERSON: You will take part in design and implementation of high-performance, low-power processor and accelerator IP for AI/ML applications. KEY RESPONISIBILITES: In this role you will: Define and specify micro-architecture of processor building blocks based on architecture requirements RTL design and debug of complex blocks in Verilog / System Verilog Analyze performance and make implementation choices to optimize timing Analyze and optimize design for power efficiency and power integrity Work with verification and physical design teams to achieve high quality design and successful tape out Solve customer problems through innovative enhancements to product architecture/ micro-architecture Design and implement underlying clocking infrastructures to ensure implementation tool requirements are met and are optimized for compile time and memory Collaborate with cross-functional teams to solve novel problems across multiple functional areas in development of clocking features and/or algorithms PREFERRED EXPERIECE: Strong experience in the following ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes Digital design and experience with RTL design in Verilog/System Verilog Circuit timing/STA, and practical experience with Prime Time or equivalent tools Low power digital design and analysis Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation Experience in following is highly desired Understanding of FPGA architecture and implementation flow TCL, Perl, Python scripting Version control systems such as Perforce, ICManage or Git Strong verbal and written communication skills Ability to organize and present complex technical information Fluent in working with Linux environment Needs to be manually updated. ACADEMIC CREDENTIALS BSEE or equivalent and 8 years of relevant work experience, or MSEE or equivalent with 6 years of experience LOCATION:San Jose, CA #LI-DA1 Requisition Number: 152880 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This is a unique opportunity to be at the forefront of AMD's next-generation product development. In this role, you will drive design verification flows that enable robust product design and successful tapeout, including advanced silicon technologies and 3DIC packaging solutions. THE PERSON: We are seeking a highly skilled Physical Verification Engineer to join our team. The candidate will be responsible for developing and maintaining Design Rule Check (DRC) decks, supporting product-level physical verification sign-off, and ensuring compliance with manufacturing requirements through Design for Manufacturability (DFM) flows. JOB RESPONSIBLITIES: * Develop, validate, and maintain DRC decks for advanced technology nodes * Support product & IP physical verification sign-off, including: * Performing QA on physical verification flows * Reviewing and approving waiver requests * Collaborating with design teams to resolve violations * Work closely with foundry and internal teams to ensure rule compliance and process alignment * Implement and optimize DFM flows to improve yield and manufacturability KEY QUALIFICATIONS: * Strong experience in physical verification tools (e.g., Mentor Calibre, Synopsys IC Validator). * Proficiency in SVRF, TVF, or similar rule deck languages * Familiarity with advanced process nodes (TSMC 2nm & 3nm) and foundry design rules * Knowledge of DFM methodologies and best practices * Working experience of LVS, RC Extraction, EMIR and PERC ESD flow is preferred * Prior experience in supporting semiconductor product sign-off is preferred * Excellent problem-solving and communication skills ACADEMIC CREDENTIALS: * Bachelor degree in engineering or physical science, preferably with advanced degree (MS or PhD) LOCATION: San Jose, CA This role is not eligible for visa sponsorship. #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As an IP verification engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success. THE PERSON: You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBLITIES: * Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's * Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases * Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers * Build the directed and random verification tests * Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality PREFERRED EXPERIENCE: * Experience with PCIe or CXL or NVMe or ethernet protocols is a must * Proficient in IP level ASIC verification * Expert in Verilog, System Verilog, Object Oriented programming * Expertise in developing UVM based verification frameworks and testbenches * Scripting and automation of verification processes and flows * Exposure to leadership or mentorship is an asset * Experience working in a team environment through the ASIC / FPGA Project lifecycle from Planning to Tape Out * Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process * Good Computer Architecture, systems knowledge * Comfortable in python / perl and editing / maintaining scripts * Strong communication skills and the ability to work independently as well as in a cross-site team environment * Exposure to generative AI or simulation tools for test, testbench, assertion, test plan generation or performance optimization is a plus ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This is an exciting opportunity for an experienced Principal Hardware System Engineer to work on cutting-edge technologies with our NTSG - Network Technologies Solutions Group. If you are passionate about hardware development, we encourage you to apply and join our dynamic team. We are seeking a talented and experienced Engineer to join our team, focusing on hardware systems and products. THE PERSON: We are seeking an experienced Principle Hardware System Engineer to drive the continuation of existing and future hardware systems and products. The successful candidate will be responsible for ensuring the functionality, reliability, and performance of our hardware products around PCIe, DDR and Ethernet subsystems, while keeping an outlook for future enabling and related technology. The ideal candidate will have a strong background in hardware engineering, excellent technical skills, and communication skill. Hardware Bring up and Support: * Lead the bring up and support of refreshed hardware systems and products involving next-gen PCIe, memory, and high-speed ethernet subsystems. * Collaborate with cross-functional teams, including escalation from manufacturing, quality, and field service, to ensure hardware products meet customer requirements. Root Cause Analysis and Corrective Action: * Investigate, hand-on debug and resolve next-gen PCIe, memory, and high-speed ethernet hardware issues, including root cause analysis and corrective action. * Collaborate with suppliers and vendors to resolve hardware-related issues. * Develop and implement corrective actions to prevent future hardware failures. Design and Implementation of Improvements: * Identify opportunities for hardware improvements and cost reductions. * Collaborate with cross-functional teams to design and implement hardware improvements, including design changes, component second source validation and component substitutions. * Develop and implement test plans to validate hardware improvements. Documentation and Knowledge Transfer: * Maintain and update technical documentation, including design documents, user manuals, and technical notes. * Collaborate with knowledge management teams to ensure knowledge transfer and retention. Collaboration and Communication: * Collaborate with stakeholders, including product management, sales, and marketing, to understand customer requirements and market needs. * Communicate technical information to non-technical stakeholders, including project status, technical risks, and design decisions. PREFERRED QUALIFICATIONS: * Extensive experience in hardware engineering around next-gen PCIe Gen5 and above, DDR4/DDR5 memory, and 100G ethernet and above. * Experience with hand-on hardware troubleshooting down to component isolation and root cause, repair, and replacement. * Strong knowledge of hardware design principles, including circuit design, PCB design, and system integration. * Experience with hardware development tools, including CAD software (e.g., Altium, Cadence), simulation tools (e.g., SPICE), and programming languages such as Python scripting. * Familiarity with hardware testing and validation techniques, including testing, debugging, and troubleshooting. * Excellent communication and collaboration skills, with ability to work with cross-functional teams. * Strong problem-solving skills, with ability to analyze complex technical issues and develop effective solutions. * Ability to prioritize tasks, manage multiple projects, and meet deadlines. Nice to Have: * Experience with specific hardware technologies, such as FPGA, CPLD, ASIC, or high-speed digital design. * Experience with configuration management tools, such as Git or SVN. ACADEMIC CREDENTIALS: Bachelor's degree in Electrical Engineering, Computer Engineering, or related field. Master's degree or higher preferred. LOCATION: Santa Clara, CA This role is not eligible for VISA sponsorship #LI-BW1 #LI-hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : Broadcom's Central Engineering Design Correlation team is looking for an energetic and self-driven professional to join our team to help with silicon technology evaluation in advanced process nodes for IP and product designs. Our mission is to assess foundry technology offerings, help define new technology platforms for IP and product designs, risk assessment, and provide Broadcom's design communities with insights into design and process-technology interactions especially during co-development in advanced process nodes. The candidate will have the opportunity to participate in new technology platform definition, PPAC (power performance area cost) assessment and benchmarking, test structure design, silicon characterization and model to silicon correlation in most advanced foundry technology nodes. The candidate will work closely with other experts in the fields of CMOS process technology, device & modeling, process and device reliability, digital & analog IP design, design sign-off flow for timing and power, CAD & EDA tools, as well as chip designers from various product lines. Primary duties will include assessment of technology offerings and capabilities to meet design needs and drive alignment with IP/product requirements. This role will involve active participation with foundry and internal teams on new technology enablement including help ensuring robustness of technology platforms. Candidate must have the ability to prioritize well, communicate clearly, deliver solutions on time, and possess excellent data analysis & foundry interaction skills. The candidate expected to work across multiple facets of projects and juggle multiple responsibilities at the same time. The position is in Broadcom's Irvine facility in California. Responsibilities: Candidate will support IP and Chip teams with technology evaluation including reliability and design enablement. Responsibilities as part of technology evaluation will involve test structure layout, verification, extraction, simulation, and silicon evaluation. The job scope will include a) cross-functional quality assurance of designs and tape-outs, b) EDA & RCX tool quality and predictability, and c) custom device infrastructure readiness & robustness. Candidate will engage in collaborative team projects involving design, platform technology, and operations teams and foundry partner Qualifications: Advanced degree in EE, Material Science, Physics or related field with 10+ years of industry experience after MS or 7+ years after PhD with recent work in advanced FINFET (or GAA) nodes. 1. Strong background in advanced CMOS technology (FEOL, MEOL, BEOL) including understanding of design-technology interactions 2. Proficient in interacting with design teams and foundry partner 3. Familiarity with analog and digital design flows and CAD tools 4. Hands-on experience with device/circuit level test structure designs, verification (DRC, LVS), extraction, spice simulation, silicon characterization (DC/AC/RF) and data analysis 5. Extremely detail oriented with strong analytical, communication, and multitasking skills 6. Mix of hands-on and project management skills Additional Job Description: Compensation and Benefits The annual base salary range for this position is $127,100 - $203,400 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

**Please Note:** **1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)** **2. If you already have a Candidate Account, please Sign-In before you apply.** **:** **** Broadcom's Central Engineering Design Correlation team is looking for an energetic and self-driven professional to join our team to help with silicon technology evaluation in advanced process nodes for IP and product designs. Our mission is to assess foundry technology offerings, help define new technology platforms for IP and product designs, risk assessment, and provide Broadcom's design communities with insights into design and process-technology interactions especially during co-development in advanced process nodes. The candidate will have the opportunity to participate in new technology platform definition, PPAC (power performance area cost) assessment and benchmarking, test structure design, silicon characterization and model to silicon correlation in most advanced foundry technology nodes. The candidate will work closely with other experts in the fields of CMOS process technology, device & modeling, process and device reliability, digital & analog IP design, design sign-off flow for timing and power, CAD & EDA tools, as well as chip designers from various product lines. Primary duties will include assessment of technology offerings and capabilities to meet design needs and drive alignment with IP/product requirements. This role will involve active participation with foundry and internal teams on new technology enablement including help ensuring robustness of technology platforms. Candidate must have the ability to prioritize well, communicate clearly, deliver solutions on time, and possess excellent data analysis & foundry interaction skills. The candidate expected to work across multiple facets of projects and juggle multiple responsibilities at the same time. The position is in Broadcom's Irvine facility in California. **Responsibilities** : Candidate will support IP and Chip teams with technology evaluation including reliability and design enablement. Responsibilities as part of technology evaluation will involve test structure layout, verification, extraction, simulation, and silicon evaluation. The job scope will include a) cross-functional quality assurance of designs and tape-outs, b) EDA & RCX tool quality and predictability, and c) custom device infrastructure readiness & robustness. Candidate will engage in collaborative team projects involving design, platform technology, and operations teams and foundry partner **Qualifications** **:** Advanced degree in EE, Material Science, Physics or related field with 10+ years of industry experience after MS or 7+ years after PhD with recent work in advanced FINFET (or GAA) nodes. 1. Strong background in advanced CMOS technology (FEOL, MEOL, BEOL) including understanding of design-technology interactions 2. Proficient in interacting with design teams and foundry partner 3. Familiarity with analog and digital design flows and CAD tools 4. Hands-on experience with device/circuit level test structure designs, verification (DRC, LVS), extraction, spice simulation, silicon characterization (DC/AC/RF) and data analysis 5. Extremely detail oriented with strong analytical, communication, and multitasking skills 6. Mix of hands-on and project management skills **Additional Job Description:** **Compensation and Benefits** The annual base salary range for this position is $127,100 - $203,400 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. **Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.** **If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.** Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library (******************************* and check out our Connected by Broadcom (************************************************************************************************************************************************* series. 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Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : Broadcom's Central Engineering Design Correlation team is looking for an energetic and self-driven professional to join our team to help with silicon technology evaluation in advanced process nodes for IP and product designs. Our mission is to assess foundry technology offerings, help define new technology platforms for IP and product designs, risk assessment, and provide Broadcom's design communities with insights into design and process-technology interactions especially during co-development in advanced process nodes. The candidate will have the opportunity to participate in new technology platform definition, PPAC (power performance area cost) assessment and benchmarking, test structure design, silicon characterization and model to silicon correlation in most advanced foundry technology nodes. The candidate will work closely with other experts in the fields of CMOS process technology, device & modeling, process and device reliability, digital & analog IP design, design sign-off flow for timing and power, CAD & EDA tools, as well as chip designers from various product lines. Primary duties will include assessment of technology offerings and capabilities to meet design needs and drive alignment with IP/product requirements. This role will involve active participation with foundry and internal teams on new technology enablement including help ensuring robustness of technology platforms. Candidate must have the ability to prioritize well, communicate clearly, deliver solutions on time, and possess excellent data analysis & foundry interaction skills. The candidate expected to work across multiple facets of projects and juggle multiple responsibilities at the same time. The position is in Broadcom's Irvine facility in California. Responsibilities: Candidate will support IP and Chip teams with technology evaluation including reliability and design enablement. Responsibilities as part of technology evaluation will involve test structure layout, verification, extraction, simulation, and silicon evaluation. The job scope will include a) cross-functional quality assurance of designs and tape-outs, b) EDA & RCX tool quality and predictability, and c) custom device infrastructure readiness & robustness. Candidate will engage in collaborative team projects involving design, platform technology, and operations teams and foundry partner Qualifications: Advanced degree in EE, Material Science, Physics or related field with 10+ years of industry experience after MS or 7+ years after PhD with recent work in advanced FINFET (or GAA) nodes. 1. Strong background in advanced CMOS technology (FEOL, MEOL, BEOL) including understanding of design-technology interactions 2. Proficient in interacting with design teams and foundry partner 3. Familiarity with analog and digital design flows and CAD tools 4. Hands-on experience with device/circuit level test structure designs, verification (DRC, LVS), extraction, spice simulation, silicon characterization (DC/AC/RF) and data analysis 5. Extremely detail oriented with strong analytical, communication, and multitasking skills 6. Mix of hands-on and project management skills Additional Job Description: Compensation and Benefits The annual base salary range for this position is $127,100 - $203,400 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for 30 years. It's an outstanding legacy of innovation that's motivated by great technology-and outstanding people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. Join the NVIDIA Client Platform Engineering team and help empower engineers throughout the world developing pioneering products in AI, Automotive, VR, Gaming, Deep Learning, and High Performance Computing! See your efforts in action as developers use your platform to connect to the resources they need to be more productive. Shape the future of work by helping create the next generation client platform. As a Staff Client Hardware Engineer you will work in NVIDIA IT to lead initiatives focused on the client platform. You will apply knowledge of client hardware to craft a world-class service for all NVIDIA. We're looking for somebody who thrives on innovation and coming up with new ways of doing things to transform the user experience. What you'll be doing: Test, evaluate, and benchmark client hardware (laptops, desktops, custom builds) across diverse teams and specialized use cases. Automate hardware performance evaluation, compatibility checks, and reporting through scripted workflows and standardized tools using Git Workflows. Build and maintain scalable test environments for fleet-wide deployment, ensuring robust validation and repeatability for new equipment. Design hardware lab and testing solutions for engineering groups and development environments Cross functional partnership and development with a diverse landscape of teams. Support advanced issues on tickets that arise in your field. Recommend changes to policies and establish procedures that affect immediate organization What we need to see: BSEE, BSCS or equivalent degree (or equivalent experience) 8+ years of experience in Client Hardware Engineering Hands-on expertise in client hardware assembly, troubleshooting, and performance tuning for various vendors and custom requirements. Proficiency with automated testing frameworks, scripting languages (Python, PowerShell, etc.). Experience with benchmarking tools relevant to hardware evaluation. Experience designing, implementing, and supporting lab environments for enterprise-scale hardware assessment and continuous improvement Deep understanding of the foundational elements of Operating Systems Ways to stand out from the crowd: Sincere dedication to the end-user experience. Experience with mobile OS device management a plus Strong understanding of device driver management Experience with managing client platforms. Experience with enterprise print management NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you! #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 140,000 USD - 224,250 USD. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until December 8, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. ATE/SLT hardware team provides the interface hardware of IC package testing at final test and system level test. Hardware includes highly custom high-speed sockets, active thermal plungers, and load boards. Take an active role in hardware design for both product bring-up and HVM, design and manufacture improvement, and verification/debug, to production support. What you'll be doing: Review and approve the design of test socket, thermal plunger, and other accessories related to ATE/SLT IC testing for product bring-up and production. Provide ATE and SLT test fixture/HW solutions from design, manufacturing order, schedule monitoring, verification, and improvement. Drive ATE and SLT socket/thermal technology, solutions, and qualifications. Drive DOE with a sense of responsibility from collecting and analyzing engineering data and making decisions and recommendations for improvement. Provide cross-functional support. Drive a project and host a meeting internal and external stakeholders. Apply strong hardware troubleshooting and root-cause analysis. Possess the ability to provide preventive actions. Able to debug ATE/SLT hardware setup such as socket, thermal plunger, PCB, chiller, and handler. Require on-duty lab support. Weekend support may be necessary. What we need to see: Bachelor's degree or equivalent experience is required. EE and ME related degrees are preferred. 5 plus years of IC testing engineering and ATE/SLT hardware engineering experience. Having test socket knowledge is a strong plus. Familiar with test socket mechanics, footprints, and contact pins. Fully capable of understanding mechanical drawings and knowing mechanical and electrical circuit knowledge. Have IC testing knowledge of ATE/SLT interface hardware, maintenance, troubleshooting, and repairs. (Socket, load board, thermal plungers) Having ATE tester knowledge is a plus. Proven troubleshooting skills and ability to provide solutions and prevent reoccurrence. Willing to conduct hands-on-work such as socket pin repair, electric wire, and tiny capacitor/resistor. Able to lift 30 pounds load board during unboxing, boxing, and a short transportation. Have the knowledge of prevention and control of electrostatic discharge (ESD) With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers; we have some of the most forward-thinking and hardworking people in the world working for us and, due to unparalleled growth, best-in-class teams are rapidly growing. If you're creative and autonomous with a real passion for your work, we want to hear from you! Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 128,000 USD - 201,250 USD. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until November 18, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : You will be part of the NPI team within the Wireless Semiconductor Division (WSD) of Broadcom. Cross-functional with R&D Project teams, Product engineering, Quality and Reliability Engineering teams, Packaging team and suppliers. Support products from development stage to product release. Job scope and responsibilities Lead NPI engineering build plan and documentation/instruction to Contract Manufacturer release. Analyze demand and generate build plan as well as material supporting plan for engineering samples. Active interaction with suppliers to manage build process and material flow. PCB tape out logistic management and DRC process. Managing Wafer Backend(bumping dicing & TnR) processing vendor. Oversee overall engineering material supply from forecasting, tape out, order logistic and WIP monitoring. Communicate logistic status & lead activities to meet overall program objectives/supportability. Material planning and tracking for fast-paced projects inclusive of wafers, passive components and PCB. Develop and establish integrated system to drive work efficiency. Education & Experience Bachelor's degree in engineering field. At least 2+ years of working in manufacturing environment, semiconductor industry is a plus. Key qualification Experienced in manufacturing environment Able to collaborate with cross-functional teams to achieve project goal. Proactive communication skills & attention to details. Able to work in fast pace environment Demonstrate multi-tasking across different projects. Creative and strategic thinking in problem solving Additional requirements Master in Microsoft excel Additional Job Description: Compensation and Benefits The annual base salary range for this position is $81,000 - $130,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.