Design Verification Engineer jobs at MediaTek - 184 jobs

Company Qualcomm Technologies, Inc. Job Area Engineering Group, Engineering Group > GPU ASICS Engineering Qualcomm CDMA Technologies (QCT) is the world leader in wireless ICs powering the majority of 5G devices and is the largest fabless semiconductor in the world. QCT's Digital ASIC design team delivers cutting edge hardware and software products that power the user's experience and graphics content of the most advanced mobile devices on the market. Responsibilities Work with Architecture and Design team to understand the low power design features and create verification plan Develop test plan documents for the design features and get them reviewed with design team Develop verification components, testbench for low power verification and integrate third party VIPs/UVCs as required Create constraint random verification environment using System Verilog, UVM Follow company defined verification methodologies Perform Power Aware Verification in a random verification environment with embedded firmware running on the design Regress and close the required Low Power coverage metrics to ensure high quality design Create portable test setup, verification components that can be reused across simulation, emulation platforms Perform failure debug involving hardware software co-debug Work with tool vendors and push the methodology to improve the verification flows. System level RTL simulation & design verification. Support SoC DV for their integration verification, chip bring up and post silicon debug. Minimum Qualifications Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 6+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 5+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. Desirable Skills Bachelor's degree in science, engineering, or closely related field 5+ years of hands-on experience in System Verilog, OVM/UVM based constrained random verification. 5+ years in Design-validation/post-silicon-debug. 5+ years of hands‑on experience in developing verification components/UVCs, testbench for RTL verification. 5+ years of hands on testbench bringup, integrating third party VIPs, digital design, verification, debugging, and waveform debug. 3+ years of experience in UPF based Power Aware verification. 3+ years of experience in Functional coverage model development and/or code coverage closure. Preferred Skills MS degree in Electrical Engineering or equivalent; 8 years of practical experience Power Aware Emulation verification experience Hardware/Software Co-verification or embedded firmware verification experience is highly desirable Worked on Low Power coverage metrics collection and coverage closure Knowledge of GPU/CPU/DDR/Bus preferred Scripting skills using Python Formal verification experience (AND/OR) Low Power Formal Verification experience Equal Opportunity Employer Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability-accomodations@qualcomm.com or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). EEO Employer Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Pay range and Other Compensation & Benefits $195,200.00 - $292,800.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Join Qualcomm's design verification team in verifying the high‑speed mixed‑signal IP designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IoT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system‑level concept to tape‑out and post‑silicon support. Responsibilities: Define pre‑silicon and post‑silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post‑silicon validation. From scratch VIP development experience for Serdes controller + PHY is an additional plus. Required for this Role: Master's/Bachelor's degree in Electrical Engineering, Computer Engineering, or related field. 2+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications: Experience with Low Power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc. Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors. Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Equal Opportunity Employer Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Accommodations for Individuals with Disabilities If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm will provide an accessible process. Email disability-accomodations@qualcomm.com or call Qualcomm's toll‑free number for assistance. Pay Range & Other Compensation & Benefits $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants. In addition, our highly competitive benefits package supports your success at work, at home, and at play. Contact If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Qualcomm Technologies, Inc. - Engineering Group, ASICS Engineering. Qualcomm is a leading technology innovator focused on enabling next-generation experiences and transforming communication and data processing to create a smarter, connected future. The team is responsible for the complete verification lifecycle, from system-level concept to tape-out and post-silicon support. The position involves comprehensive pre-silicon test planning for digital power IPs, testbench development using SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Involve in developing automation to improve verification efficiency. Responsibilities • Complete verification lifecycle activities from concept to post-silicon support for digital power IPs. • Perform pre-silicon test planning, testbench development using SystemVerilog-UVM, coverage development, assertion modeling, and formal verification (property checking). • Learn and deploy power-aware UPF verification flow and methodology. • Develop automation to improve verification efficiency. Qualifications Bachelor's degree in Engineering, Science, or a closely related field 4+ years of experience with ASIC design and verification tools, techniques, and methodology Preferred Qualifications Master's degree in Computer Science, Electrical Engineering, Computer Engineering, or a closely related field 6+ years of experience with ASIC design and verification tools, techniques, and methodology 6+ years of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL 6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills 6+ years of experience with developing block-level testbench environment using SystemVerilog 6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification 6+ years of experience with scripting/automation skills using either Perl or Python Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable (not mandatory) Knowledge or experience with Assertion Based Formal Verification is desirable (not mandatory) Minimum Qualifications • Bachelor\'s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR • Master\'s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR • PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Additional Information Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may e-mail disability-accommodations@qualcomm.com or call Qualcomm\'s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to updates on applications or resume inquiries). EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including security requirements regarding protection of confidential information, to the extent permissible by law. Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00 The above pay scale reflects the broad range for this job code and location. Salary is one component of total compensation, which may include a discretionary bonus program and annual RSU grants. Our benefits package is designed to support your success at work, at home, and at play. Your recruiter can discuss details about Qualcomm benefits. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc.Job Area: Engineering Group, Engineering Group > ASICS Engineering As a leading technology innovator, Qualcomm pushes the boundaries to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, validate digital/analog designs and develop a comprehensive validation/verification testbench environment for projects that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions that meet performance, security, technology, and feature requirements. As a Design Verification Engineer, you will work with Chip Architects to validate the concepts of core and sub-system level micro-architectures. You will work on a selected part of the subsystem Design Verification to ensure that it functions to the standards of being launch ready for the end Product. Role and Responsibilities Work with subsystem and SOC Architects to understand the concepts and high-level system requirements. Develop detailed Test and Coverage plans based on the Architecture and Micro-architecture. Develop Verification Methodology, ensuring scalability and portability across environments. Develop Verification environment, including all the respective components such as Stimulus, Checkers, Monitors Assertions, and Coverpoints. Develop Verification Plans and Testbenches for your functional domain. Execute Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures. Track and report DV progress using a variety of metrics, including Bugs and Coverage. Preferred Qualifications Deep knowledge of APB/AXI/SPI protocols, handshake mechanisms, cross-clock domains and clock gating. Solid understanding of memory organization, fault-tolerant design, parity schemes, error detection and error correction schemes. Advanced techniques such as: Formal, Assertions, and Silicon bring-up, is helpful. In-depth knowledge of Micro-processor functions, Network-on-Chip Architectures, and Micro-architectures. Experience in writing Testplans, portable Testbenches, Transactors, and Assembly code. Experience with different Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Mixed signal Verification. Ability to develop and work independently on a Block/Unit of the design. Qualifications Minimum Experience Level should be 2+ years in SOC-level or core-level verification with good understanding of debugging either ARM-based or RISC-V based processors, good understanding of APB/AHB/AXI protocols. Must have solid understanding of SV/UVM concepts. Prior experience in any cryptographic algorithm is preferred. Must have basic understanding of UNIX commands and Python/Perl scripting Minimum Qualifications • Bachelor\'s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master\'s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm\'s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm, which also includes a discretionary bonus program and potential RSU grants. Our benefits package supports success at work, at home, and at play. Your recruiter can discuss details, and you can review more about US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > DSP Architecture and Design A variety of high performance, low power Hexagon/NPU cores are at the heart of Qualcomms multi-tier mobile SOC, Server, IoT, Automotive roadmap. The Hexagon architecture is designed to deliver performance with low power and area over a variety of applications like Audio, Modem, Machine learning, IoT and Automotive The successful candidate will verify the correct function, performance, and power characteristics of a new high performance, low-power Hexagon DSP/NPU processor core and associated subsystems, collaborate with digital architects and designers to develop verification plans, implement verification environments, and effectively execute verification strategies, with the following responsibilities: Responsible for owning a unit and/or subsystem verification environment through all stages of the verification process Responsible for working closely with architecture, design, and implementation teams to address the full spectrum of verification issues in modern design processes. Responsible for working with customers to which we deliver core IP to help them verify the integration of the processor core in larger components of an SOC Responsible for maintaining a current knowledge of industry trends and activities, and taking the steps necessary to make sure that Qualcomm is on the leading edge of the technology. Qualifications Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering 2+ year experience in digital design verification, including modern verification environments and techniques Detailed understanding of SystemVerilog Testbench verification environment is required. Excellent programming background and skills are required; in particular, a strong background in Object-Oriented programming. Preferred Qualifications Master\'s, Computer Engineering and/or Computer Science and/or Electrical Engineering 2+ year of experience in processor verification Knowledge of cache, memory coherency, interconnect, bus protocol, and processor integration is a strong plus Minimum Qualifications: Bachelor\'s degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 2+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master\'s degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 1+ year of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field. 2+ years of experience with high-performance microprocessor design. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm\'s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Pay range and Other Compensation & Benefits: $127,200.00 - $190,800.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants. In addition, our benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer. More details about our US benefits are available through the provided link. If you would like more information about this role, please contact Qualcomm Careers. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Senior Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network‑on‑Chip (NoC), and cutting‑edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal‑based verification environments at both block and SoC‑level to achieve first‑pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre‑Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities: Lead the verification of high‑speed Crypto, Network‑on‑Chip (NoC), cutting‑edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal‑based verification environments at IP and SoC‑level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion‑based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. Proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analysed and verified system‑level Performance and QoS (Quality of Service) requirements. Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including assertion and coverage‑driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high‑performance IP and/or VLSI designs is a plus. Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate‑level simulation, power‑aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. ACADEMIC CREDENTIALS: BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD/Xilinx programmable devices. THE PERSON: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware and firmware engineers to understand the new features to be verified Take ownership of block level verification tasks Define test plans, test benches, and tests using System Verilog and UVM Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes Review functional and code coverage metrics to meet the coverage requirements Develop and improve existing verification flows and environments PREFERRED EXPERIENCE: Strong understanding of computer architecture and logic design Knowledge of Verilog, system Verilog and UVM is a must Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification Working knowledge of C/C++ and Assembly programming languages Exposure to scripting (python preferred) for post-processing and automation Experience with gate level simulation, power and reset verification ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE Adaptive and Embedded Computing Group (AECG) seeks a Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high‑speed Crypto, Network‑on‑Chip (NoC), and cutting‑edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal‑based verification environments at both block and SoC‑level to achieve first‑pass silicon success. THE PERSON The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre‑Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities Lead the verification of high‑speed Crypto, Network‑on‑Chip (NoC), cutting‑edge DRAM Memory controller (LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal‑based verification environments at IP and SoC‑level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion‑based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. Preferred Experience Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Strong understanding of state of the art of verification techniques, including assertion and metric‑driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high‑performance IP and/or VLSI designs is a plus. Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate‑level simulation, power‑aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. Academic Credentials BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. #LI-CJ2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

Architects, designs, implements, verifies, and optimizes performance and power of GPU cores. Responsible for verification of Graphics IP, and performing pre- and post-silicon verification to verify correctness and ensure performance and power goals are met. Responsibilities Owning and executing on key independent tasks towards program requirements Using verbal and written communication skills to convey basic, routine factual information about day-to-day activities to others who are fully knowledgeable in the subject area. Working within prescribed timeline requirements and resource constraints Applying independent creative thought to troubleshoot technical problems or deal with novel circumstances. Research through available resources and engagement with various inter-disciplinary teams Using deductive problem solving to solve moderately complex problems; most problems have defined processes of diagnosis/detection; some limited data analysis may be required. Principal Duties and Responsibilities Applies Graphics knowledge and experience to architect, design, implement, and verify the structure and performance of GPU hardware, drivers, features, applications, and tools. Creates and maintains verification test benches and environments in System Verilog/UVM Create and leverage advanced testing frameworks to generate and recreate real-world system integration conditions Collaborates with Architecture, Software, Firmware, Design, Modeling, Emulation and Post-silicon validation teams to define and develop test methodology and content Participate in GPU architecture, micro-architecture reviews Collect, organize and execute various forms of system level test content including directed testcases, gaming benchmarks, standards compliance testsuites, and system level scenarios Build automation for continue integration and testing based on latest GPU IP Help collect and analyze test results using straightforward statistics and data predictions to track benchmarks and identify issues Works with team members to understand and align on narrow scope of feature development and meet targets. Write technical documentation and feature descriptions for straightforward projects under the direction of a supervisor. Minimum Qualifications Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. Preferred Qualifications 5+ years Hardware Engineering, Software Engineering, Systems Engineering, or related work experience Verification skills: Test planning, Scripting, Simulation, problem solving and debug. System Verilog, UVM, Verilog or VHDL, C/C++ skills required. Constrained random, Functional Coverage development, design debug experience required. Exposure to Emulation/Prototyping Platforms (Veloce, Palladium, Zebu, FPGA) Master's Degree in Electrical or Computer Engineering, Computer Science, or related field. 2+ years relevant GPU experience (either external or internal). Preferred Skills Experience in GPU based verification Experience in system or sub-system level verification Concurrency, Preemption, Stress testing frameworks Testbench Architecture and Implementation GFX API Exposure : Vulkan/DX11/DX12 Exposure Scripting and automation skills (Python, Make, Airflow etc) Embedded FW Development and Debugging Benchmarking and Performance Analysis Windows and/or Linux OS Kernel Architecture C/C++, GNU Toolchain, Visual Studio Formal verification - FPV and DPV experience is a plus Experience with emulation/prototyping/hybrid build and execution flows (Veloce, Palladium, Zebu, Protium, HAPS, qemu) Development of synthesizable transactors, monitors, scoreboards for emulation platforms Embedded FW and/or Kernel level development and debugging skills (C/C++, Makefile, gdb, uboot, uefi, kernel-mode drivers) This role is available in multiple locations at different levels. The compensation range will be determined upon the offer location and title. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may omail disability-accomodations@qualcomm.com for accommodations. Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Pay range and Other Compensation & Benefits: $161,800.00 - $273,400.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is one component of total compensation; Qualcomm also offers a discretionary bonus program and RSU grants. For more details about US benefits, see the internal benefits information. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering Design Verification Role: Familiarity with RTL design in Verilog and System Verilog Develop verification methodology, ensuring scalable and portable environment across simulation and emulation. Develop test plan to verify hardware building blocks, design macros and standard interfaces (PCIE, DDR, USB, I2C, SPI, etc). Own end to end DV tasks from coding test benches and test cases, write assertions, run simulations and achieve all coverage goals Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches Develop verification methodology, ensuring scalable and portable environment across simulation and emulation. Develop and maintain emulation environment to collect metrics related to emulation environment. Location: Need to be in San Diego full time, 5 days a week Security: Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. Must be a U.S. citizen and eligible to receive a U.S. Government security clearance Required Qualifications: 5+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture 5+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flows Relevant experience of 5+ yrs in any of the mentioned domain - Design/Verification/ Implementation Preferred Qualifications: One or more of the following preferred: Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc. Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology Good understanding of chip-level functional model building Good understanding of OOP concepts; experience in HVL such as System Verilog, UVM/OVM & System C Knowledge of Behavioral and Structural models and familiarity with simulation environments Experience customizing and debugging make-based build flows and working with Xilinx's Vivado tools Experience with cm tools such as Git and Gerrit Experience in formal / static verification methodologies will be a plus Experience with emulation platforms - Palladium, Zebu, Veloce, FPGAs Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog Experience with C/C++ DPI transactors and monitors Develop and maintain emulation environment to collect metrics related to emulation environment. Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors. Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Experience with debugging tools such as JTAG and lab test equipment such as logic analyzers, oscilloscopes, signal generators, etc. Experience with GLS, and scripting languages such as Perl, Python is a plus Linux OS proficiency Ideal candidate: The ideal candidate would be a self-starter with strong initiative, discipline, motivation, and a focus on quality. The candidate must be a team player and be flexible and open to a variety of task assignments within the team. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR • Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR • PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. EEO and Compliance: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Pay range and Benefits: $147,600.00 - $246,000.00 The pay scale reflects the broad, minimum to maximum, for this job code and location. Salary is one component of total compensation; Qualcomm offers a competitive annual discretionary bonus program and potential RSU grants, plus a comprehensive benefits package. Your recruiter can share more details. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

A leading technology company is seeking a Design Verification Engineer based in San Diego. The role demands strong RTL design skills in Verilog and System Verilog, along with experience in design verification methodologies. Candidates should have at least 5 years of experience in the field and a relevant degree. The position offers a comprehensive benefits package and a competitive salary range of $147,600 to $246,000, alongside various bonuses and stock options. #J-18808-Ljbffr

Qualcomm is a global leader in wireless technology, driving innovation and shaping the future of connectivity. We are looking for talented and motivated individuals to join our team in San Diego, to contribute to cutting-edge projects and help us continue to lead the industry. Role Overview As a CAD Engineer specializing in design verification (DV), you will play a crucial role in (1) developing automation tools and flows for DV, (2) enabling state of the art EDA tools for Qualcomm DV teams, (3) exploring and applying the latest ML/AI technologies to improve DV workflow. You will also be responsible for creating comprehensive documentation, providing support to internal teams, and ensuring the efficiency and reliability of our automation processes. Key Responsibilities Apply engineering principles to develop and optimize CAD tools and flows to enhance productivity, efficiency, and results. Conduct research to stay updated with the latest industry trends (including ML/AI technologies) and incorporate new learnings into Qualcomm workflow. Provide technical support and training to internal teams on CAD automation tools and workflows. Collaborate with cross-functional teams to identify and implement improvements in automation processes. Propose and execute innovative solutions to complex problems, contributing to the continuous improvement of our CAD automation capabilities. Personal Character Traits Analytical: You possess strong analytical skills, enabling you to understand complex systems and identify areas for improvement. Resourceful: You are adept at finding creative solutions to challenges and are not afraid to think outside the box. Self-Motivated Learner: You are proactive in acquiring new knowledge and skills through self-guided research, training, and asking insightful questions. Problem Solver: Over time, you develop the ability to tackle higher-level problems, propose effective solutions, and execute decisions independently. Collaborative: You work well with others, sharing knowledge and supporting team members to achieve common goals. Qualifications for this Role Bachelor's degree in computer science or electrical engineering 2+ years of ASIC design, verification, validation, or related work experience Strong programming skills in languages such as Python, TCL, GNU Make and Perl Experience with DV EDA tools such as VCS, Xcelium and Questa Preferred Qualifications Master's degree or PhD in Computer Science or Electrical Engineering 5+ years of ASIC design, verification, CAD or related work experience Familiar with ML/AI techniques Experience in developing VLSI automation flows Knowledge of Hardware Description Languages like SystemVerilog Preferred Qualifications (Additional) Plus: Data science, ML/AI, VLSI CAD experience Minimum Qualifications Minimum qualifications include a Bachelor's degree or higher with related ASIC design/verification experience, or an equivalent combination of education and experience as specified by the job posting. For example: Bachelor's degree in Science, Engineering, or related field with 4+ years of relevant experience; or Master's degree with 3+ years; or PhD with 2+ years. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may provide disability accommodations via email or by calling Qualcomm's toll-free number. Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Pay range and Other Compensation & Benefits $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation. Qualcomm also offers a competitive annual discretionary bonus program and RSU grants. We also offer a comprehensive benefits package. Your recruiter can discuss details about Qualcomm benefits. For more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

A leading technology firm based in San Diego seeks an experienced ASIC Design Verification Engineer to verify high-speed mixed-signal IP designs. The ideal candidate has a degree in Electrical Engineering and at least 2 years of relevant experience. Responsibilities include defining testplans and developing testbenches using SystemVerilog/UVM methodologies. Competitive salary range of $140,000 - $210,000 with comprehensive benefits including bonuses and RSU grants. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE As a member of the AMD, you will help bring to life cutting‑edge designs and deliver IPs to SOC. As a member of the front‑end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first‑pass silicon success. THE PERSON You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem‑solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi‑site environment are keys to being successful in this role. KEY RESPONSIBLITIES RTL design of high speed design, clock/reset/power features, IP Integration, sub‑system level design Architect and design of power management features. Design optimization for implementing power efficient IP, implementing the RTL using low power techniques Responsible for the inter‑IP integration issues resolution Own the Clock‑Domain crossing, Linting aspects of the overall design of the IP and the subsystem Work closely with FEINT, DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Architecting, micro‑architecting and documentation of the design features Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. REFERRED EXPERIENCE Extensive experience in Digital IP/ASIC design and Verilog RTL development Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification Well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects. Should possess expertise in front‑end EDA tools sign‑off and its flows Familiarity with low power design and low power flow is an added plus Ability to program with scripting languages such as Python or Perl is a plus Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements Proven interpersonal skills, leadership and teamwork Excellent writing skills in the English language, editing and organizational skills required; Skilled at prioritization and multi‑tasking Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts Knowledge of, or experience in, functional design verification or design is highly desired ACADEMIC CREDENTIALS Bachelors or Masters degree in computer engineering / Electrical Engineering This role is not eligible for visa sponsorship. LOCATION: Santa Clara, CA Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading semiconductor company in Santa Clara, CA, seeks a skilled digital design engineer. The role involves RTL design, power management features, and collaboration across teams. Candidates should have strong Verilog skills and experience in IP design. A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required. This position offers an opportunity to be part of a company that values innovation and teamwork, but it is not eligible for visa sponsorship. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE AMD is looking for a Senior ASIC/RTL Design Engineer to contribute to the development of large SoCs, featuring multiple physical blocks and complex timing constraints. The candidate's responsibilities will include RTL ownership and integration, building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred. THE PERSON The ideal candidate demonstrates high energy, excellent written and verbal communication skills, and a structured, organized approach to work. They are collaborative and strongly focused on achieving team and organizational goals. KEY RESPONSIBILITIES Responsible for RTL design and integration. Contribute to all aspects of SoC design including chip definition, architecture development and modeling, development of micro-architectural specification, conversion of micro-architectural specifications to logic implementation, verification, emulation, debug, synthesis and timing closure. Develop complex multi-mode/multi-corner timing constraints that are compatible for RTL and signoff. Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency. Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA (static timing analysis) checks. Collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows. Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts). Continuously review and identify areas for process improvements and early issue detection during the design phase. PREFERRED EXPERIENCE Experience with SoC designs that includes RTL design and integration. Worked with EDA tools that enable RTL quality checks. Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Ability to multitask, grasp new flows/tools/ideas. Experience in improving the methodologies. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT). Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters. Strong analytical and problem-solving skills. ACADEMIC CREDENTIALS Bachelor's or Master's degree in Electrical Engineering or Computer Engineering LOCATION San Jose This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

A technology company in San Jose is seeking a Senior ASIC/RTL Design Engineer to contribute to the development of large SoCs. The role requires expertise in RTL ownership, complex timing constraints, and EDA tools, alongside strong communication skills. Candidates should have a Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. This is a non-remote role requiring in-person presence, and does not offer visa sponsorship. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering As a leading technology innovator, Qualcomm pushes the boundaries to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, validate digital/analog designs and develop a comprehensive validation/verification testbench environment for projects that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions that meet performance, security, technology, and feature requirements. As a Design Verification Engineer, you will work with Chip Architects to validate the concepts of core and sub-system level micro-architectures. You will work on a selected part of the subsystem Design Verification to ensure that it functions to the standards of being launch ready for the end Product. Role and Responsibilities Work with subsystem and SOC Architects to understand the concepts and high-level system requirements. Develop detailed Test and Coverage plans based on the Architecture and Micro-architecture. Develop Verification Methodology, ensuring scalability and portability across environments. Develop Verification environment, including all the respective components such as Stimulus, Checkers, Monitors Assertions, and Coverpoints. Develop Verification Plans and Testbenches for your functional domain. Execute Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures. Track and report DV progress using a variety of metrics, including Bugs and Coverage. Preferred Qualifications Deep knowledge of APB/AXI/SPI protocols, handshake mechanisms, cross-clock domains and clock gating. Solid understand of memory organization, fault-tolerant design, parity schemes, error detection and error correction schemes. Advance techniques such as: Formal, Assertions, and Silicon bring-up, is helpful. In-depth knowledge of Micro-processor functions, Network-on-Chip Architectures, and Micro-architectures. Experience in writing Testplans, portable Testbenches, Transactors, and Assembly code. Experience with different Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Mixed signal Verification. Ability to develop and work independently on a Block/Unit of the design. Qualifications Minimum Experience Level should be 2+ years in SOC-level or core-level verification with good understanding of debugging either ARM-based or RISC-V based processors, good understanding of APB/AHB/AXI protocols. Must have solid understanding of SV/UVM concepts. Prior experience in any cryptographic algorithm is preferred. Must have basic understand on UNIX commands and Python/Perl scripting Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. #J-18808-Ljbffr

A leading tech company in Silicon Valley seeks a Staff Silicon Design Verification Engineer. In this role, you will lead verification efforts for advanced designs including high-speed Crypto and DRAM Controllers, utilizing cutting-edge technologies. Ideal candidates will have strong leadership skills, a background in verification methodologies, and experience with UVM and simulation tools. This position offers opportunities for professional growth and impacts the future of computing, aiming for first-pass silicon success. #J-18808-Ljbffr