Microchip Technology jobs in Roseville, CA - 80 jobs

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: Microchip's Data Center Solutions Business Unit (DCS) delivers industry leading performance, reliability, and security in Storage Controllers, Memory Controllers, NVMe SSD Controllers, PCIe Switches and SAS Expanders that are applied in Cloud Storage and Compute Data Centers, and Storage Area Networks. As a System Validation Engineer, you will join a group of world class talented system integrators responsible for the bring-up, integration and validation of cutting-edge System on a Chip (SoC) products for the Data Center Solutions Business Unit. Job Responsibilities The responsibilities include but are not limited to: * Integrating prototype SOC HW and FW into a complete solution. This includes working with emulation platforms, proto-ICs, validation boards, FW and SW to bring an entire system level solution to life and enable functional testing and FW development. * Develop, execute, and document a series of feature tests that will fully validate the operation of the SoC and its various functional HW blocks and FW to ensure all components and the overall SoC is functioning per design specs, achieves * expected performance and meets industry requirements and standards. * Working with pre-silicon FGPA based emulation platforms and prototype (post-silicon) ICs/SOCs. * Architecting, building and maintaining validation infrastructure through the development of boards, FPGAs, embedded software, device drivers and test bench scripts. * Developing block, subsystem and system level test FW and scripts, and further integrating them in to best-in-class test automation suites. * Leading small technical team activities in area of expertise. * Architecting comprehensive test plans for area of expertise. * Leading complex test execution and conducting investigations in a lab environment on-site and remotely. * Finding and reporting bugs. Working with cross-expertise teams and leading efforts to isolate, investigate and solve them. * Learning and dynamically applying knowledge of the device, system, protocols, and industry standards. * Help grow and train the validation team. * Effectively presenting technical information to internal and external groups. The role and responsibilities will grow with the individual candidate's skills and interests. Requirements/Qualifications: * Bachelor's or Master's degree in Computer Engineering, Electrical Engineering or Computer Science. * 10+ years of relevant industry experience. More junior applicants will be considered for other levels. * Experience leading a small technical team. * Experience in IC and SoC validation. * Experience working with prototype ICs, boards and HW infrastructure. * Experience working in a lab environment and knowledge of relevant test equipment and protocol analyzers. * Experience in debug and investigation of SoC's using FW and MIPS debug environment. * Strong knowledge of digital system and computer architecture. * Strong knowledge of Data Communication and Digital Design theory. * Strong knowledge of scripting language such as Python or Tcl/Tk, proficiency in C/C++ programming. * Demonstrated strong analytical and problem-solving skills. * Experience in defining comprehensive test coverage at sub-block and system level, utilizing design specification, feature requirements and industry standards. * Ability to develop and execute functional validation plans and necessary validation software and scripts. * Knowledge of PCIe system architecture and protocol. Ability to read and analyze PCIe protocol traces. * Experience in PCIe and/or DDR validation. * Familiarity with CXL, DDR, I2C, SPI protocols is an asset. * Experience testing and debugging high-speed SERDES. * SoC performance validation and performance tuning experience is an asset. * Hands-on hardware experience with x86 based systems. * Experience working in Linux and Windows based OS environments. * Thorough knowledge of circuit theory and high-speed signal fundamentals. * Ability to quickly learn new technologies, protocols and standards. * Comfortable working with developing specs and standards. * Team player working well with peers and cross-functional groups. * Strong communications and interpersonal skills. Desired Qualifications: * Familiarity with FPGA based emulation environments - deployment of test coverage for pre-silicon test is an asset. * Experience in high-speed digital designs, board designs, PCB layouts, signal integrity concepts and manufacturing process is an asset. * Past experience developing and debugging MIPS based architecture. Programming FW in C/C++ * Working knowledge of protocols like: PCIe, CXL, DDR, NVMe, ONFI, SAS, SATA I2C, SPI and protocol trace debugging. * In depth Linux OS architecture and driver knowledge. * Linux or Windows host driver development. * Knowledge of FPGA layout tools and VHDL/Verilog coding. * Threadx or RTOS knowledge. Travel Time: 0% - 25% Physical Attributes: Handling, Hearing, Seeing, Talking, Works Alone, Works Around Others Physical Requirements: Regular business hours. 70% sitting, 15% standing, 15% walking Pay Range: We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below: Benefits of working at Microchip The annual base salary range for this position, which could be performed in the US, is $75,000 - $232,000.* * Range is dependent on numerous factors including job location, skills and experience. Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster. To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Job Details:Job Description: About SPEO Supply Chain Product Enabling and Operations (SPEO) creates an environment where employees can prosper while enabling the innovative product data designs that make amazing possible. Our business architect scope spans across Intel's Silicon, Systems and Boards, and Software product portfolios, from the earliest phases of product design and technology development through delivery of product and service to customers. SPEO approaches Diversity and Inclusion with the same rigor, accountability, and visibility as our critical business strategies, embedding diversity and inclusion practices in everything we do. We are a global workforce that generates diversity of thought and innovation, resulting in better overall business results. SPEO values and embraces individual uniqueness and empowers employees to bring their whole selves to deliver their very best. Position Overview Join the SPEO Business Architect and Analyst Team leading product data design for Intel's leading-edge products and large scale transformations. Help create the next generation of product data designs that will shape the future for decades to come. This role offers the opportunity to work on transformative solutions that keep pace with Intel's rapidly changing product landscape while ensuring alignment to industry standards and optimal use of Intel's PLM capabilities. Key Responsibilities BOM Design Collaboration: Collaboratively influence Bill of Materials (BOM) design options for Intel's existing and future products, ensuring solutions align to industry standards and leverage Intel's PLM capabilities effectively. Silicon Product Support: Work with planners and product teams to develop and set-up Silicon BOMs supporting planning and execution of Intel's silicon products from Fab to finished goods. Scenario Planning: Conduct scenario "what-if" planning for engineering processes, inventory, and/or ordering strategies when necessary. Issue Resolution: Influence and recommend issue resolution strategies in supply chain areas using data-driven decision making across key stakeholders and management levels. Continuous Improvement: Drive continuous process and project improvements across supply chain operations. Product Data Architecture: Distill product data requirements and translate into designs, business interaction models, workflows, and business processes for large scale transformative solutions, ensuring seamless hand-off for execution and adoption. Qualifications: The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications US Citizenship is required. Bachelors of Arts or Bachelors of Science Degree. 5+ years of experience in one or more of the following areas: Supply Chain: Supply planning, procurement, logistics, inventory management, demand planning. Business Administration: Supply chain operations management, process improvement, business analysis. Information Management: Data management, systems analysis, data analysis. Related fields: Manufacturing operations, product management, change management. Preferred Qualifications Master's Degree in Supply Chain, Business Administration, or related field of study. Experience with Project and Product Life Cycle principles. Experience with Intel planning systems and internal processes. Experience with Oracle Cloud PLM, SPEED, and SAP systems. What We Offer Opportunity to shape the future of Intel's product data designs for decades to come. Work on leading-edge products and large-scale transformations across Silicon and Software portfolios. Inclusive environment that values individual uniqueness and empowers employees to bring their whole selves to work. Career development opportunities within a global, diverse workforce. Chance to drive continuous improvement in supply chain operations and processes. Ready to help create the next generation of product data designs? Apply today and be part of Intel's transformative journey. Job Type:Experienced HireShift:Shift 1 (United States of America) Primary Location: US, California, FolsomAdditional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, HillsboroBusiness group:The Corporate Planning Group (CPG) is the strategic heartbeat of Intel, acting as catalyst for innovation and transformation, guiding the company towards achieving its vision and maintaining a competitive edge in the marketplace. CPG exists to build a comprehensive operating plan that leverages internal and external manufacturing for Intel's growth. We emphasize data-driven innovation and results, ensuring we meet customer demands and financial targets. Join CPG to be part of a forward-looking group that is not just planning for tomorrow, but redefining it.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $107,990.00-214,440.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: In this high-profile role, the Lead IP/SOC Verification will be the overall design verification lead for next generation graphics program. You will work across all of engineering and business to meet overall verification needs THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. * Good understanding of requirements management, documentation management, and defect management * Ability to grasp concepts during discussions and turn minutes into action items * Able to communicate concepts and processes with stakeholders * Analytical, self-motivated, organized, detailed-oriented and results-oriented * Excellent interpersonal skills including the ability to work well with multiple people and teams, ability to communicate progress to team members on a regular basis * Experience working in a high-pressure environment and competing priorities and tight turnaround times KEY RESPONSIBLITIES: * Closely work with designers and architect to come up with features, verification and execution plans * Own and lead verification quality for GFXIP projects * Engage with IP and SOC teams to drive closure to verification strategy * Working with architects and verification leads and driving quality test plan specifications. * Collaborate with architects, hardware engineers, and firmware engineers to understand the complex features and impact to System level/SOC environment * Developing verification strategy, infrastructure and needed improvements * Driving Pre and post Si verification closure to meet schedule with quality * Leading Post Si verification activities to drive triage with FW, SW, IP, SOC and various teams. Plug holes appropriately to improve quality of the IP * Working with each domain (sub-system) lead and guide them to get better quality and verification outcome * Automating workflows in a distributed compute environment * Helping management with risk assessment on features, quality, and schedules * This individual will work with engineering management to drive execution excellence, including key metrics - performance, schedule, cost, quality * Plan, Execute, Verify and Track new features at IP and SoC level * Desire and enthusiasm to grow into leadership role taking progressive responsibility over time * Aspiration to grow to technical lead responsible for project level design verification * Defines, plans and drives projects and program plans based on management and senior technical guidance * Possesses specialized knowledge plus a broader technical knowledge in areas outside his or her area of expertise * Has responsibility for projects or processes of significant technical importance and for results that cross engineering project areas * Initiates significant changes to existing processes and methods to improve project and team efficiencies PREFERRED EXPERIENCE: * Experience focused on IP and/or SOC verification with successful completion of multiple ASICs that are in production * Prior experience in Graphics domain is highly beneficial, though not a requirement * Requires proven track record in technical leadership. This includes planning, execution, tracking, verification closure, and delivery to programs. * Requires strong experience with development of UVM, SystemVerilog, C/C++ and Scripting Languages * Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification * Good understanding of code and functional coverage, ability to influence coverage improvement with design and verification teams * Experience with Processor based SoC verification and understanding of at least one ISA is a plus * Experience with gate level simulation, power verification, reset verification, abstraction techniques is a plus * Experience with Agile methodology, JIRA and Confluence ACADEMIC CREDENTIALS: * Undergrad degree required. Bachelor, Master's or PhD degree in Electrical or Computer Engineering preferred. This role is not eligible for Visa sponsorship. #LI-BM1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

**Do Something Wonderful!** Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. **Who We Are** This role offers an exciting opportunity for individuals to gain exposure and contribute to the overall Intel strategy through supporting mergers, acquisitions, divestitures, and/or special strategic projects. The Mergers and Acquisitions (M&A) Accounting Manager position will be a member of the M&A and ICAP Accounting team, part of the broader Corporate Accounting group and Chief Accounting Office. This is a dynamic, high impact role that will entail both technical accounting and project management work, the mix of which will vary on a deal-by-deal and project-by-project basis. In this role, candidates may perform the following: + Own integration/disintegration activities pertinent to Finance, which may include project management for CAO organization, detailed functional area work needed to support deals, and working with stakeholders across Intel. + Quickly synthesize disparate information surrounding the transaction or strategic project to identify accounting opportunities/risks/issues, then create and drive solutions. + Act as the key accounting point person for stakeholders inside and outside of Intel, developing a deep understanding of the key processes, accounting infrastructure, and practices to drive good decision making. + Lead the design and implementation of carve out financials, TSA services, integration/disintegration of key areas as determined necessary for the deal. + Manage month-end close processes and acquired/divested legal entity transition plans ensuring financial integrity and compliance is maintained. + Manage cross-functional strategic projects from end-to-end, driving results through others and holding the team accountable to established milestones. + Perform accounting research on complex technical issues. **Who** **You Are** The candidate will partner with organizations within and outside of Intel and must have a proven success record of thriving in cross-functional, ambiguous environments. To be considered for this position, candidates must have a solid understanding of US GAAP accounting rules, have a proven track record of problem solving in a high-pressure environment, and have demonstrated strong communication and influence with the highest levels of management. Desired skills include but not limited to: + Acquisition, integration, restructuring or divestiture experience a plus, + Excellent project and stakeholder management skills to drive projects to timely completion, + Strong, concise communication skills (written and oral) upward and across organizations, + Problem solving mindset with One Intel approach, + Knowledge of US GAAP/SEC reporting and accounting requirements, as well as guidelines and policies - which may include statutory and/or legal entity accounting, + Strong knowledge of finance information systems, specifically SAP and transaction flows, is a plus, + Ability to network across and outside of finance, including Corporate Development, Global Supply Chain, IT, Global Tax, Legal, etc. + Candidate must be able to work independently and manage through ambiguity in complex and changing environments, + The ability to be flexible and work in a fast-paced environment to develop and implement solutions to complex problems, + Public accounting and/or valuation experience is useful. Prior experience working on large multi-national transactions or strategic projects is beneficial **Qualifications:** You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. **Minimum Qualifications** + Bachelor's Degree in Accounting/Finance with 4+ years of relevant experience -OR- Master's Degree in Accounting/Finance with 3+ years of relevant experience + CPA or equivalent certification + 3+ years of public accounting and/or valuation experience **Preferred qualifications** + Experience in acquisition, integration, restructuring or divestiture + Excellent project and stakeholder management skills to drive projects to timely completion. + Knowledge of US GAAP/SEC reporting and accounting requirements, in particular ASC 805 and ASC 810. + Knowledge of ERP systems, specifically SAP and transaction flows. + Ability to network across and outside of finance, including Corporate Development, Global Supply Chain, IT, Global Tax, Legal, etc. + Prior experience working on large multi-national transactions or strategic projects. **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Oregon, Hillsboro **Additional Locations:** US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara **Business group:** Join Intel's Finance Group, a key player in driving strategic business decisions that enhance shareholder value. Our team is dedicated to facilitating change and improvement across finance and the operations we support. As strategic partners, we lead acquisitions and inorganic growth initiatives, managing transactions from ideation to completion while serving as trusted advisors to executive leadership. Additionally, we enhance employee experiences by maintaining Intel sites globally and advancing environmental sustainability efforts. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $116,160.00-234,200.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ TEAM: AMD is searching for a dynamic, motivated self-starter, who is passionate about automation, solving problems, and reaching goals. You will be joining the Server Software Automation team to take our Server Automation testing to the next level. RESPONSIBILITIES: · Planning, designing, and developing Automation framework and infrastructure. · Closely interact with Senior Engineers on the team for design, development and debugging for your project · Analyzing and working on Azure Cloud products to implement Server Automation infrastructure. · Accountable on time delivery of deliverables. · Has accountability for results in a particular area of work. · Attend weekly meetings, status communication, presentations to the team Requisition Number: 186886 Country: United States State: California City: Roseville Job Function: Student/ Intern/ Temp Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

Silicon Engineering Group (SiG) plays a critical role in Intel's mission to create world-changing technology. Our engineers work on next-generation processor architectures that define the future of computing, from mobile devices to high-performance computing systems. We're pushing the boundaries of what's possible in silicon design while maintaining Intel's leadership in semiconductor innovation. We are actively seeking a talented CPU Core Logic Designer to join our dynamic team. This role offers the opportunity to work on cutting-edge processor designs that will shape the future of computing technology. This role's responsibilities include but are not limited to: * Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs. * Participates actively in the definition of architecture and microarchitecture features of the CPU being designed. * Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. * Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. * Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure high quality integration of the CPU block. Qualifications: You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: * Bachelor's degree in Electrical/Computer Engineering or Computer Science or related field and 6+ years of experience - OR - a Master's degree in Electrical/Computer Engineering or Computer Science or related field and 4+ years of experience. * 4+ years combined experience in: * System Verilog/Verilog/VHDL and/or VCS or similar Simulator * Logic design and/or front end. * Computer architecture and microarchitecture. Preferred Qualifications: * 4+ years of experience with: * Software/programming languages (i.e. C, C++, C#, Visual Basic/.NET. Perl, Python, Java, etc.). * Modern energy-efficient/low-power logic design techniques, including those specifically applicable to high frequency optimization. * Knowledge of Intel Architecture ISA and system architecture, including x86 assembly language. * Experience with high speed circuit design and optimization for Datapath, circuits and/or arrays. * Familiarity with circuit planning and timing convergence. * Experience working with cross functional teams (Architecture, Spec development, Design, Formal, Verification). Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Folsom Additional Locations: Business group: The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Intel is seeking an exceptional, business-minded attorney to join our Commercial Legal team, which supports Intel's business units that design and deliver cutting-edge semiconductor products, software, and technology solutions for the PC, data center, networking, edge and AI market segments. As a key member of our Legal team, you will partner directly with senior executives, engineering leads, product managers, and commercial stakeholders to provide legal advice and structure, draft, and negotiate high-impact agreements that enable our innovation and go-to-market strategies. We are looking for a lawyer who thrives on complexity, can lead sophisticated transactions, and enjoys working collaboratively in a fast-paced environment. This position offers the opportunity to influence Intel's most strategic initiatives and shape the future of technology. Key responsibilities include but are not limited to: * Lead drafting, structuring, and negotiation of a wide range of agreements, including: technology collaboration agreements, inbound and outbound technology and IP licenses, optimization and ecosystem enablement agreements, and software license and SaaS agreements. * Advise cross-functional teams on product strategy, development cycles, commercialization, and risk management. * Provide strategic counsel on a broad range of legal issues, including IP ownership, licensing frameworks, confidentiality, antitrust, privacy, export controls, and pre-litigation matters. * Serve as a trusted advisor to senior business leaders, delivering clear, practical, and business-oriented legal guidance. * Collaborate across Intel's legal and business teams to drive solutions that enable growth and manage risk. Qualifications: You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. This position is not eligible for Intel's immigration sponsorship. Minimum Qualifications * J.D. from an accredited law school and membership in good standing with a state bar * 5+ years of experience in commercial, technology, and product-related transactions Preferred Qualifications: * Significant in-house experience at a leading technology company. * Proven ability to lead and execute sophisticated technology transactions, including technology/IP licensing, custom silicon/ASIC deals. * Exceptional negotiation, drafting, communication and stakeholder-management skills. * Strong business acumen and judgment, with the ability to influence senior stakeholders. * Expertise in technology transactions and familiarity with semiconductor industry dynamics. * Demonstrated ability to balance legal risk with business objectives and communicate clearly with both legal and non-legal audiences * Highly collaborative team player with a positive, solutions-oriented approach. * Ability to work independently in a fast-paced environment while maintaining high-quality results Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro Business group: Intel's Corporate Affairs, Policy, Integrity, Trade, and Legal (CAPITL) group offers unique opportunities to work in a variety of areas, including counsel to Intel businesses; technology and intellectual property licensing; patent prosecution; trademarks and brands; litigation, mergers, acquisitions and investing; public policy, legislative and regulatory lobbying; global trade, export, import, and customs; and corporate compliance. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $152,830.00-318,650.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

The Cost and Inventory GPO team within Corporate Accounting Office is responsible of the design and execution of Intel's inventory processes. We are amid a tremendous amount of change and this role will play a big part into defining and designing the future state of how we operate within Cost and Inventory. As we continue Intel's biggest transformation into our IDM 2.0 Foundry model, the GPO team is designated to identify, design, and deliver Cost and Inventory capabilities and processes to meet new business needs. This is an exciting opportunity to be front and center as we enable Intel's future. _Key Responsibilities:_ The IAO Cost and Inventory Accounting Projects Analyst is a key role within the Cl Global Process Owner group responsible for: _ERP Support:_ + Lead, review, and provide inputs for the next generation (SAP) cost and inventory system, specifically related to Intel Products and Intel Corporation: + Business Process design + Functional design spec + Functional unit test + Cutover plan + Price - Cost Test + Provide inputs to: + Process flows, Solution Design Decision, Security roles, and Change Impacts + Integrate the Demand Planning process/output, Spending Forecasts, and Intel Products Standard Cost modeling into the new ERP costing system + Prepare and execute + User Acceptance testing _Merger and Acquisition Accounting Support:_ + Develop Inventory and Cost Of Sales positions for Merger and Acquisition (M and A) related projects. + Support M and A team and other stakeholders with Inventory information related to plant codes, locations, movements, and reconciliations related to M and A Projects. + Where M and A Projects require a change to Cost and inventory Processes, align with stakeholders across Intel to design and implement changes to the Cost and inventory processes. + Act as a liaison between the accounting organizations and the Costing technical team to implement any system changes that may be necessary for the given project. + Post or Approve Journal Entries related to project activity. + Responsible for inventory and cost of sales reconciliations. The ideal candidate will have the following behavioral traits: + High tolerance for ambiguity: Comfortable with ambiguous or uncertain situations and have an ability to operate effectively in an uncertain environment by considering a range of creative solutions or options. + Problem-solving: Identify breakdowns, analyze potential causes, create innovative solutions. IAO is fast moving and dynamic environment. + Subject Matter Expertise: Deep understanding of Cost and Inventory subject matter along with Operation finance supporting factories or Business Unit to help identify pain points and critical needs. + Stakeholder management and Business Partnering: Build strong relationships with stakeholders and operational teams to align priorities, synchronize plans, lead, and engage the right experts to design across functions, and influence recommended changes to optimize solutions. + Influencing: This role is individual contributor but also will work through others in the org as we build this capability. Must be comfortable with ambiguity. + Communication skills: Skills to effectively communicate across multiple stakeholders including finance, IT, accounting, audit, legal, and other stakeholders. Skills to present concise and impactful messages to senior leaders. **Qualifications:** Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. This position is not eligible for Intel's immigration sponsorship. **Minimum Qualifications** + Bachelor's degree in Accounting, Finance, Business Administration, or related field. + 2+ years of experience working with costing or standard costing systems (e.g SAP S4) + 4+ years of experience with finance systems and processes. **Preferred Qualifications** + Basic Experience or knowledge of Intel's manufacturing processes. + Experience with SAP inventory management systems + Advanced English level: verbal, writing and reading. **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Oregon, Hillsboro **Additional Locations:** US, California, Folsom, US, California, Santa Clara **Business group:** Join Intel's Finance Group, a key player in driving strategic business decisions that enhance shareholder value. Our team is dedicated to facilitating change and improvement across finance and the operations we support. As strategic partners, we lead acquisitions and inorganic growth initiatives, managing transactions from ideation to completion while serving as trusted advisors to executive leadership. Additionally, we enhance employee experiences by maintaining Intel sites globally and advancing environmental sustainability efforts. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $97,210.00-195,980.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

About Intel Foundry Services Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. Position Overview The IP Alliance Manager plays a critical role in building and managing Intel Foundry's IP ecosystem, establishing strategic partnerships with IP vendors to create a comprehensive portfolio that serves our foundry customers' diverse needs. This role combines business development, technical program management, and strategic partnership management to ensure Intel Foundry has access to best-in-class IP solutions across all technology domains. Key Responsibilities IP Alliance Partnership Management * Manage and build strategic business relationships with IP alliance partners to create a robust ecosystem supporting foundry customers * Align and collaborate with IP alliance partners on IP roadmaps to ensure critical IP availability for mutual customers across all market segments * Monitor IP Alliance partners' ongoing activities and adherence to IP Alliance requirements for continuing membership in the IFS IP Alliance program * Present comprehensive IP Alliance overviews to prospective IP Alliance partners and drive partnership expansion Strategic IP Planning & Collaboration * Collaborate with Intel stakeholders on comprehensive quality reviews of IP, driving corrective actions and follow-up when required * Engage with and review IP vendors' qualifications for those applying to the IP Alliance program, ensuring alignment with Intel Foundry's quality and technology standards * Build and manage the IP alliance portal, aligning with industry best practices and providing seamless customer access to IP solutions * Drive IP roadmap alignment to support Intel Foundry's technology advancement and customer requirements Legal & Contract Management * Facilitate legal interactions with IP vendors and Intel stakeholders for agreement negotiations and contract management * Support contract reviews and negotiations to establish mutually beneficial partnership terms * Ensure compliance with legal requirements and intellectual property protection standards * Coordinate with Intel legal teams on IP licensing, partnership agreements, and risk management Cross-Functional Collaboration & Quality Assurance * Collaborate with engineering teams on IP integration, validation, and quality assurance processes * Work with business development teams to align IP alliance strategy with customer needs and market requirements * Support customer engagement activities related to IP selection, integration, and support * Drive continuous improvement in IP alliance processes and partner management Qualifications: The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through industry-relevant job experience, internship experience, and/or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications * Bachelor's degree in Computer/Electrical Engineering, or in a STEM related field of study with 7+ years of industry experience * 5 + Years of experience in technical program management of SoC IP Preferred Qualifications: * A post graduate degree in Computer/Electrical Engineering, or in a STEM related field of study and or MBA * Experience with foundry business models and customer engagement * Experience in technical program management with suppliers of SoC IP * Experience with semiconductor IP market dynamics and competitive landscape * Experience with IP portfolio management and technology roadmap planning * Experience in advanced process technologies and their IP requirements * Experience with international business development and partnership management * Experience in intellectual property law and licensing strategies What We Offer * Opportunity to build and lead Intel Foundry's strategic IP ecosystem from the ground up * Direct impact on Intel's foundry business success and customer satisfaction * Collaboration with world-class engineering teams and industry-leading IP partners * Competitive compensation and comprehensive benefits package * Professional development in strategic partnership management and foundry business * Leadership role in establishing Intel as a premier foundry service provider Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The ROLE As a Technical Program Manager, GPU Modeling under the umbrella of PMO, you will be accountable for GPU model software development. The role concentrates on unifying modeling efforts for architecture features across multiple product lines. The modeling view of a software-first paradigm means you, as the modeling technical PM, have a good understanding of the software stack for both Compute and Graphic workloads. THE PERSON: The ideal candidate has excellent organizational and people skills, demonstrates keen diligence for delivering accurate and quality results. The individual embraces accountability and shows mettle and tenacity in dealing with new challenges. Proven SDLC project leadership, strong prioritization, multitasking, and technical communication skills. KEY RESPONSIBILITIES: * Work closely with Graphics and SW teams, and IP design teams, and establish requirements for architecture modeling projects. * Track modeling efforts for common and unique architecture features across product lines and contribute to achieving shift-left silicon verification. * Collaborate with design infrastructure on collecting and refining test plan needs across product lines. * Develop plan of record for architecture modeling deliverables with detailed milestones, track progress, and assess and mitigate program risks. * Employ Agile Methodology for SW development and drives sprints and daily scrums. * Able to implement and track resource allocation across projects, identify resource gaps, and own resource balancing. * Coordinate with Perf Attainment team, define, and monitor performance attainment metrics across modeling efforts. PREFERRED EXPERIENCE * Software development background is required. * Solid understanding of Object-Oriented Programming. * Project management experience in the software domain * Solid understanding of the Silicon development life cycle ACADEMIC CREDENTIALS * Undergrad degree required. Bachelor's or higher degree in Computer Science or Computer Engineering is preferred. LOCATION: * Folsom, CA This role is not eligible for visa sponsorship. #LI-BM1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an adaptive, self-motivative Design Verification (DV) engineer to join our growing PLL team. As a key contributor, you will be part of a leading team that drives and improves AMD's ability to deliver the highest quality, industry-leading technologies to the market. The Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: * The successful candidate will possess: * Excellent analytical and critical thinking skills along with attention to details * Must be an initiative-taker, able to drive tasks independently and efficiently to completion * Strong/effective communication skills * Enthusiastic team-first mentality * Ability to provide mentorship and guidance to junior engineers * Relevant academic background (M.Sc. degree preferred) and at least 8 years of progressive experience KEY RESPONSIBILITIES: * Analyze complex verification and digital design problems and propose verification / micro-architecture solutions * Develop RTL and Firmware validation. * Drive/develop ASIC verification flows and scripts. * Create Verification architecture. * Work with the RTL Design team to ensure functional correctness and coverage. * Support silicon bring-up and diagnostics. * Support Post-silicon debug, root cause bug, provide solution or workaround. PREFERRED EXPERIENCE: * Proven experience in design verification from specification to successful silicon. * Experience in PLL, high-speed interfaces such as DDR, PCIe and high-speed SERDES. * Experience in designs with multiple power domains. * Experience in designs with multiple clock domains. * Experience in behavior modeling for Analog Circuits. * Experience in industry-standard ASIC CAD tools for verification, simulation, synthesis, STA, CDC, UPF, power estimation, etc. ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: * Folsom, CA This role is not eligible for visa sponsorship. #LI-SL3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

Join Us in Shaping the Future At Intel, we are building the next generation of software innovation through the one API software stack, a unified programming model designed to unlock the full potential of heterogeneous computing. Our team is at the forefront of enabling developers worldwide to harness CPUs, GPUs, and accelerators with cutting-edge tools, libraries, and compilers. By joining us, you'll contribute to an open ecosystem that drives performance, scalability, and portability across diverse architectures-empowering breakthroughs in AI, HPC, and beyond. If you're passionate about transforming how the world computes and want to work on technology that truly matters, this is your opportunity to make an impact. The Team The Intel Compiler Engineering Team is a high performing team responsible for the creation of the industry-leading Intel C/C++/DPC++ and Fortran Compilers, and is a leader in LLVM.org, the basis of our compiler products. We are continually pushing the boundaries of compiler technology in support of providing maximally useful and performant compilers for all of Intel's processor platforms, both CPU and GPUs. Position Overview We are seeking a dynamic leader to build and scale world-class compiler engineering teams driving Intel's next-generation compiler products and open-source contributions. In this role, you will lead geographically distributed teams of 15-25 highly skilled compiler engineers and architects, fostering collaboration across multiple time zones. Your strong technical background in compiler technology will enable you to guide and mentor experts, ensuring alignment with our product and technology goals. As the Sr. Compiler Engineering Manager, you will: * Lead and grow high-performing teams delivering cutting-edge compiler products and technology. * Define and drive the technical vision and strategic roadmap for Intel's compiler products and technology. * Champion innovation and a culture of technical excellence and continuous learning, as well as collaboration and contribution to the open-source community. * Collaborate cross-functionally with hardware, runtime, and application teams to deliver integrated solutions. * Own talent development, including hiring, performance management, and career growth for team members. * This is an opportunity to shape the future of heterogeneous computing and influence open standards like LLVM, SYCL, and OpenMP while working on technology that powers AI and HPC workloads globally. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences. Required Qualifications: * BS with 8+ OR MS with 6+ OR PhD with 4+ years of experience with a degree in Computer Science or related field. * 10+ years of hands-on software engineering, application performance tuning and software engineering management. * 5+ years experience of direct software engineering management experience with demonstrated ability of building and leading high performing teams. Preferred Qualifications: * Experience with compiler engineering. * Hardware knowledge: understanding of modern CPU, GPU, and accelerator architecture. * Demonstrated knowledge with accelerated computing and parallel programming models. * Experience leading team contributing to LLVM projects. * Strong communication skills. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, Massachusetts, Beaver Brook, US, Oregon, Hillsboro, US, Texas, Austin Business group: The Software Team drives customer value by enabling differentiated experiences through leadership AI technologies and foundational software stacks, products, and services. The group is responsible for developing the holistic strategy for client and data center software in collaboration with OSVs, ISVs, developers, partners and OEMs. The group delivers specialized NPU IP to enable the AI PC and GPU IP to support all of Intel's market segments. The group also has HW and SW engineering experts responsible for delivering IP, SOCs, runtimes, and platforms to support the CPU and GPU/accelerator roadmap, inclusive of integrated and discrete graphics. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $173,660.00-330,340.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below! * Life at Intel * Intel Global Diversity and Inclusion WHO WE ARE Platform Enabling is the leading edge of all new platform driver development across integrated and discrete graphics. Development is not limited to a specific area of functionality in the driver - a successful Platform Enabling engineer will need to be able to work across all areas of the graphics driver functionality (Display, Core/MM, SRIOV, GuC/PnP, Media, etc.) to adapt existing driver functionality to HW changes in upcoming platforms. Platform Enabling is the front line of Linux Graphics SW Power On execution for all platforms both client side and server side. Platform Enabling works across all phases of a program, responsible for initial pre-silicon (simulation and emulation) bring-up of the driver, to first silicon Power On execution, to post-silicon development and bug fixing on HW. A successful Platform Enabling engineer will need to be comfortable working on the internal driver to meet needs across pre-silicon and early HW enabling for Intel internal partners business units and external Intel partners, as well as being comfortable working directly with the upstream community and maintainers to upstream new platform patches and coordinate implementation of significant driver changes. This position is not eligible for Intel immigration sponsorship. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field with 6+ months relevant experience or Master's degree in the same fields. Relevant work experience should be of the following: * Experience with Linux kernel development and debugging * Experience with Open Source project/community interaction and contribution * Experience to ramp quickly in new areas of functionality * Experience with Systems programming experience in C * Experience with the fundamental concepts of Graphics, Display, Compute, and Media * GIT experience Preferred Qualifications: * Direct contribution to upstream Linux kernel * Experience in Linux HW driver development - directly interacting with/driving HW * Deep git experience, including branch manipulation, patch cherry-picking, rebasing, and resolving patch conflicts * Understanding of/experience with Display HW and signaling * Understanding of/experience with device memory management * Understanding of/experience with GPU command execution * Familiarity with/contributions to the Linux DRM subsystem and drivers * Understanding of all components in a typical Open Source Graphics/Compute/Media SW stack * Experience with a scripting language such as bash or python * Experience with Linux kernel power management flows * Experience working in simulation and emulation environments * Excellent communication and cross-org coordination skills, especially during high-stress/pressure environments such as initial silicon Power On Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, California, Folsom Business group: The Software Team drives customer value by enabling differentiated experiences through leadership AI technologies and foundational software stacks, products, and services. The group is responsible for developing the holistic strategy for client and data center software in collaboration with OSVs, ISVs, developers, partners and OEMs. The group delivers specialized NPU IP to enable the AI PC and GPU IP to support all of Intel's market segments. The group also has HW and SW engineering experts responsible for delivering IP, SOCs, runtimes, and platforms to support the CPU and GPU/accelerator roadmap, inclusive of integrated and discrete graphics. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $111,030.00-211,200.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. This role is within Intel's Client Computing Group. CCG is a computing paradigm where services and data reside in scalable data centers, and those services and data can be accessed by any connected device over the Internet. Responsible for designing and optimizing processors, chipsets and other hardware for consumer devices while also working on the software ecosystem, including drivers and utilities that enhance user experience. Intel is seeking a highly motivated and experienced Post-Silicon Validation Engineer to join our team and play a critical role in ensuring the quality and functionality of cutting-edge CPU products for laptops, desktops and gaming systems. You will work at the heart of innovation, contributing to the validation of complex CPU/SOC architectures and ensuring our products meet the highest standards of reliability and performance. Your responsibilities will include (but not limited) to: * Develop and execute validation plans to verify CPU/SOC functionality, Power and thermal management across multiple silicon platforms. * Design, implement, and debug validation tests and methodologies for post-silicon environments. * Collaborate with cross-functional teams, including design, firmware, software, and manufacturing, to identify and resolve issues. * Analyze and debug CPU/SOC and system-level issues using advanced tools and methodologies. * Lead debug task forces to root-cause and resolve issues impacting program milestones. * Mentor junior validation engineers to aid in their technical development. * Drive validation automation, coverage improvement, and process efficiency for validation execution. * Work with internal stakeholders to ensure smooth integration and delivery of products to the market. The Post-silicon Validation and Debug Engineer should possess the following attributes: * Strong written and verbal communication skills. * Willingness to prioritize multiple projects and work independently. * Willingness to work effectively in a collaborative, cross-functional environment. * Excellent problem-solving and debugging skills Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: * Bachelor's in electrical engineering, Computer Engineering, Computer Science or related field with 3+ years of combined experience in the following; OR Masters in electrical engineering, Computer Engineering, Computer Science or related field with 2+ years of combined experience in the following; * experience in post-silicon validation, pre-silicon verification or Design, particularly in CPU, SOC, or chipset domains * experience with technology such as SOC and CPU architecture, microarchitecture, and Power Management flows. * experience with silicon validation tools, lab equipment (e.g., logic analyzers, oscilloscopes), and debugging techniques. * experience in scripting and programming languages (e.g., Python, C/C++, or Perl) to develop validation tools and frameworks. Preferred Qualifications: * 2+ years of experience with Graphics, Media, Display IPs architecture, microarchitecture, and Power Management flows. * Candidates with advanced degrees and 5+ years' experience encouraged to apply. * Familiarity with power and performance testing methodologies is a plus. * Experience with Intel architecture, silicon bring-up, and validation flow. * Knowledge of firmware and software interaction with hardware. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, California, Folsom Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. AI /ML CPU System Validation Architect THE ROLE: The AI/ML CPU System Validation Architect will build sophisticated, scalable frameworks by employing advanced AI/ML technologies that will accelerate CPU system level silicon validation and debug. Exposure begins at the architecture level, working with pre-silicon teams to maximize pre-silicon coverage, post-silicon bring-up and enablement, and engagement through production and working with customer-facing teams for best adoption. You will work in a dynamic environment, directly with the product, tools, motherboards, and BIOS/OS. As a key contributor to the success of AMD's server & client roadmaps, you will be part of a high performing team driving the delivery of high quality, industry leading processors to market. The CPU platform validation team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: The AMD CPU platform validation team is looking for a dynamic, energetic AI/ML CPU Validation Architect to join our growing team focused on the silicon validation of AMD's family of Zen CPU's. KEY RESPONSIBILITIES: * Lead the charge at AMD evaluating, implementing, and deployment of AI/ML solutions in a post-silicon environment to accelerate CPU debug and bug hunting * Build and maintain ML pipelines using frameworks such as PyTorch, TensorFlow, or scikit-learn for anomaly detection, failure classification, and root cause analysis * Develop and refine NLP models using transformer models, tokenization libraries(NLTK, spa Cy, etc.) to meet CPU post-silicon validation use cases and requirements * Utilize machine learning techniques to analyze and interpret data * Implement and deploy Microservices/ML Pipelines on Linux/Windows Platforms * Solutions are delivered via a fully automated CI/CD Pipeline * Work closely with CPU post-silicon validation engineers to understand their requirements and develop AI/ML solutions that meet their needs, balancing technical feasibility with business objectives. PREFERRED EXPERIENCE: * 8+ yrs of experience in software product development with at least 4 yrs of relevant technical expertise in designing & developing AI/ML solutions, including experience with deep learning, NLP, and time-series analysis * Strong Python programming skills with experience in ML frameworks (PyTorch, TensorFlow, scikit-learn) and data processing libraries (pandas, NumPy) * Hands-on experience developing AI/ML models in real-world environments and integrating AI/ML using cloud-native or hybrid technologies into applications. * Experience with SQL and NoSQL databases, vector databases, and working with large-scale structured and unstructured datasets * Post-silicon validation and/or system level debug * Laboratory experience with post-si platforms * Developing validation testplans * x86 instruction set experience is a plus * Good written and oral communication skills * Strong analytical/problem solving skills, ability to learn quickly, and pronounced attention to detail. * Self-motivated, a good team player ACADEMIC CREDENTIALS: * BS/MS/PhD in Electrical or Computer Engineering with multiple years of relevant experience LOCATION: Folsom, CA Austin, TX #LI-LM1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

Intel's Discrete Graphics Engineering (DGE) organization develops cutting-edge discrete graphics products for gaming and AI. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role You will be responsible for designing and/or integrating IP for a discrete graphics SoC. You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation of discrete graphics SoC products, including: * Creating a design to produce key assets that help improve product KPIs for discrete graphics products * Working with SoC Architecture and platform architecture teams to establish silicon requirements * Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule * Creating micro architectural specification document for the design. * Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs. * Driving vendor's methodology to meet world class silicon design standards * Architecting area and power efficient low latency designs with scalabilities and flexibilities * Power and Area efficient RTL logic design and DV support * Running tools to ensure lint-free and CDC/RDC clean design, VCLP * Synthesis and timing constraints * Having achieved multiple tape-outs reaching production with first pass silicon * Ability to drive and improve digital design methodology to achieve high quality first silicon Hands on experience with FPGA emulation, silicon bring-up, characterization and debug * Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule * Strong verbal and written communication skills Good understanding of verilog and system verilog, synthesizable RTL * Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis * Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post silicon power correlation * Background in computer architecture * Bus fabric, including, but not limited to APB/AHB/AXI * Power management with multiple power domains, UPF, Power state tables. * Knowledge of lint tools, CDC and RDC tools, timing constraints, fishtail. * Knowledge of connectivity tools. * Understanding of key SoC design elements, arbiters, async FIFOs, DMAs, basic Controllers. * Comprehension of asynchronous clock crossing means and methodologies * Proven track record of bringing logic designs into high volume production * Ability to work well in a team and be productive under ambitious schedules * Should be self-motivated and well organized Qualifications: * BS+5 Years of relevant industry experience Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This job opening is for a Circuit Designer within a team responsible for definition, specification and implementation of high speed and high precision memory interface PHY circuits for DDR, LPDDR and GDDR. This team owns a wide variety of key IP in Digital and Analog/Mixed-Signal domains catering to AMD products across multiple business units. With a good mix of experienced designers and recent college graduates from top Engineering institutions across the country, this team offers a very competitive atmosphere with excellent scope to learn and improve. Meticulous execution routine resulting in a solid track record, a strong focus on innovation and a balanced work-life distribution makes this one of the top-class teams in this space across the industry. THE PERSON: Ideal candidate would be the one with not only strong circuit design knowledge, but also clear communication and presentation skills along with diligent documentation of work. Passion to go beyond the call of duty and innovate for higher efficiency would be a key differentiator. KEY RESPONSIBILITIES: * Complete ownership of analog mixed-signal blocks for memory interface PHY's in cutting edge FinFet technology nodes. * Responsible for circuit design, layout quality, electrical and timing analysis, and reliability checks. * Interface with cross-functional teams like RTL, Verification and Physical Design. PREFERRED EXPERIENCE: * Strong hands-on experience in analog/mixed signal circuits for memory interface PHY (DDR 5/6, LPDDR 5/6 and GDDR6/7) or serial links (SerDes, PCIE), such as, Transmitter, Receiver (with CTLE, VGA, DFE), DLL, PI and clock distribution. * Knowledge of LDO and Ultra-Fast Transient Regulators is a plus. * Python, Ocean scripting, Tcl scripting is a plus * Good technical knowledge of power-performance trade-offs in the designs. * Direct experience in all phases of design analysis including functional, timing and electrical sign-off ACADEMIC CREDENTIALS: * Masters in Electrical/Electronics Engineering, with specialization in microelectronics or something similar LOCATION: Folsom, CA (Open to Austin, TX; Fort Collins, CO ) #LI-SL3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

About the Role: We are seeking a Principal Engineer to lead system-level modeling and pre-silicon simulation for next-generation data center platforms. This role focuses on defining modeling strategies that enable accurate performance, power, and scalability analysis across compute, storage, networking, and interconnect components. The ideal candidate combines deep technical expertise in data center architectures with a passion for driving innovation in modeling frameworks and simulation methodologies. Key Responsibilities • Own system-level modeling strategy and execution for complex data center platforms, spanning compute, memory, and interconnect subsystems. • Develop predictive models for workload characterization, capacity planning, and performance/power trade-off analysis. • Drive pre-silicon simulation techniques to optimize system efficiency and guide architectural decisions. • Collaborate with architecture, hardware, and software teams to align modeling requirements with product roadmaps. • Innovate modeling frameworks, automation, and simulation flows to accelerate design cycles. • Lead technical reviews and mentor engineers, ensuring best practices in modeling methodologies and tool usage. • Influence next-generation platform architecture through data-driven insights from modeling and analysis. • Engage with hyperscalers, OEMs/ODMs, and industry partners to partner on workload analysis and future-looking datacenter direction. What You'll Gain • Opportunity to shape modeling strategies and roadmaps for next-generation platforms powering global data centers. • Hands-on experience influencing architectural decisions and accelerating design cycles. • Work at the forefront of system-level innovation in performance, power, and scalability. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. • 10+ years in system architecture, modeling, or performance analysis for data center or HPC environments. • Proven expertise in architectural modeling tools (e.g., Simics, SystemC, C++, Python-based frameworks). • Deep understanding of CPUs, GPUs, accelerators, memory hierarchy, and networking. • Strong background in simulation methodologies, workload analysis, and power/performance modeling. Preferred Qualifications • Familiarity with AI/ML workloads and large-scale data center environments. • Experience with advanced modeling frameworks and automation techniques. • Track record of technical leadership and cross-functional collaboration. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, California, Folsom, US, California, Santa Clara Business group: At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Job Details:Job Description: Silicon Engineering Group (SiG) plays a critical role in Intel's mission to create world-changing technology. Our engineers work on next-generation processor architectures that define the future of computing, from mobile devices to high-performance computing systems. We're pushing the boundaries of what's possible in silicon design while maintaining Intel's leadership in semiconductor innovation. We are actively seeking a talented CPU Core Logic Designer to join our dynamic team. This role offers the opportunity to work on cutting-edge processor designs that will shape the future of computing technology. This role's responsibilities include but are not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs. Participates actively in the definition of architecture and microarchitecture features of the CPU being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure high quality integration of the CPU block. Qualifications: You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Bachelor's degree in Electrical/Computer Engineering or Computer Science or related field and 6+ years of experience - OR - a Master's degree in Electrical/Computer Engineering or Computer Science or related field and 4+ years of experience. 4+ years combined experience in: System Verilog/Verilog/VHDL and/or VCS or similar Simulator Logic design and/or front end. Computer architecture and microarchitecture. Preferred Qualifications: 4+ years of experience with: Software/programming languages (i.e. C, C++, C#, Visual Basic/.NET. Perl, Python, Java, etc.). Modern energy-efficient/low-power logic design techniques, including those specifically applicable to high frequency optimization. Knowledge of Intel Architecture ISA and system architecture, including x86 assembly language. Experience with high speed circuit design and optimization for Datapath, circuits and/or arrays. Familiarity with circuit planning and timing convergence. Experience working with cross functional teams (Architecture, Spec development, Design, Formal, Verification). Job Type:Experienced HireShift:Shift 1 (United States of America) Primary Location: US, California, FolsomAdditional Locations:Business group:The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.