Design Engineer jobs at OmniVision Technologies

Responsibilities: Design and implement module level micro-architecture Participate in top-level implementation and integration Participate in both top level and module level RTL coding, simulation, synthesis and timing closure Generate test cases for the module level and chip level. Participate in FPGA emulation and post-silicon validation. Write design specification Requirements: BS in Electrical or Computer Engineering or related field or related experience, or MS in Electrical or Computer Engineering plus related experience 2+ years of ASIC design experience with knowledge of ASIC design flow, including hands-on experience in ASIC chip design and integration. Requires knowledge of Verilog, system Verilog, C or C++ languages, digital image processing and chip-level tape out procedure from initial PRD, design, verification, timing closure, FPGA emulation and ECO. Knowledge of display technology is a plus Knowledge of UVM is a plus Knowledge of DFT(Scan/MBIST/Functional Pattern) is a plus Annual base salary for this role in California, US is expected to be between $120,000 - $145,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.

Description Responsibilities : Image sensor control or processing function design and verification High speed interface (USB/MIPI) design and verification Full-chip integration and verification Chip bring-up, validation, and debugging Participate in the FPGA development Architecture, registers, interface and design documentation. Qualifications : PhD or MSEE with some experience of digital design Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis, and formality Knowledge of high performance and low power design techniques. Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture. Knowledge of assertion-based formal verification is a plus Image processing/DSP knowledge is a plus Annual base salary for this role in California, US is expected to be between $110,600 - $140,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role. EOE/Minorities/Females/Vet/Disability

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Graphics Memory Controller (GMC) is an IP that delivers into AMD's Discrete GPU (Navi) and Instinct (HBM) based SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for an experienced, conscientious logic design engineer in the Dram Controller IP at AMD's Santa Clara Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. THE PERSON: The ideal candidate for this role is an experienced and detail-oriented logic design engineer with a strong background in RTL development and a commitment to advancing graphics technologies. With over five years of experience in digital design, they bring expertise in high-speed memory interfaces such as HBM and GDDR and have a proven ability to deliver high-performance designs that meet timing, power, and area requirements. They are proficient in Verilog and familiar with industry-standard CAD tools from Synopsys, Cadence, and Mentor Graphics, with strong skills in simulation, synthesis, and timing analysis. This individual works effectively in dynamic, collaborative environments, communicates clearly across teams, and demonstrates strong analytical and problem-solving abilities. Their initiative and attention to detail make them a valuable contributor to AMD's Santa Clara Design Center, where they will support the development of next-generation discrete GPUs and data center solutions. KEY RESPONSIBILITIES: * Participate in the development of Architecture and Micro-architecture specifications for the Logic components. * Perform logic design, Register Transfer Level (RTL) coding for new features within existing blocks and design new blocks supporting HBM and GDDR DRAM Technologies * Deliver Designs that meet functional and performance requirements, * Deliver Design that meets physical/structural design constraints (timing, area, power) * Work with Verification Engineers to effectively communicate and resolve issues from test plan through feature bring up to coverage closure PREFERRED EXPERIENCE: * Logic design implementation using hardware description language (RTL) * Experience working on DRAM or similar high-speed interfaces is a big plus * Usage/execution of logic simulation, synthesis and familiarity with logic development flows * Strong RTL analysis skills including Verilog, Timing Analysis * Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics * Strong communication, Time Management, and Presentation Skills * Must be a self-starter, and be able to independently and efficiently drive tasks to completion * Excellent analytical and problem-solving skills along with attention to details * Aware of latest Power -aware design methodologies ACADEMIC CREDENTIALS: * Bachelor's or master's degree in computer engineering, Electrical Engineering, or a related field. #LI-DP1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a PCB Layout Physical Design Engineer - CAD in our Networking Technology & Solutions Group (NTSG), you will be responsible for ensuring that AMD's next-generation products deliver industry-leading reliability, performance, and efficiency. THE PERSON: In this role, you will closely collaborate with Silicon IP team, ASIC packaging team, PCB team, System Architect and external partners/suppliers to meet the most demanding SerDes requirements while ensuring the manufacturability. KEY RESPONSBILITIES: * PCB physical design for high-speed and high-power boards from initial concept to mass production * Optimize component placement, high-speed signal routing, critical power plane * Create design constraints based on the requirements of Hardware Design engineers, Signal/Power-Integrity engineers, Mechanical/Thermal engineers * Ensure that complex system layouts meet electrical and mechanical/thermal specifications * Adapt designs to fit component availability or manufacturing limitations * Resolve any issue related to PCB physical design and ensure a smooth transition from design to production * Generate comprehensive manufacturing and assembly packages such as Gerber, ODB * Building strong relationships with both engineers and manufacturers to reduce the risk of redesigning * Collaborate with cross-functional teams to drive product development while keeping projects on schedule and within scope. * Stay at the forefront of PCB physical design innovations and technologies to ensure AMD leadership in the industry PREFERRED QUALIFICATIONS: * Strong experience on PCB physical design for high-speed/high-power systems * Strong background in electronic fundamentals * Strong expertise in PCB design software such as Cadence Allegro * Deep knowledge on different types of layers such as copper, silkscreen, solder mask, and different types of component models such as symbol, footprint * Basic knowledge of mechanical, thermal, signal integrity, power integrity * Familiarity with PCB manufacturing processes and standards * Hands-on experience of balancing the technical requirements from hardware engineers and the practical constraints set by manufacturers * Excellent problem-solving and cross-functional collaboration skills ACADEMIC CREDENTIALS: Bachelor or Master degree of Electrical Engineering, Computer Engineering, or related field LOCATION: Santa Clara, CA #LI-BW1 #LI-NTSG-HW Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: * RTL design for memory I/O * PHY Digital Architecture development from pathfinding, coding, verification to physical implementation * PHY link layer design, implementation & verification with Analog and System architect. * PHY Analog/Digital co-design * Digital design and RTL coding * Timing Synthesis & Drive Physical implementation * Collaborate with architects, hardware engineers, and firmware engineers to understand the new features * Estimate the time required to write the new feature tests and any required changes to the test environment * Build the unit tests * Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues PREFERRED EXPERIENCE: * Digital design engineering experience * Experienced with Verilog, System Verilog, C, and C++ * Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus * Knowledge of clocking architectures, synchronization, and CDC methodology * Experience with synthesis, Timing closure * SERDES, DDR, Memory Controller, or MAC Design experience is preferred * Proficient in debugging firmware and RTL code using simulation tools * Strong understanding of computer organization/architecture. * Mixed signal RTL, Low power design experience is a plus * Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Santa Clara, CA or Boxborough, MA This role is not eligible for Visa sponsorship #LI-SC3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the Graphics and Engineering group, you will help bring to life cutting-edge designs related to Artificial Intelligent/ High Performance Computing SOCs . As a member of the Physical design and SOC teams, you will work closely with the architecture, IP design, RTL design, CAD, silicon technology teams and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: * Physical design and signoff methodology development for advanced nodes and High performance * Automation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environment for an SOC * Full chip / sub-system/ Tile level timing analysis with bleeding edge STA methodologies * Full chip / sub system level Clock tree synthesis and advanced clock tree construction and analysis. * Block and top level Formal verification, Physical Verification and chip finishing methodologies. * Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion, IRdrop and logic equivalence * Statistical and Static Timing Analysis, Variation aware analysis, stdcell Library characterization enhancements * Developing and Integrating ML and LLM applications for Physical Design and Analysis flows * Performing data analysis and identifying design trends * Customizing and implementing solutions for new challenges * Collaborating with multi-site engineering teams to reach project goals * Hands-on in reference flows, excellent debugging skills. * Maintain and update technology collaterals PREFERRED EXPERIENCE: * Experience in ASIC Physical Design and/or CAD development * Hands-on experience with Place and Route, Timing Analysis, and Physical Verification tools from Synopsys, Cadence, like ICC2, Fusion Compiler, DSO.AI, Innovus, Cerebrus, Primetime, Primeshield, PT-PX, Formality, Conformal, RedHawk, etc. * Experience in 5nm and below technologies * Script development, scripting (TCL, Perl, Python, Pandas), ML/AI techniques * Knowledge and Experience in ML and LLM * Experience with data analytics applications, database management ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering This role is not eligible for Visa Sponsorship. #LI-PA1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This role is an excellent opportunity to work on the cutting-edge next generation technologies that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets. You will join one of the fastest-growing field of Chiplet Interconnect technology rapidly being adopted across the VLSI industry. The team works on supporting both AMD proprietary I/O protocols and is also a key driver for industry standard Universal Chiplet Interconnect Express. The IP portfolio caters to short/ultra-short reach die-2-die interconnect with different bounding boxes tied to beachfront, Power, BER requirements. As a member of this team, you get a chance to work on IP development, drive design-specification, work on digital design and collaborate in the whole spectrum of areas include DFT, Firmware, Design verification, and Physical Design. THE PERSON: Enjoys being an environment where they can grow and learn with sense of team spirit Strong analytical thinking and problem-solving skills, excellent attention to detail. Eager to learn new designs and implementation techniques. Must have good collaboration and interpersonal skills. Excellent communication skills with leadership qualities KEY RESPONSIBILITIES: * Experience with I/O protocols like USB, PCIe, CXL. * Experience in developing micro-architecture for any given module. * RTL design experience with multi-clock, high frequency designs, low latency, low power & high performance. * Debugging/Post Silicon Bring up * Good Documentation and presentation skills. * Micro-architecture of simple to complex digital blocks. * RTL development using best industry practices. * Optimize design for key metrics like Area, Power, Performance etc. * Ability to work with cross-functional teams like DFT, Implementation, Verification, Emulation, Firmware regularly. PREFERRED EXPERIENCE: * Experience in digital front-end implementation, including micro-arch. definition * Experience with scripting/automation languages like Python/Perl * Firmware on Hardware-Firmware co-design * Experience with state-of-the-art industry standard digital tools * Preferred experience in design with multiple clock domains * RTL design experience with multi-clock, high frequency designs * Knowledge in digital RTL Digital Design and Implementation * Experience with Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA) ACADEMIC CREDENTIALS: Master's/Bachelor's in electrical engineering or equivalent preferred LOCATION: San Jose, CA #LI-SL3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Join our leading-edge Design and RTL Methodology team as a Hardware Development Engineer, contributing directly to the development of our latest FPGA products. In this role, you will help ensure the highest quality of RTL design that our customers rely on. THE PERSON: You are an experienced, proactive RTL Design Engineer who thrives in a fast-paced environment. You quickly ramp up on new tools and methodologies, and you're comfortable working on a small, highly capable team where you can take on significant responsibility. KEY RESPONSIBILITITES: * Collaborate with the design team to drive continuous improvements in front-end design methodologies, ensuring top-quality RTL across areas such as Lint, CDC, formal equivalence, and low-power verification. * Enhance and develop flows that analyze RTL and Unified Power Format (UPF) Files, including updating or creating new UPF to enable robust verification of power-domain crossings for AMD's next-generation monolithic and stacked FPGA-SoC product families. * Leverage corporate AI systems to increase productivity and streamline workflows. PREFERRED EXPERIENCE: * Proven experience in logic design and static verification (SystemVerilog, Verilog, or VHDL), ideally with contributions to at least two ASIC products brought to market. * Strong background in RTL/logic design, including specifying multi-power-domain architectures using IEEE 1801 Unified Power Format (UPF). * Programming skills in Perl, Python, and TCL. ACADEMIC CREDENTIALS: * Bachelor's degree in Electrical or Computer Engineering; Master's degree preferred. LOCATION: San Jose or other HYBRID office locations. #LI-GW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a design engineer in our CAD and methodology team, you will be responsible for leading and optimizing the EDA environment for Project CAD team in the Adaptive & Embedded Computing Group (AECG). You will oversee the complete SCH-to-GDS flow, manage tool deployments, and drive methodology development across multiple semiconductor projects. This is an opportunity to shape the technical direction of critical IC design workflows and lead a team of skilled CAD engineers. You will advise on tools selection, and interface with various EDA tool vendors and foundries to run the EDA tools, PDKs and other files necessary for the Silicon Development Team to operate efficiently. You will be responsible for defining and creating a unified environment that sets the versions of the tools, PDK and design for every individual chip in development. Additionally, you will interact with the various Silicon development teams who will be requesting newer versions of the tools and raise trouble tickets with CAD vendors as needed. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: * Execute in CAD infrastructure team supporting multiple IC design projects * Establish and maintain standardized design flows and methodologies * Implement and support customized CAD flows for Fabric design groups * Enable the team to meet design and development targets by working closely with external tool vendors * Develop tools flows methodologies on digital back-end domains, sign-off flows for timing, power, EM/IR, DRC/LVS/DFM, etc. * Improve engineering efficiency while improving design quality in IP release process * Be single point contact for bugs and issues for custom and analog physical design team * Build flow in TCL, Python to ensure quality and faster executions * Understand different methodologies used across industry to adopt best practices * Leverage and deploy AMD AI systems to design teams PREFERRED EXPERIENCE: * Proficiency in TCL, Python, PERL, or other scripting languages * Experience with PDKs and technology enablement * Skilled in Spice and PVT simulation environments * Hands-on expertise with Virtuoso-based custom layout tools and flows * Familiarity with Calibre extraction flows and EM/IR analysis using Totem and Redhawk * Working knowledge of SiliconSmart, PrimeTime, and Physical aspect of VLSI designs * Strong written and verbal communication skills ACADEMIC CREDENTIALS: * Bachelor's degree in Computer or Electrical Engineering, or equivalent; Master's degree preferred LOCATION: * San Jose #LI-GW1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the Adaptive and Embedded Computing Group, you will help bring to life cutting-edge designs. As a member of the front-end design team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: You have a passion for modern, complex processor architecture, RTL coding, and digital design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: * Own the design and implementation of blocks to meet functional, timing, area and power requirements * Guide and review verification for these blocks * Design and implement logic functions that enable efficient test and debug * Implement automation to increase design team efficiency PREFERRED EXPERIENCE: * Strong front-end RTL engineering background * Strong communication skills, able to summarize complex problems for executives as well as drill down to details with architects and engineers * Strong analytic and problem solving skills including the ability to analyze current behavior, identify potential areas for improvement, and design of experiments * Experience with Arm architecture and APB, AXI, CHI protocols * Experience with design reuse, including RTL, constraints, and waivers * Experience with SoC level design integration * Experience with automation using scripting techniques such as PERL, Python, or Tcl * Experience with timing constraints and timing exceptions * Experience running standard quality checks such as LINT and CDC * Experience designing with multiple power domains including writing UPF * Must be a self-starter and self-motivated ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ TITLE: Design Engineer At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. THE ROLE: This position is within the AMD SERDES Technology team in San Jose, CA, looking for a talented and motivated team member with a focus on FPGA design and hands on silicon bring-up. You will use your knowledge of high-speed SerDes and design experience to develop various solutions for common high-speed SerDes interfaces and applications. RESPONSIBILITIES: FPGA design and IP solutions development Develop embedded firmware for validation and applications development Work with internal teams to create IP solution, debug features associated with physical layer functionalities Provide customer support and field debugging as required Preferred Skills & Experience: FPGA design and debug experience C/C++ for embedded system development Knowledge of physical layer specifications in IEEE 802.3 and / or PCIe Programming experience in Python or Perl scripting languages Hands-on experience with various lab equipment for silicon bring-up and validation Knowledge of 50G+ multi-level (i.e. PAM4) SERDES is preferred Excellent verbal and written communication skills ACADEMIC CREDENTIALS: B.S. or M.S. Electrical or Computer Engineering preferred Requisition Number: 179684 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ Job Requirements: Experience in Digital Design or Silicon characterization Should be knowledgeable about all the internal blocks of FPGA like DSP, BRAM, I/O etc Good understanding of device technology, custom circuit and digital designs and electrical analysis Strong scripting skills using Perl, Python, C-shell or similar scripting languages. Experience with Xilinx FPGA design / implementation tools is a plus Good analytical, communication, presentation and troubleshooting skills are required Education Requirements Minimum of a BS with 2+ year of experience or MS degree in Electrical Engineering, Computer Engineering or related equivalent #LI-JY1 Requisition Number: 167464 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ SILICON DESIGN ENGINEER 2 THE ROLE: Join a team of silicon design engineers who utilize their skills in logical and physical circuit optimization to innovate and implement programmable logic interfaces. Our team owns the design and implementation from RTL to final layout database delivery, as well as supports silicon validation and characterization. You'll be part of a small and focused design team with a wide scope of responsibilities and technical opportunities using the latest in circuit design tools and methodologies. Your skills will be deployed in simulation, characterization, and model development for circuit performance and power at cell, critical path, and block-level designs. THE PERSON: We are looking for a self-motivated team worker, who possesses good verbal and written communication skills. The ideal candidate strives to tackle challenges in creative ways with solutions that can be applied in a wide range of applications. If you have a drive for high-quality, high-accountability design work, then you will be a great fit for our team! KEY RESPONSIBILITIES: Schematic capture Logical equivalency checks Test bench development Place and route constraint definition Physical design closure in APR tools Critical-path simulations for timing correlation with STA Electrical rule checks commensurate with each stage of the design Generating and characterizing models of circuit timing and power PREFERRED EXPERIENCE: Knowledge in VLSI design, design automation, IC design, and RTL design Knowledge of floor planning, synthesis, place & route, static timing analysis, and EM/IR analysis Knowledge of Cadence SPICE, Synopsys Primetime, and IC compiler preferred ACADEMIC CREDENTIALS: MS (preferred) or BS with additional experience in Electrical Engineering or Computer Engineering or related equivalent #LI-JY1 Requisition Number: 162224 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ The System Validation team plays a key role in validation of complex SOCs in pre-silicon and post silicon. Our most recent project Versal ACAP, a fully software-programmable, heterogeneous compute platform that combines Scalar Engines, Adaptable Engines, and Intelligent Engines to achieve dramatic performance improvements with dual core ARM processing system and Programmable logic is known for Industry's first Heterogeneous architecture. We are looking for a passionate engineer to work with us on our latest SOC - Versal. We are looking for an aspiring Systems Design Engineer with a strong background in software to join the System-level Test team in San Jose. As a System Validation Engineering Intern, you will be involved in the silicon life cycle from testing of emulated next-generation RTL through to silicon verification and characterization. You will have a view of the full system but also will become an expert in certain IP down to the register-level. We are looking for someone who can span the range of able to develop device drivers in software to debug on hardware. As an intern on our team, you will gain real engineering experience in working with complex SOC and validation software and make a difference to the quality of our products. Responsibilities Assist in bringing up system level validation tool on new silicon Run regressions and experiments to help root cause issues Enhance existing test software for system-level validation and verification of existing and new FPGA features. Design, develop, implement, test, and verify systems based on FPGAs with embedded Micro Blaze or ARM processors Help to develop novel methods for system-level modeling and verification Help automate design, test, and build processes Qualificiations Must be a student enrolled in a bachelor's or master's degree program in Electrical / Computer Engineering with an emphasis on embedded system development and/or computer architecture Computer Architecture class(es) required Programming languages: C, Python, Verilog To support our group, we are looking for a intern that can commit to a full time (40 hr per week), 4-12-month internship starting in January 2023. You must be able to work onsite at are San Jose, CA Office. Located at 2100 Logic Dr, San Jose, CA 95124 Shorter internships will NOT be considered. Requisition Number: 185604 Country: United States State: California City: San Jose Job Function: Student/ Intern/ Temp Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The candidate will join a highly visible team of physical interface experts concentrated on SERDES interfaces across AMD products. The team works across a large swath of AMD teams and is instrumental in the delivery of leading-edge, high-speed interface capabilities. THE PERSON: The ideal candidate is self-motivated to work independently as well as collaboratively with engineers across a variety of AMD design, verification, and validation teams. KEY RESPONSIBILITIES: * Excellent working knowledge of RTL-based design flows * Strong knowledge of firmware and hardware interaction * FPGA design and prototyping for various MAC or PCS functionalities * Working knowledge of the entire FPGA or ASIC design process and tool flow * Work with internal and external teams to develop transceivers solutions for various applications * Hands-on experience with various lab equipment for silicon bring-up and validation PREFERRED EXPERIENCE: * Familiar with industry standards such as Ethernet and PCIe is a plus * Strong analytical and problem-solving skills with pronounced attention to details ACADEMIC CREDENTIALS: * BS or MS in Electrical or Computer Engineering preferred LOCATION: San Jose, CA #LI-DP1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Description The Product Characterization Engineer works in an aggressive, fast-paced R&D environment to scientifically characterize performance of new pixel technology, using strong analytical skills to objectively analyze design trade-offs and debug problems in pixel design/process and taking ownership of multiple projects. Responsibilities: Supports CMOS Imaging technology development through detailed scientific characterization Responsible for complete electrical and optical characterization of various CMOS Image sensors Debugs and solves problems on new and existing pixel designs Guides pixel layout/process design for next generation CMOS Sensors by characterizing performance of various experimental layouts and process conditions Works with Process Integration/Layout design and Process Simulation team to characterize new designs/process and suggest new process experiments based on characterization data Acts as primary feedback source to various inter-disciplinary teams for silicon data on various pixel designs and process designs Works with test engineering team to develop automated wafer-level characterization programs Develops special test routines in C++/Matlab Works with Production, QA teams to solve yield issues related to pixel performance Requirements: 2+ yrs experience in characterization and designing integrated circuit systems (Imagers, DRAM, processors, etc.) Knowledge of Analog/Mixed Signal/Digital CMOS circuits, CMOS fabrication process and CMOS device physics Experience with CMS Image sensor characterization and design is a big plus Knowledge of C++/Perl/Python/MATLAB, Layout/Simulation tools and color technology is a plus MS in Electrical Engineering, Physics related field or equivalent work experience; PhD is a plus. Annual base salary for this role in California, US is expected to be between $110,600 - $130,200. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.EOE/Minorities/Females/Vet/Disability

Description Primary responsibility is to bring a new product from tapeout to mass production. Candidate designs a characterization/testing plan and works with R&D teams and manufacturing engineers on technical issues, resolving these issues to meet performance requirements on product requirement documents. For existing products, the senior product engineer will maintain and sustain technical support and actively participate in yield improvements. Description: Owner of assigned products Participate in product definition and provide DFM inputs. Lead product introduction and ramp-up for image sensors and ASIC devices. Analyze yield and drive corrective actions for yield improvements. Drive characterization to finalize the product datasheet. Co-work with testing engineers to develop, verify and release testing program at CP or FT. Preferred: 1-6 yrs of Product Engineering experience in image sensor or memory (flash, SRAM, DRAM) or ASIC products. Familiarity with silicon process will be plus. Good communication and organizational skills Strong analytical and problem solving skills. Master's Degree in EE or Physics, or a related field. Mandarin speaking proficiency (both spoken and written), strongly preferred due to daily interactions with our China-based team . This skill is crucial for effective communication, understanding project requirements, and fostering strong relationships within our international team. Annual base salary for this role in California, US is expected to be between $90,600 - $130,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role. EOE/Minorities/Females/Vet/Disability

Description Primary responsibility is to bring a new product from tapeout to mass production. Candidate designs a characterization/testing plan and works with R&D teams and manufacturing engineers on technical issues, resolving these issues to meet performance requirements on product requirement documents. For existing products, the senior product engineer will maintain and sustain technical support and actively participate in yield improvements. Description: Owner of assigned products Participate in product definition and provide DFM inputs. Lead product introduction and ramp-up for image sensors and ASIC devices. Analyze yield and drive corrective actions for yield improvements. Drive characterization to finalize the product datasheet. Co-work with testing engineers to develop, verify and release testing program at CP or FT. Preferred: 1-6 yrs of Product Engineering experience in image sensor or memory (flash, SRAM, DRAM) or ASIC products. Familiarity with silicon process will be plus. Good communication and organizational skills Strong analytical and problem solving skills. Master's Degree in EE or Physics, or a related field. Mandarin speaking proficiency (both spoken and written), strongly preferred due to daily interactions with our China-based team . This skill is crucial for effective communication, understanding project requirements, and fostering strong relationships within our international team. Annual base salary for this role in California, US is expected to be between $90,600 - $130,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role. EOE/Minorities/Females/Vet/Disability

We are looking for Digital Design Engineer for design and development of next generation image sensors and related technologies. The candidate should have strong fundamentals in digital circuit design and ability to independently design blocks with given specifications. The candidate should have the capability to lead, design and develop circuits, as well as experience in debugging/verifying design issues. As Digital Circuit Design Engineer, you will: Primarily responsible for sensor timing control design and Image Signal Processing (ISP) system level integration. Actively participate in chip level architecture definition, including analog interface/control, image data processing, power, performance, and area trade-offs. Integrate and validate ISP data pipes according to PRD/design specification & system architecture of SoC CIS products Work with CIS project lead, sensor digital & analog engineers for system integration & validation Work with back-end team closely in floor planning, timing closure, and DFT. Full-chip integration and verification. Chip bring-up, validation, and debugging Work with algorithm and application engineers for image tuning and qualification Silicon validation, debugging & tuning Qualifications: In depth hands-on experience in ASIC design flow: RTL coding, simulation, synthesis, static timing analysis, formality verification, DFT. Extensive knowledge of all aspects of chip development: from design specification, architecture definition, low-power design, tape-out, chip validation, chip debugging, mass production, to customer support. Be familiar with image sensor performance metrics, image signal processing (ISP), image sensor usage and integration into camera systems. Experience/knowledge in image sensor and camera system is a plus Minimum of 4 plus years of relevant experience. MSEE or equivalent Annual base salary for this role in California, US is expected to be between $120,600 - $150,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role. EOE/Minorities/Females/Vet/Disability