Product engineer jobs in Sunnyvale, CA - 12,856 jobs

A leading semiconductor company in San Jose is seeking a Staff Power Module Design Engineer. You'll develop innovative power module products and collaborate with industry experts. The role requires a strong educational background in Power Electronics and significant experience in switching power converter design. This position offers competitive pay within a vibrant engineering team, fostering professional growth and mentorship opportunities. #J-18808-Ljbffr

Physical Design Engineer - New College Grad 2026 page is loaded## Physical Design Engineer - New College Grad 2026locations: US, CA, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR2009983We are now looking for a Physical Design Engineer!NVIDIA has continuously pioneered and reinvented itself over two decades through various avenues of computing: Graphics, High Performance Computing, Artificial Intelligence, Research, and more. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can solve, and that matter to the world. This is our life's work, to amplify human creativity, intelligence, and technology. Today, visual computing is becoming increasingly central to how people interact with technology, and there has never been a more exciting time to join our team. We are looking for a Physical Design Engineer who will be responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets, and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets.**What you will be doing:*** As a member of the team, you will participate in the efforts in establishing CAD and physical design methodologies (flow and tools development) as well as implementation.* Your day to day will include developing chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects.* This position requires you to work with EDA vendor (Synopsys, Cadence, Mentor, etc.) tool suites such as: ICC2,PrimeTime, dc\_shell, Innovus, SeaHawk.* You will interact with a diverse team engineers.**What we need to see:*** Completing an BSEE, MSEE or PhD (or equivalent experience).* Deep understanding of VLSI and Physical Design related basics & concepts.* Possess a deep understanding of static timing analysis, clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis.* Experience in scripting and programming using several of the following languages/tools: Perl, C, C++, TCL, Scheme, Skill, or Make.* Previous internship or project experience in physical design implementation With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a passion for technology, we want to hear from you!Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 96,000 USD - 161,000 USD for Level 1, and 108,000 USD - 184,000 USD for Level 2.You will also be eligible for equity and .Applications for this job will be accepted at least until December 19, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr

A leading semiconductor company in Santa Clara is looking for an FPGA Hardware Validation Engineer to create and implement validation platforms while collaborating with design and firmware teams. Candidates should have extensive experience in FPGA prototyping and strong problem-solving skills, along with a BS in Electrical or Computer Engineering. The role involves complex architecture designs and debugging hardware/firmware issues. Join a culture of innovation driven by collaboration and inclusivity. #J-18808-Ljbffr

Vision Affordable, natural, factory-built homes. We've embarked on a homebuilding renaissance where affordability,sustainability, and beauty come together. Out beyond ideas of right angles and hard lines, there's a bioceramic dome. The Geodesic Dome, introduced by the Visionary Architect Buckminster Fuller, is the world's most efficient structure. But to manufacture domes, we needed a material science breakthrough. Enter bioceramics a new class of earth-friendly materials that mimic human bone. Bioceramic domes maximize efficiency at the most fundamental levels - geometry, materials, and manufacturing method. In the future, we won't live in boxes. Join us there! Project After successfully achieving factory-built housing certification from the State of California and breaking ground on our flagship Amma dome build, we are hiring key team members to help us complete the design of the Amma product. We have a strong preference for team members to locate full-time onsite in Grass Valley, California, although hybrid/remote arrangements are possible for standout candidates. Role Geoship is seeking a Product Design Engineer to advance and finalize the design of our first Amma dome system. This role is for a first-principles problem solver and a multidisciplinary engineer who thrives in ambiguity and rapid iteration. You will integrate structural, mechanical, materials, and relevant building and safety standards into elegant, manufacturable solutions that bring a new form of sustainable housing into reality. You will work closely with studio designers, materials scientists, manufacturing engineers, and operations teams to develop bioceramic molded parts, connection systems, structural components, interior systems, and other assemblies that seamlessly integrate into the finished dome. Your work will span concept development, detailed design, prototyping, design-for-manufacturing, analysis, testing, documentation, supplier engagement, and hands-on support during prototype builds. This is a rare opportunity to build a new housing technology from the ground up. If you think beyond conventional solutions, care deeply about regenerative design, and want to help shape the future of homes, we'd love to meet you! Description ● Product & Component Design: Own the design of bioceramic components, connection systems, and mechanical assemblies from initial concept through release-applying first-principles reasoning, strong engineering fundamentals, and comprehensive system-level design that includes performing energy and load calculations, flow and pressure analysis, and MEP equipment selection; developing schematics, layouts, and installation instructions for HVAC ducting, piping, and related infrastructure; and ensuring compliance with all relevant building codes and industry standards. ● Design for Manufacturing: Ensure designs are compatible with casting, mixing, material-handling, and assembly processes; create clear specifications, tolerances, and performance requirements to enable high-quality, repeatable, scalable production ● Prototyping & Testing: Build and test prototypes, develop test rigs when needed, and conduct design analyses, validate mechanical behavior and assembly methods, and iterate rapidly based on real-world results ● Compliance & Standards Integration: Ensure mechanical designs align with relevant structural, safety, and building standards, translating regulatory and performance requirements into clear engineering specifications. ● Cross-Functional Collaboration: Partner with studio design, engineering, materials, and operations teams to develop system architectures, resolve tradeoffs, and support prototype and pilot builds ● Documentation & Communication: Produce clear CAD models, drawings, BOMs, specifications, DFMEAs, test summaries, and design justifications; present design options and tradeoffs to facilitate alignment and decision-making Qualifications ● Bachelor's degree in Mechanical Engineering, or related field ● 3 ~ 7+ years of professional experience in mechanical/product design, preferably involving large complex assemblies ● Strong analytical and problem-solving skills, with a proven ability to identify and implement effective solutions using first principles, modeling, and hands-on experimentations ● Strong CAD proficiency (SolidWorks, Fusion, Onshape, or similar) ● Demonstrated ability to take hardware products from concept through prototyping and into production ● Experience with tolerance stacks, design-for-manufacturing, and geometric dimensioning & tolerancing (GD&T) ● Ability to thrive in a fast-paced startup environment-proactive, self-directed, resourceful ● Strong communication skills and ability to collaborate effectively across disciplines Desired Experience ● Takes ownership and responsibility for current and past results ● Takes risks, learns from mistakes, and drives to improve the performance of oneself, others, and the company ● Experience working with cast or molded materials, especially ceramics and composites ● Familiarity with structural analysis techniques and tools (FEA and hand calcs) ● Experience designing components for modular building systems, architectural hardware, or complex mechanical assemblies ● Hands-on prototyping experience: machining, molding, 3D printing, fabrication, or test rig development Benefits ● Base pay between $125,000 and $170,000, based on experience and qualifications ● Comprehensive healthcare coverage ● Stock options ● Health savings account ● 401k ● Opportunity to join a conscious, future-building team

About Commonwealth Fusion Systems: Commonwealth Fusion Systems is on a mission to deliver the urgent transition to fusion energy. Combining decades of research, top talent, and new technologies, we're designing and building commercially viable fusion power plants. And working with policymakers and suppliers to build the energy industry of the future. We're in the best position to make it happen. Since 2018, we've raised nearly $3 billion in capital, making us the largest and leading private fusion company in the world. Now we're looking for more thinkers, doers, builders, and makers to join us. People who'll bring new perspectives, solve tough problems, and thrive as part of a team. If that's you and this role fits, we want to hear from you. Principal Mechanical Engineer We're looking for a Principal Mechanical Engineer to join our R&D and equipment design team to help build the next generation of thin‑film deposition technology. The Principal Mechanical Engineer will be responsible for the design and implementation of advanced R&D equipment and complex machinery. This role requires strong technical expertise, procedural discipline, and the ability to collaborate across engineering and technology functions to ensure safe, reliable, and high‑performance equipment. If you enjoy working on complex design problems, mentoring others, and solving problems in a collaborative, fast‑paced environment, this is your opportunity to make an impact. What you'll do: Lead the design and implementation of advanced R&D equipment for thin‑film processing, including ownership of key mechanical modules and sub‑systems Define system level requirements and drive innovative design concepts to meet these requirements Lead design reviews for overall mechanical system and key mechanical subsystems Generate and maintain interfaces with other engineering subsystems Report on and be accountable for project progress to stakeholders Work effectively within a multi‑disciplinary team of top scientists and engineers Mentor engineering staff for effectiveness and delivery of on‑time & in‑spec outcomes Get things done: drive projects, consistently deliver, act with speed What we're looking for: Master's degree in Mechanical Engineering or related field (or equivalent industrial experience) 15+ years of experience with at least 7 years of experience working as a principal mechanical design engineer or engineering team lead in a relevant context: design and implementation of R&D systems and manufacturing equipment Ability to conceive of novel solutions for complex engineering systems in challenging environments Expertise with 3D modeling; preferred experience with SolidWorks and NX Experience with COMSOL, ANSYS or other FEA tools Ability to select and qualify vendors for components or subsystems Demonstrated ability to lead in either direct or matrix structures Strong verbal and written communication skills and a dedication to high‑quality documentation Bonus points for: Ph.D. in Mechanical Engineering or related field (or equivalent industrial experience) Prior success building first‑of‑kind or experimental tools for material science or semiconductor R&D Familiarity in applying Semi‑S8, ASME, ACI, ASTM, and other mechanical standards to design solutions Experience with the operation of equipment in a manufacturing environment Must‑have Requirements: Ability to occasionally lift up to 50 lbs Perform activities such as stooping, climbing, standing, or sitting for extended periods of time Dedication to safety to mitigate industrial hazards that may include heat, cold, noise, fumes, strong magnets, lead (Pb), high voltage, and cryogenics Willingness to travel or work required nights/weekends/on‑call occasionally $150,000 - $225,000 a year Benefits Competitive compensation with equity 12.5 Company‑wide Holidays Flexible vacation days 10 sick days Generous parental leave policy Health, dental, and vision insurance 401(k) with employer matching Professional growth opportunities Team‑building activities #LI‑Onsite At CFS, we excel in fast‑paced environments, driven by our values of integrity, execution, impact, and self‑critique. As we grow, we're eager to bring on mission‑driven folks who offer diverse perspectives and fresh ways to tackle challenges. We value diversity deeply and are proud to be an equal opportunity employer by choice. We consider all qualified applicants equally, regardless of race, color, national origin, ancestry, citizenship status, protected veteran status, religion, physical or mental disability, marital status, sex, sexual orientation, gender identity or expression, age, or any other basis protected by law. This role requires compliance with U.S. laws concerning the export of controlled or protected technologies or information (collectively, “Export Control Laws #J-18808-Ljbffr

A leading IoT solutions company in San Jose is seeking a Sr. Staff PHY Design Engineer to join their innovative team focusing on wireless semiconductor RF technology. In this role, you will be responsible for defining, developing, and refining hierarchical UVM testbench for verification of wireless PHY and MAC layers. The position offers a competitive salary range of $216,091 - $220,000 per year and a collaborative work environment that encourages growth and diversity. #J-18808-Ljbffr

Physical Design Engineer Job at Apple, Cupertino, CAJob Description Physical Design Engineer Department: Hardware Imagine what you can do here. Apple is a place where extraordinary people gather to do their best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Description Apple Inc. has the following available in Cupertino, California, and various unanticipated locations throughout the USA. Responsible for physical design and implementation of partitions. Build partition architecture and drive physical aspects early in the design cycle. Physically implement design partitions (from netlist to tape-out) for a highly complex System-on-Chip (SoC) utilizing state-of-the-art process technology. Work on partition-level place and route (P&R) implementation, including floor planning, clock and power distribution, timing closure, physical and electrical verification. Complete netlist to GDSII implementation for partitions meeting schedule and design goals. Oversee timing, physical, and electrical verification, and drive the signoff closure for the partitions. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. The base pay range for this role is between $151,091 - $214,500/year, depending on skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees have the opportunity to participate in Apple's stock programs, receive benefits including medical and dental coverage, retirement benefits, discounts, free services, educational reimbursement, and potential bonuses or relocation assistance. Learn more about Apple Benefits. Minimum Qualifications Master's degree or foreign equivalent in Electrical Engineering or related field. 2 years of relevant experience. 1 year of experience with each of the following: Encounter Design System tool, QRC, Calibre, Voltus, Primetime. Preferred Qualifications N/A Apple is an equal opportunity employer committed to inclusion and diversity. We promote equal opportunity for all applicants regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics. Note: Apple benefits, compensation, and employee stock programs are subject to eligibility and other terms. This job posting appears to be active and does not indicate it is expired. #J-18808-Ljbffr

Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams Chip/Block Level Floorplanning and pin assignment Review top-level/block-level clock specifications for completeness and feasibility Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing) Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification) Presentations and Customer Interaction in customer meetings Necessary Qualifications: BSEE, with 9+ years of experience or equivalent experience. MSEE preferred. Experience in ASIC Physical Design; Experience in an SoC product development organization with tapeouts at 28nm/16nm design nodes. Hands-on Experience with implementation EDA tools like ICC2/Innovus. Scripting (Perl/Tcl/Python) is required. Good understanding of ASIC frontend design. Experience in both Flat and Hierarchical layouts. Strong problem‑solving skills and ability to analyze and resolve physical design issues related to library, timing constraints or CAD tools is required. Experience with power analysis and IR‑drop tools (primepower/Redhawk) and Static Timing Analysis (Primetime). Experience with Physical Verification and fix PV errors in layout. Expert handling of Verilog HDL based Netlists, Physical design libraries. Team player with good interpersonal and communication skills; ability to explain processes and answer customer questions during meetings. Compensation: $190,000.00 - $200,000.00 per year MAKING THE INDUSTRY'S BEST MATCHES DBSI Services is widely recognized as one of the industry's fastest growing staffing agencies. Thanks to our longstanding experience in various industries, we have the capacity to build meaningful, long‑lasting relationships with all our clients. Our success is a result of our commitment to the best people, the best solutions and the best results. Our Story: Founded in 1995 Privately Owned Corporation Managing Partner Business Model Headquartered in New Jersey US Based Engineers Only Methodology and Process Driven Top performing engineers are the foundation of our business. Our priority is building strong relationships with each employment candidate we work with. You can trust our professional recruiters to invest the time required to fully understand your skills, explore your professional goals and help you find the right career opportunities. #J-18808-Ljbffr

A leading tech company in California is seeking a Technical Marketing Lead who will own marketing systems and build automation tools. You'll create AI-native workflows and work with tools like Claude Code and Cursor. Ideal candidates will have 4-8 years of B2B marketing experience and a track record of building and deploying effective systems. This is a chance to take ownership from day one and prove yourself in a rapidly evolving environment. #J-18808-Ljbffr

Altera .# **Job Details:**### ## **Job Description:****About the Role:**As a Physical Design Engineer at Altera, you will play a critical role in the backend implementation flow - from RTL/netlist through GDSII/tape-out for FPGA/SoC devices. You will collaborate with architecture, logic design, DFT, CAD/EDA, and manufacturing teams to achieve performance, power, and area (PPA) goals, with a particular emphasis on programmable logic structures, block and full-chip integration, and the unique demands of FPGA technologies (e.g., configurable logic blocks, routing fabrics, I/O rings, on-chip power domains).**Key Responsibilities:*** Execute physical design implementation tasks (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist to GDSII.* Apply PPA optimization techniques (performance/timing closure, power reduction, area efficiency) across block-level and full-chip hierarchies.* Collaborate with front-end design, architecture, and CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets, and DFT insertions are met.* Develop and enhance physical design flows, methodologies, scripts, and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR, and reduce manual intervention.* Participate in timing, power, EM/IR integrity, signal/power noise, and DRC/LVS/ERC verification for sign-off readiness.* Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization.* Debug physical design issues and interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.**$127,400 - $184,400 USD**We use artificial intelligence to screen, assess, or select applicants for the position.### ## **Qualifications:****Minimum Qualifications:**Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 6+ years of experience in:* Hands-on digital/SoC physical design (synthesis through P&R and sign-off).* Industry-standard EDA tools (e.g., Synopsys IC Compiler/Fusion, Cadence Innovus/Encounter, PrimeTime, STAR-RCX, Calibre) for high-speed digital ASIC/SoC implementation.* Scripting/programming (TCL, Python, Perl, shell) for flow automation and productivity enhancement.* Physical design flow: floorplanning, CTS, placement, routing, power domain gating, clock domain crossing, multi-power domain design, timing closure, ECOs, and DRC/LVS/DFM resolution.* Power/IR analysis, signal/power integrity reporting, and corrective action planning.* Interfacing with front-end teams (RTL, architecture), CAD/EDA tool teams, and manufacturing/packaging teams.**Preferred Qualifications:*** Experience with advanced process nodes (7nm, 5nm or smaller) or FPGA/programmable logic device flows.* Familiarity with FPGA architecture: routing fabrics, programmable logic blocks (PLBs), on-chip networks, I/O rings, static/dynamic reconfiguration.* Expertise in low-power design methodologies, power grid design, power gating, multi-voltage domain implementation, and power sign-off flows.* Prior exposure to full-chip integration flows (block-to-chip convergence) and high-frequency (1 GHz+) timing closure.* Experience in high-volume manufacturing environments, including yield and DFM/DFY considerations.* Experience mentoring or leading small physical design sub-teams or owning major P&R blocks.### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr

An automotive giant is seeking a Staff ML Engineer for their ML Compute Platform to scale backend services and contribute to AI infrastructure. Responsibilities include designing software components, improving system efficiency, and leading initiatives. Candidates should have 7+ years of experience and expertise in languages like Go, C++, or Python, as well as a solid background in distributed systems. Join a team that's transforming mobility and tackling complex engineering challenges with AI applications. #J-18808-Ljbffr

About xAI xAI's mission is to create AI systems that can accurately understand the universe and aid humanity in its pursuit of knowledge. Our team is small, highly motivated, and focused on engineering excellence. This organization is for individuals who appreciate challenging themselves and thrive on curiosity. Engineers are encouraged to work across multiple areas of the company, and as a result, all engineers and researchers share the title "Member of Technical Staff." We operate with a flat organizational structure. All employees are expected to be hands-on and to contribute directly to the company's mission. Leadership is given to those who show initiative and consistently deliver excellence. Work ethic and strong prioritization skills are important. All engineers and researchers are expected to have strong communication skills. They should be able to concisely and accurately share knowledge with their teammates. xAI does not have recruiters. Every application is reviewed directly by a technical member of the team. About the Team The Starfleet team is responsible for creating the tools and systems necessary to drive frontier model performance. We collaborate closely with our research teams and AI tutor teams to develop new solutions that accelerate research progress across model capabilities, evaluation, safety, and alignment. About the Role In this role you might: Build features end-to-end: front-end, back-end, system design, debugging and testing Create innovative human data generation pipelines. Ensure that our overall data collection platform is secure, scalable, and delightful to use. Develop systems that improve our model's reasoning and agentic capabilities Innovating new ideas that bring us closer to our goal: to develop AI systems that can accurately understand the universe and aid humanity in its pursuit of knowledge. Exceptional candidates may have: Experience delivering high-quality web applications in rapidly changing environments - as a tech lead, former founder, etc. Experience collaborating in highly cross-functional environments Experience in connecting machine learning model behavior to data distribution and data quality Tech Stack Typescript, Python, Rust React, Express, PostgreSQL Location The role is based in the Bay Area [San Francisco and Palo Alto]. Candidates are expected to be located near the Bay Area or open to relocation. Interview Process After submitting your application, the team reviews your CV and statement of exceptional work. If your application passes this stage, you will be invited to a 15-minute interview (“phone interview”) during which a member of our team will ask some basic questions. If you clear the initial phone interview, you will enter the main process, which consists of four technical interviews: Coding assessment in a language of your choice. Front end technical interview, in React/Typescript Systems hands-on: Demonstrate practical skills in a live problem-solving session. Meet the Team: Present your past exceptional work and your vision with xAI to a small audience. Our goal is to finish the main process within one week. We don't rely on recruiters for assessments. Every application is reviewed by a member of our technical team. All interviews will be conducted via Google Meet. Annual Salary Range $180,000 - $440,000 USD California Consumer Privacy Act (CCPA) Notice #J-18808-Ljbffr

Meet the Team Splunk, a Cisco company, is building a safer, more resilient digital world with an end‑to‑end, full‑stack platform designed for hybrid, multi‑cloud environments. The Splunk AI Platform and Services team provides the core runtime and developer experience that power AI across Splunk and Cisco. We manage large-scale, multi-tenant LLM inference across major cloud providers and build platform services to support these workloads. We also provide VectorDB/RAG services and MCP services that make AI workloads secure, observable, and cost-efficient for product teams. On top of this foundation, we deliver agentic frameworks, SDKs, tools, and evaluation/guardrail capabilities that help teams quickly build reliable GenAI assistants and automation features. You'll join a group that sits at the intersection of distributed systems, ML, and developer experience, grounded in operational excellence and a culture of impact‑driven, cross‑functional collaboration. Your Impact Implement features for GenAI services and APIs that power chat assistants, and automation workflows across Splunk products. Help build and maintain RAG pipelines: retrieval orchestration, hybrid search, chunking & embeddings, and grounding with logs/events/metrics. Contribute to agentic and multi‑agent workflows using frameworks like LangChain or LangGraph, integrating with MCP tools, internal APIs, and external systems. Develop and refine developer‑facing SDKs, templates, and reference apps (primarily Python/TypeScript) that make it simple for other teams to compose tools, chains, and agents on top of it. Integrate with LangSmith or similar eval stacks to instrument prompts, capture traces, and run evaluations under the guidance of more senior engineers and scientists. Collaborate with product managers and UX to turn user stories into GenAI experiences, iterate based on feedback, and ship features that move customer and business metrics. Apply and advocate responsible AI practices in day‑to‑day work: grounding, guardrails, access controls, and human‑in‑the‑loop flows. Minimum Qualifications: Bachelor's degree in computer science, Engineering, or equivalent practical experience. 5+ years of hands‑on experience building and operating backend or distributed systems in production or 2+ years of experience with a Master's degree Proficiency in at least one modern programming language (e.g., Python, TypeScript/JavaScript, Go, or Java) and solid software design/debugging skills. Some hands‑on experience with LLM APIs and ecosystems (e.g., OpenAI, Claude, Bedrock, or OSS models such as Llama) and related production features. Familiarity with web APIs and microservices (REST/gRPC), including testing, deployment, and basic observability (logs/metrics). Demonstrated ability to work end‑to‑end on features: collaborate on design, implement, write tests, help deploy, and iterate based on metrics or feedback. Preferred Qualifications: Experience or strong interest in RAG systems and vector databases (Weaviate, Qdrant, Milvus, FAISS, etc.). Exposure to agentic frameworks (LangChain, LangGraph, LlamaIndex, Semantic Kernel, or similar) and tool/agent orchestration patterns. Familiarity with LangSmith or similar evaluation platforms, or experience instrumenting prompts/pipelines for quality and debugging. Background contributing to platform or Developer experiences capabilities: internal libraries, SDKs, templates, or shared components that other engineers use. Experience with full‑stack development for GenAI interfaces (React/TypeScript), including prompt UX or conversation flows, is a plus. Understanding basic AI safety and governance concepts (guardrails, data privacy, RBAC) and how they apply in an enterprise environment. Strong communication skills and a growth mindset, comfortable asking questions, giving/receiving feedback, and learning from more senior teammates. Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $181,000.00 to $235,000.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job‑related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non‑exempt employees 1 paid day off for employee's birthday, paid year‑end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non‑exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full‑time employees Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non‑sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance‑based incentive pay on top of their base salary, which is split between quota and non‑quota components, subject to the applicable Cisco plan. For quota‑based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non‑quota‑based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $181,000.00 - $270,300.00 Non‑Metro New York state & Washington state: $165,300.00 - $240,600.00 For quota‑based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non‑exempt, will participate in a unique time off program to meet local requirements. Cisco is an affirmative action and equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records. #J-18808-Ljbffr

A leading technology company in San Mateo is seeking an exceptional founding design engineer to create intuitive product experiences. The role requires expertise in TypeScript and React, with responsibilities that include crafting polished user interfaces and translating advanced AI technologies into high-quality products. Candidates should have a strong design sensibility and experience shipping products used by millions. This opportunity offers competitive compensation and a dynamic work culture. #J-18808-Ljbffr

A technology firm specializing in integrated task systems seeks a Machine Learning Researcher / ML-Ops Engineer to advance computer vision and sensor fusion capabilities. The role involves implementing machine learning pipelines and optimizing models for deployment. Candidates should have a strong Python background and experience in deep learning frameworks like PyTorch and TensorFlow. This position in Palo Alto, California, offers competitive compensation and a collaborative work environment. #J-18808-Ljbffr

Since its founding in 2015, 1X has been at the forefront of developing advanced humanoid robots designed for household use. Our mission is to create an abundant supply of labor via safe, intelligent humanoids. We strive for excellence in all we do, solving some of the hardest problems in robotics with the world's most talented individuals. Every part of our robots is designed and produced in-house-from motor coils to AI-reflecting our vertically integrated approach. At 1X, you'll own real projects, be recognized for your achievements, and rewarded based on merit. Why this job is exciting Join the NEXT team shaping the foundations of the future humanoid robot Tackle unsolved challenges like human-level walking, dexterous manipulation, and embodied perception Push the boundaries of research into practical, buildable solutions-fast Responsibilities Research, design, and prototype fundamental humanoid technologies including actuation systems, robotic joints, and structural components Model and simulate systems to evaluate performance and feasibility Design experiments and analyze results to validate hypotheses and inform engineering tradeoffs Build and iterate on physical prototypes using machining, rapid fabrication, and embedded systems Evaluate academic research and patents for technical inspiration and practical application Distill high-concept ideas into actionable engineering workstreams Collaborate closely with other domain experts to bridge theory and application Requirements Strong grasp of core engineering principles including math, mechanics, and materials Experience designing actuation systems-motors, drivetrains, joints, structures Background in Mechanical Engineering, Electrical Engineering, Physics, or similar Demonstrated ability to go full-stack in R&D: from concept to prototype to evaluation Skilled at assessing feasibility and filtering high-potential ideas from theoretical noise Nice-to-haves Passion for building, tinkering, or technical exploration-professional or personal Portfolio of personal or professional projects you've designed and built Experience developing novel systems from scratch-not just incremental improvements Interest in human biomechanics or the nervous system as it relates to robotics Strong communication skills and ability to present bold technical concepts Appreciation for historical inventors and scientific pioneers PhD in a relevant technical field Location Policy We believe the best work is done when collaborating and therefore require in-person presence in our office locations. Not sure if this is you? If you're excited about 1X and this role but not sure if you qualify, apply anyway! You may be the right candidate for this or other roles. 1X is an inclusive and equal-opportunity employer that values diversity. We consider all qualified applicants regardless of race, religion, gender, age, sexual orientation, disability, or any other protected class. If you have a disability or special need that requires accommodation, please let us know. We will do our best to accommodate your needs. We're excited to get to know you and the prospect of having you on board! #J-18808-Ljbffr

A tech innovation company in Mountain View, California, is seeking a Machine Learning Research Engineer. You'll design sophisticated robot learning algorithms to enhance dexterous manipulation in home environments. The role requires 3+ years in machine learning for robotics and proficiency with Python, particularly PyTorch. This is an opportunity to join a passionate team working at the forefront of robotics technology, ensuring personal robots are accessible for everyday households. #J-18808-Ljbffr

About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical designs, and will help Etched as we work to improve iteration speed on physical design. Representative projects Supervise the outsourcing of physical design to a 3rd party service Deeply understand what is involved in physical design Running Physical Design flows to close blocks, support ASIC infrastructure, automate Physical Design flows, improve CAD infrastructure Drive dashboards that show the convergence of projects related to Physical Design Optimize tool flows, working with EDA vendors to incorporate the latest features Accountable for block level closure Requirements 2+ years of previous experience with PD Tools, flow, and design methodology from RTL synthesis to GDSII sign-off Experience with back-end design and timing closure on 3nm-7nm Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis Deeply creative and able to think from first principles Desired qualifications: Familiarity with transformer models and machine learning. Familiarity with Cadence or Synopsys automated RTL-to-GDSII flows Ability to program with Python or another scripting language. We encourage you to apply even if you do not believe you meet every single qualification. Benefits: Full medical, dental, and vision packages, with generous premium coverage Housing subsidy of $2,000/month for those living within walking distance of the office Daily lunch and dinner in our office Relocation support for those moving to West San Jose Compensation Range $150,000 - $275,000 How we're different: Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. #J-18808-Ljbffr

A tech company specializing in AI is seeking a Machine Learning Engineer to enhance its platform by developing and deploying generative AI models. You will collaborate with cross-functional teams to integrate technologies, manage AI models focusing on natural language processing, and work in a fast-paced environment. A Bachelor's degree in Computer Science and expertise in Python and machine learning techniques is required. #J-18808-Ljbffr