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Staff Engineer jobs at Proofpoint - 32597 jobs
Senior Opto-Mechanical Engineer
Applied Materials
Santa Clara, CA jobs
Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world - like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. You'll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. Visit our Careers website to learn more. At Applied Materials, we care about the health and wellbeing of our employees. We're committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Aid in the establishment and management of packaging suppliers and related processes and procedures. Develop test plans and perform laboratory testing on products, packages, and packaging materials. Support the Product Life Cycle (PLC) process by defining Design For Transportability (DFT) requirements and influencing product design. Develop and maintain global packaging standards and specifications for Applied Materials and its Supply Base. Provide advanced training and support to Packaging Engineer III. Duties will vary according to the project in progress and/or the specific goals of the department in which the incumbent works. Demonstrates depth and/or breadth of expertise in own specialized discipline or field May lead functional teams or projects with moderate resource requirements, risk, and/or complexity Impacts the achievement of customer, operational, project or service objectives; work is guided by functional policies At Applied Materials' CTO office, we are developing optical interconnect solutions for the next generation hyperscale computing and AI/ML. You will be working with a highly capable international team to develop advanced photonics packaging solution. You will lead optomechanical design, optical sub-assembly design, micro optics, fixture and tooling development. Those fixtures and tooling are expected to achieve micron level assembly accuracy. You are also expected to design / develop multi-fiber optical connectors and work with external vendors to develop connector eco-system. You are also expected to be familiar with various materials used in photonics industry, including but not limited to: glass, epoxy, silicon and other related materials. You daily activities includes working with 3D solid models, drawings, and documentation utilizing GD&T principles; assessing designs against environmental requirements; With a product focus, the individual will actively partner with other engineering disciplines and operations personnel to develop solutions that adhere to DFT and DFM requirements. D in optics, or mechanical engineering is desired. Industrial experience in optical communication industries is required. You should have expert level knowledge on optomechanical design, Solidworks or ProE, GD&T and ASME 14.5. Understanding of FEA for stress and thermal analysis, ideally understand the use of Ansys Mechanical and Icepak simulation tools Appreciation for Structured Problem Solving Full time Travel: Relocation Eligible: The salary offered to a selected candidate will be based on multiple factors including location, hire grade, job-related knowledge, skills, experience, and with consideration of internal equity of our current team members. In addition to a comprehensive benefits package, candidates may be eligible for other forms of compensation such as participation in a bonus and a stock award program, as applicable. For all sales roles, the posted salary range is the Target Total Cash (TTC) range for the role, which is the sum of base salary and target bonus amount at 100% goal achievement. Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law. In addition, Applied endeavors to make our careers site accessible to all users. If you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_****************, or by calling our HR Direct Help Line at ************, option 1, and following the prompts to speak to an HR Advisor. This contact is for accommodation requests only and cannot be used to inquire about the status of applications.$127k-164k yearly est. 2d agoHead of Service Engineering
Applied Materials
Round Rock, TX jobs
Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world - like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. You'll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. Visit our Careers website to learn more. At Applied Materials, we care about the health and wellbeing of our employees. We're committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Forecasts financial, manpower, and operational requirements for key businesses (start up, warranty, service agreements, paid service). Identifies and pursues service agreement business in conjunction with marketing and sales. Manages start ups in terms of time and cost requirements. Manages local inventories and RMA procedure. Manages systems start up and warranty cost under reserve. Ensures customer satisfaction with Company service and system performance. Interviews, hires, and trains customer engineers as necessary to support regional business establishing training and career development plans. Ensures the appropriate safety practices among customer engineers. Escalates system downs according to valid escalation procedure, to ensure earliest possible return to service. Achieves guaranteed up time and other parameters as sold to customers Promotes quality improvement processes to: - drive continuous improvement of technical performance - Responsible for following departmental procedures to safeguard the health, safety and welfare of themselves and those around them who may be affected by their acts or omissions Manages multiple related teams, sets organizational priorities and allocates resources Impacts the business results of a team or area by supporting and funding of projects, products, services and/or technologies and developing policies and plans Guided by business unit, department or sub-functional business plans Influences others internally and externally, including senior management Position requires understanding of Applied Materials global Standards of Business Conduct and compliance with these standards at all times. This includes demonstrating the highest level of ethical conduct reflecting Applied Materials' core values. #Full time Travel: Relocation Eligible: The salary offered to a selected candidate will be based on multiple factors including location, hire grade, job-related knowledge, skills, experience, and with consideration of internal equity of our current team members. In addition to a comprehensive benefits package, candidates may be eligible for other forms of compensation such as participation in a bonus and a stock award program, as applicable. For all sales roles, the posted salary range is the Target Total Cash (TTC) range for the role, which is the sum of base salary and target bonus amount at 100% goal achievement. Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law. In addition, Applied endeavors to make our careers site accessible to all users. If you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_****************, or by calling our HR Direct Help Line at ************, option 1, and following the prompts to speak to an HR Advisor. This contact is for accommodation requests only and cannot be used to inquire about the status of applications.$105k-135k yearly est. 2d agoSenior Aerospace Engineer - Aircraft Components
United Airlines
San Francisco, CA jobs
A leading airline company in San Francisco is seeking an experienced aircraft maintenance engineer to analyze and resolve technical challenges, ensure regulatory compliance, and provide detailed project management. Candidates should possess a Bachelor's degree in Engineering and have extensive knowledge in airline operations. This full-time role offers competitive compensation and a comprehensive benefits package. #J-18808-Ljbffr$104k-133k yearly est. 1d agoStaff ML Engineer - AI-Powered Observability Platform
Cisco Systems
San Jose, CA jobs
A global technology company is looking for a seasoned software engineer to enhance AI capabilities within their observability platform. Candidates should have a strong background in AI/ML systems, cloud computing, and robust technical leadership. This role is pivotal in driving innovation in data analysis and delivering scalable solutions. The ideal candidate will thrive in an agile environment and provide mentorship to junior engineers. Enjoy competitive salaries and benefits while contributing to impactful technology solutions. #J-18808-Ljbffr$151k-191k yearly est. 2d agoSenior ASIC Physical Design Engineer
Google Inc.
Sunnyvale, CA jobs
corporate_fare Google Sunnyvale, CA, USA Apply Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 7 years of experience with physical design (e.g. from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure). Experience in Python, Tcl, or Perl scripting. Preferred qualifications: Experience working with external partners on Physical Design (PD) closure. Experience in Static Timing Analysis (STA), with an understanding of how to define timing corners, margins and derates. Experience with Synopsys/Cadence PnR tools. Experience with backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.). Understanding of DFT including Scan, MBIST and LBIST. Understanding of performance, power and area (PPA) trade-offs. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As an ASIC Physical Design Engineer, you will collaborate with RTL, Design for Testing (DFT), Floorplan, and full‑chip Signoff teams. Additionally, you'll solve technical problems with innovative micro‑architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full‑time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Participate in the Physical Design of complex blocks. Contribute to the design and closure of the full chip and individual blocks from RTL‑to‑GDS. Collaborate with internal logic and internal and external teams to achieve the best Power/Performance Analysis (PPA). This includes conducting feasibility studies for new microarchitectures as well as optimizing runs for finished RTL. Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr$144k-186k yearly est. 4d agoSenior ASIC RTL Design Engineer
Advanced Micro Devices
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE As a member of the AMD, you will help bring to life cutting‑edge designs and deliver IPs to SOC. As a member of the front‑end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first‑pass silicon success. THE PERSON You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem‑solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi‑site environment are keys to being successful in this role. KEY RESPONSIBLITIES RTL design of high speed design, clock/reset/power features, IP Integration, sub‑system level design Architect and design of power management features. Design optimization for implementing power efficient IP, implementing the RTL using low power techniques Responsible for the inter‑IP integration issues resolution Own the Clock‑Domain crossing, Linting aspects of the overall design of the IP and the subsystem Work closely with FEINT, DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Architecting, micro‑architecting and documentation of the design features Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. REFERRED EXPERIENCE Extensive experience in Digital IP/ASIC design and Verilog RTL development Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification Well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects. Should possess expertise in front‑end EDA tools sign‑off and its flows Familiarity with low power design and low power flow is an added plus Ability to program with scripting languages such as Python or Perl is a plus Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements Proven interpersonal skills, leadership and teamwork Excellent writing skills in the English language, editing and organizational skills required; Skilled at prioritization and multi‑tasking Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts Knowledge of, or experience in, functional design verification or design is highly desired ACADEMIC CREDENTIALS Bachelors or Masters degree in computer engineering / Electrical Engineering This role is not eligible for visa sponsorship. LOCATION: Santa Clara, CA Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr$112k-148k yearly est. 5d agoSenior ASIC RTL Design Engineer - Power & IP Focus
Advanced Micro Devices
Santa Clara, CA jobs
A leading semiconductor company in Santa Clara, CA, seeks a skilled digital design engineer. The role involves RTL design, power management features, and collaboration across teams. Candidates should have strong Verilog skills and experience in IP design. A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required. This position offers an opportunity to be part of a company that values innovation and teamwork, but it is not eligible for visa sponsorship. #J-18808-Ljbffr$112k-148k yearly est. 5d agoGPU/ML Shader Core ASIC Design Engineer
Advanced Micro Devices
Santa Clara, CA jobs
A leading technology company in Santa Clara seeks an experienced ASIC Design Engineer specializing in GPU/ML Shader Core. In this role, you will define micro-architecture, implement RTL, and collaborate with various engineering teams. Ideal candidates will have experience in micro-architecture and an undergraduate degree in Computer Engineering or Electrical Engineering. Enjoy a vibrant culture that fosters innovation and teamwork, while pushing the boundaries of next-generation computing. This role does not offer visa sponsorship. #J-18808-Ljbffr$112k-148k yearly est. 5d agoASIC Design Engineer, GPU/ML Shader Core
Advanced Micro Devices
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an ASIC Design Engineer, GPU/ML Shader Core who are motivated to challenge the status quo. If you are excited about building the next generation GPU/MI shader core, our team is on the lookout for you! You will be part of a fast-paced team working on the Graphics shader design, a team of engineers of varied disciplines who are responsible for micro-architecting, designing, and delivering GPU and ML/AI shader IP for various products. Since we are the heart of GPU engine, we strive to challenge ourselves in exceeding area, power, and performance targets. No idea is too small; we welcome every initiative that makes our product better. THE PERSON: You are an “out of the box” thinker, motivated to absorb dynamic changes and thirsty to keep innovating. You will work on the sub-block inside programmable engine aka shader core of the GPU. The shader core plays a key role in running applications program, feeding, and consuming the data to/from GPU shader resources and computing mathematical operations. Collaborate with software, architect, micro-architect and logic design team members to define and tackle “how to efficiently own an application program with the least number of instructions and data transfer while consuming the least amount of power”. Strong interpersonal skills and an excellent teammate. KEY RESPONSIBILITIES: Collaborate with block architect, ASIC designers and verification engineers to define and document block micro-architecture and analyze architectural trade-offs based on features, performance requirements and system limitations Responsible for owning full design cycle from defining micro-architecture, implementing RTL, and deliver fully verified and PD timing clean design. Consult DV engineers in describing features, outlining test plans, and closing on coverage Assist DV engineers to debug functional, performance or power test failures Work with Physical Design team to close on timing, area and power requirements PREFERRED EXPERIENCE: Experience in micro-architecture and RTL development (Verilog), focused on GPU/CPU/ML/AI pipelines, arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required. ACADEMIC CREDENTIALS: Undergraduate degree required. Bachelors or Masters degree in Computer Engineering/Electrical Engineering preferred. LOCATION: Santa Clara CA - San Diego CA - Folsom CA This role is not eligible for Visa sponsorship. Benefits offered are described: AMD benefits at a glance AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr$112k-148k yearly est. 5d agoOn-Device CVML Engineer for Spatial AI
Apple Inc.
Sunnyvale, CA jobs
A leading technology company in Sunnyvale is seeking a dedicated engineer for machine learning systems, focusing on AI and spatial computing. The role requires expertise in deep learning frameworks and strong programming skills in C++, Swift, and Python. Responsibilities include developing advanced AI systems, collaborating with cross-functional teams, and pushing the boundaries of innovation with real-world applications. This position offers competitive compensation with a base pay range of $181,100 to $318,400, alongside comprehensive benefits. #J-18808-Ljbffr$181.1k-318.4k yearly 1d agoOn-Device ML Optimization Engineer (LLM & Diffusion)
Apple Inc.
Seattle, WA jobs
A leading technology company in Seattle is seeking a Large Machine Learning Model Optimization Engineer. You will drive the development of on-device ML models, collaborate across teams, and implement optimization techniques for performance improvement. A BS degree and strong Python skills are required, alongside a passion for shipping machine learning models. The role offers a competitive salary ranging from $139,500 to $258,100, along with comprehensive benefits and stock options. #J-18808-Ljbffr$139.5k-258.1k yearly 3d agoSenior ASIC/RTL Design Engineer: SoC Timing & RTL
Advanced Micro Devices
San Jose, CA jobs
A technology company in San Jose is seeking a Senior ASIC/RTL Design Engineer to contribute to the development of large SoCs. The role requires expertise in RTL ownership, complex timing constraints, and EDA tools, alongside strong communication skills. Candidates should have a Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. This is a non-remote role requiring in-person presence, and does not offer visa sponsorship. #J-18808-Ljbffr$112k-148k yearly est. 2d agoASIC/RTL Design Engineer
Advanced Micro Devices
San Jose, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE AMD is looking for a Senior ASIC/RTL Design Engineer to contribute to the development of large SoCs, featuring multiple physical blocks and complex timing constraints. The candidate's responsibilities will include RTL ownership and integration, building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred. THE PERSON The ideal candidate demonstrates high energy, excellent written and verbal communication skills, and a structured, organized approach to work. They are collaborative and strongly focused on achieving team and organizational goals. KEY RESPONSIBILITIES Responsible for RTL design and integration. Contribute to all aspects of SoC design including chip definition, architecture development and modeling, development of micro-architectural specification, conversion of micro-architectural specifications to logic implementation, verification, emulation, debug, synthesis and timing closure. Develop complex multi-mode/multi-corner timing constraints that are compatible for RTL and signoff. Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency. Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA (static timing analysis) checks. Collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows. Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts). Continuously review and identify areas for process improvements and early issue detection during the design phase. PREFERRED EXPERIENCE Experience with SoC designs that includes RTL design and integration. Worked with EDA tools that enable RTL quality checks. Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Ability to multitask, grasp new flows/tools/ideas. Experience in improving the methodologies. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT). Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters. Strong analytical and problem-solving skills. ACADEMIC CREDENTIALS Bachelor's or Master's degree in Electrical Engineering or Computer Engineering LOCATION San Jose This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr$112k-148k yearly est. 2d agoASIC Design STA Engineer for RTL/QoR Automation
Advanced Micro Devices
San Jose, CA jobs
A leading semiconductor company is seeking an ASIC Design STA engineer in San Jose, CA to contribute to the development of large SoCs. You will be responsible for building and verifying timing constraints and collaborating on complex design projects. Ideal candidates should have strong SDC and EDA tool expertise, along with experience in Tcl scripting. This role offers a collaborative work environment and is hybrid. #J-18808-Ljbffr$112k-148k yearly est. 3d agoProduct Engineer: Build Developer-First AI Tools
Cognition
San Francisco, CA jobs
A cutting-edge AI lab in San Francisco is seeking experienced end-to-end engineers to join their small, talent-dense team. The role involves building innovative software products, enhancing user experiences, and collaborating closely with product teams. Ideal candidates should have experience with Python, Typescript, and React. Strong achievers who thrive in fast-moving environments are encouraged to apply. #J-18808-Ljbffr$90k-126k yearly est. 4d agoOS Intelligence ML Engineer - On-Device AI for OS
Apple Inc.
Cupertino, CA jobs
A global technology company based in California seeks a talented individual to design and develop Deep Learning architectures. This role involves creating intelligent experiences through innovative Machine Learning solutions, collaborating with various teams, and requires a strong programming background. Candidates should hold a Bachelor's degree in Computer Science or similar, with familiarity in Python, Objective C, or Swift and relevant project experience. Competitive salary and extensive benefits offered. #J-18808-Ljbffr$138k-174k yearly est. 1d agoPrincipal Mechanical Engineer - Robotics Subsystems Lead
Boston Dynamics, Inc.
Waltham, MA jobs
A leading robotics company in Waltham is seeking a Principal Mechanical Engineer for its Spot robot team. You will lead cross-functional teams to develop and implement complex robotic subsystems. The ideal candidate must hold a BSME with at least 10 years of relevant experience, including advanced skills in CATIA and strong technical writing. This position offers a competitive salary range and generous benefits including medical, dental, vision, 401(k), and paid time off. #J-18808-Ljbffr$110k-143k yearly est. 1d agoSenior Electronics Engineer - Space Systems (SkillBridge)
Northrop Grumman Corp. (Au
Baltimore, MD jobs
A leading aerospace and defense company in Baltimore is offering a SkillBridge internship for the role of Principal Electronics Engineer. This position involves the design and fabrication of Electrical Ground Support Equipment (EGSE) to support flight hardware testing. Candidates should possess a Bachelor's degree in STEM and relevant experience in hardware design. An Active Secret security clearance is also required for this role. Join us to make an impact in the defense sector. #J-18808-Ljbffr$90k-116k yearly est. 2d agoSenior Electronics Engineer - Ground Systems Integration Lead
Northrop Grumman Corp. (JP
San Diego, CA jobs
A leading aerospace and defense company is looking for a Senior Principal Electronics Engineer - Hardware and Software Integration Lead in San Diego. This role involves leading the development of next-generation ground system solutions, managing software supplier interactions, and coordinating various engineering efforts. Candidates should have a strong background in STEM, relevant work experience, and active security clearance. The position requires on-site work but could offer hybrid options in the future. #J-18808-Ljbffr$92k-121k yearly est. 2d agoMEP Project Engineer
G&E Partners
Miami, FL jobs
MEP Project Engineer - High-Rise Construction (Miami, FL) G&E Partners is partnered with a leading high-rise General Contractor in Miami that is actively expanding its project teams due to a strong pipeline of luxury residential and mixed-use tower projects. This is a fully on-site role supporting complex, multi-story builds and offers long-term career progression within a growing Florida operation. Responsibilities Support MEP scopes across all phases of high-rise construction Coordinate with mechanical, electrical, plumbing, and fire protection subcontractors Review submittals, RFIs, shop drawings, and MEP schedules Track procurement and long-lead equipment (switchgear, generators, chillers, etc.) Assist with inspections, testing, and commissioning activities Work closely with Project Managers, Superintendents, and BIM/VDC teams Maintain documentation and ensure compliance with contract requirements Requirements 1-5+ years of experience in construction, ideally with a GC or large MEP subcontractor Exposure to high-rise, multifamily, hospitality, or large commercial projects preferred Strong understanding of mechanical, electrical, and plumbing systems Degree in Construction Management, Engineering, or related field preferred Comfortable working fully on-site in Miami Why Join Career-defining high-rise projects (30+ to 100+ stories) Strong project backlog and long-term stability Clear path into MEP Project Management Competitive salary, bonus, and full benefits package$69k-95k yearly est. 2d ago
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