Design Verification Engineer jobs at Qualcomm - 85 jobs

Company: Qualcomm Technologies, Inc.Job Area: Engineering Group, Engineering Group > ASICS Engineering As a leading technology innovator, Qualcomm pushes the boundaries to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, validate digital/analog designs and develop a comprehensive validation/verification testbench environment for projects that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions that meet performance, security, technology, and feature requirements. As a Design Verification Engineer, you will work with Chip Architects to validate the concepts of core and sub-system level micro-architectures. You will work on a selected part of the subsystem Design Verification to ensure that it functions to the standards of being launch ready for the end Product. Role and Responsibilities Work with subsystem and SOC Architects to understand the concepts and high-level system requirements. Develop detailed Test and Coverage plans based on the Architecture and Micro-architecture. Develop Verification Methodology, ensuring scalability and portability across environments. Develop Verification environment, including all the respective components such as Stimulus, Checkers, Monitors Assertions, and Coverpoints. Develop Verification Plans and Testbenches for your functional domain. Execute Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures. Track and report DV progress using a variety of metrics, including Bugs and Coverage. Preferred Qualifications Deep knowledge of APB/AXI/SPI protocols, handshake mechanisms, cross-clock domains and clock gating. Solid understanding of memory organization, fault-tolerant design, parity schemes, error detection and error correction schemes. Advanced techniques such as: Formal, Assertions, and Silicon bring-up, is helpful. In-depth knowledge of Micro-processor functions, Network-on-Chip Architectures, and Micro-architectures. Experience in writing Testplans, portable Testbenches, Transactors, and Assembly code. Experience with different Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Mixed signal Verification. Ability to develop and work independently on a Block/Unit of the design. Qualifications Minimum Experience Level should be 2+ years in SOC-level or core-level verification with good understanding of debugging either ARM-based or RISC-V based processors, good understanding of APB/AHB/AXI protocols. Must have solid understanding of SV/UVM concepts. Prior experience in any cryptographic algorithm is preferred. Must have basic understanding of UNIX commands and Python/Perl scripting Minimum Qualifications • Bachelor\'s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master\'s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm\'s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm, which also includes a discretionary bonus program and potential RSU grants. Our benefits package supports success at work, at home, and at play. Your recruiter can discuss details, and you can review more about US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Join Qualcomm's design verification team in verifying the high‑speed mixed‑signal IP designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IoT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system‑level concept to tape‑out and post‑silicon support. Responsibilities: Define pre‑silicon and post‑silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post‑silicon validation. From scratch VIP development experience for Serdes controller + PHY is an additional plus. Required for this Role: Master's/Bachelor's degree in Electrical Engineering, Computer Engineering, or related field. 2+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications: Experience with Low Power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc. Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors. Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Equal Opportunity Employer Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Accommodations for Individuals with Disabilities If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm will provide an accessible process. Email disability-accomodations@qualcomm.com or call Qualcomm's toll‑free number for assistance. Pay Range & Other Compensation & Benefits $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants. In addition, our highly competitive benefits package supports your success at work, at home, and at play. Contact If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Architects, designs, implements, verifies, and optimizes performance and power of GPU cores. Responsible for verification of Graphics IP, and performing pre- and post-silicon verification to verify correctness and ensure performance and power goals are met. Responsibilities Owning and executing on key independent tasks towards program requirements Using verbal and written communication skills to convey basic, routine factual information about day-to-day activities to others who are fully knowledgeable in the subject area. Working within prescribed timeline requirements and resource constraints Applying independent creative thought to troubleshoot technical problems or deal with novel circumstances. Research through available resources and engagement with various inter-disciplinary teams Using deductive problem solving to solve moderately complex problems; most problems have defined processes of diagnosis/detection; some limited data analysis may be required. Principal Duties and Responsibilities Applies Graphics knowledge and experience to architect, design, implement, and verify the structure and performance of GPU hardware, drivers, features, applications, and tools. Creates and maintains verification test benches and environments in System Verilog/UVM Create and leverage advanced testing frameworks to generate and recreate real-world system integration conditions Collaborates with Architecture, Software, Firmware, Design, Modeling, Emulation and Post-silicon validation teams to define and develop test methodology and content Participate in GPU architecture, micro-architecture reviews Collect, organize and execute various forms of system level test content including directed testcases, gaming benchmarks, standards compliance testsuites, and system level scenarios Build automation for continue integration and testing based on latest GPU IP Help collect and analyze test results using straightforward statistics and data predictions to track benchmarks and identify issues Works with team members to understand and align on narrow scope of feature development and meet targets. Write technical documentation and feature descriptions for straightforward projects under the direction of a supervisor. Minimum Qualifications Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. Preferred Qualifications 5+ years Hardware Engineering, Software Engineering, Systems Engineering, or related work experience Verification skills: Test planning, Scripting, Simulation, problem solving and debug. System Verilog, UVM, Verilog or VHDL, C/C++ skills required. Constrained random, Functional Coverage development, design debug experience required. Exposure to Emulation/Prototyping Platforms (Veloce, Palladium, Zebu, FPGA) Master's Degree in Electrical or Computer Engineering, Computer Science, or related field. 2+ years relevant GPU experience (either external or internal). Preferred Skills Experience in GPU based verification Experience in system or sub-system level verification Concurrency, Preemption, Stress testing frameworks Testbench Architecture and Implementation GFX API Exposure : Vulkan/DX11/DX12 Exposure Scripting and automation skills (Python, Make, Airflow etc) Embedded FW Development and Debugging Benchmarking and Performance Analysis Windows and/or Linux OS Kernel Architecture C/C++, GNU Toolchain, Visual Studio Formal verification - FPV and DPV experience is a plus Experience with emulation/prototyping/hybrid build and execution flows (Veloce, Palladium, Zebu, Protium, HAPS, qemu) Development of synthesizable transactors, monitors, scoreboards for emulation platforms Embedded FW and/or Kernel level development and debugging skills (C/C++, Makefile, gdb, uboot, uefi, kernel-mode drivers) This role is available in multiple locations at different levels. The compensation range will be determined upon the offer location and title. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may omail disability-accomodations@qualcomm.com for accommodations. Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Pay range and Other Compensation & Benefits: $161,800.00 - $273,400.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is one component of total compensation; Qualcomm also offers a discretionary bonus program and RSU grants. For more details about US benefits, see the internal benefits information. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering The DTECH team is part of the Global SOC organization and is responsible for STA methodology and signoff, foundry technology enablement and analysis, design automation and internal and external EDA tools, design analysis and optimization tools and platforms, low power architecture, methodology, and IP, and foundation IP development. About the Role As a member of the DTECH Methodology team, you will work closely with core and SOC teams to enable a state-of-the-art design analytics platform. Your work will have a consequential impact on the power, performance, area, and quality of Qualcomm's products. Required for this Role M.S/Ph.D. degree in Electrical Engineering or Computer Science with 1-2 years of relevant experience with ASIC/VLSI design tools and flows Strong programming skills in Python Hands‑on experience with static timing analysis (STA) tools, e.g., PrimeTime and Tempus Problem‑solving and analytical mindset Preferred Qualifications Critical thinking with good software architecture understanding to develop platforms at scale Familiarity with GenAI models (e.g., LLMs such as GPT, Llama, etc.) and their application in real‑world solutions, such as chatbots, etc. Experience designing and developing agentic AI systems Experience with version control tools like Perforce or Git Experience with place & route tools and a good understanding of the ASIC RTL‑GDSII design flow Where you will be working - this role requires the candidate to be onsite in San Diego or Santa Clara, CA. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. Please e‑mail disability‑accommodations@qualcomm.com or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Pay range and Other Compensation & Benefits: $115,600.00 - $173,400.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

A leading technology company is seeking a Senior RF Design Engineer in San Diego to develop RF subsystems for advanced communications. The role requires a Bachelor's degree in Electrical Engineering and at least 5 years of RF hardware experience. Responsibilities include PCB layout, RF performance tuning, and troubleshooting production issues. The compensation ranges from $140,000 to $190,000 annually. Benefits include medical, dental, vision, and paid time off. #J-18808-Ljbffr

A leading technology firm based in San Diego seeks an experienced ASIC Design Verification Engineer to verify high-speed mixed-signal IP designs. The ideal candidate has a degree in Electrical Engineering and at least 2 years of relevant experience. Responsibilities include defining testplans and developing testbenches using SystemVerilog/UVM methodologies. Competitive salary range of $140,000 - $210,000 with comprehensive benefits including bonuses and RSU grants. #J-18808-Ljbffr

Qualcomm is a global leader in wireless technology, driving innovation and shaping the future of connectivity. We are looking for talented and motivated individuals to join our team in San Diego, to contribute to cutting-edge projects and help us continue to lead the industry. Role Overview As a CAD Engineer specializing in design verification (DV), you will play a crucial role in (1) developing automation tools and flows for DV, (2) enabling state of the art EDA tools for Qualcomm DV teams, (3) exploring and applying the latest ML/AI technologies to improve DV workflow. You will also be responsible for creating comprehensive documentation, providing support to internal teams, and ensuring the efficiency and reliability of our automation processes. Key Responsibilities Apply engineering principles to develop and optimize CAD tools and flows to enhance productivity, efficiency, and results. Conduct research to stay updated with the latest industry trends (including ML/AI technologies) and incorporate new learnings into Qualcomm workflow. Provide technical support and training to internal teams on CAD automation tools and workflows. Collaborate with cross-functional teams to identify and implement improvements in automation processes. Propose and execute innovative solutions to complex problems, contributing to the continuous improvement of our CAD automation capabilities. Personal Character Traits Analytical: You possess strong analytical skills, enabling you to understand complex systems and identify areas for improvement. Resourceful: You are adept at finding creative solutions to challenges and are not afraid to think outside the box. Self-Motivated Learner: You are proactive in acquiring new knowledge and skills through self-guided research, training, and asking insightful questions. Problem Solver: Over time, you develop the ability to tackle higher-level problems, propose effective solutions, and execute decisions independently. Collaborative: You work well with others, sharing knowledge and supporting team members to achieve common goals. Qualifications for this Role Bachelor's degree in computer science or electrical engineering 2+ years of ASIC design, verification, validation, or related work experience Strong programming skills in languages such as Python, TCL, GNU Make and Perl Experience with DV EDA tools such as VCS, Xcelium and Questa Preferred Qualifications Master's degree or PhD in Computer Science or Electrical Engineering 5+ years of ASIC design, verification, CAD or related work experience Familiar with ML/AI techniques Experience in developing VLSI automation flows Knowledge of Hardware Description Languages like SystemVerilog Preferred Qualifications (Additional) Plus: Data science, ML/AI, VLSI CAD experience Minimum Qualifications Minimum qualifications include a Bachelor's degree or higher with related ASIC design/verification experience, or an equivalent combination of education and experience as specified by the job posting. For example: Bachelor's degree in Science, Engineering, or related field with 4+ years of relevant experience; or Master's degree with 3+ years; or PhD with 2+ years. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may provide disability accommodations via email or by calling Qualcomm's toll-free number. Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Pay range and Other Compensation & Benefits $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation. Qualcomm also offers a competitive annual discretionary bonus program and RSU grants. We also offer a comprehensive benefits package. Your recruiter can discuss details about Qualcomm benefits. For more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering/storage As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next‑generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimise, verify, and test حصہ electronic systems, bring‑up yield, circuits, mechanical systems, digital/analog/RF/optical, systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting‑edge, world class products. Qualcomm Hardware Engineers collaborate with cross‑functional teams to develop solutions and meet performance requirements. Minimum Qualifications (Degree) Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Electrical Engineering or related field and 4+ years of Hardware Engineering or related work experience. Master's degree in Computer Science, Electrical/Electronics Engineering, Electrical Engineering or related field and 3+ years of Hardware Engineering or related work experience. PhD in Computer Science, Electrical/Electronics Engineering, Electrical Engineering or related field and 2+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the high‑speed mixed‑signal IP designs Tierra (PLL, DAC, ADC, Sensors, PCIe, USB, MIPI, CXL, C2C, D2D, DDR, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the design verification lifecycle, from system‑level concept to tape out and post‑silicon support. Responsibilities Define pre‑silicon and post‑silicon test plans based on design specs and using applicable standards, working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Functional Verification, UPF/Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop test cases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post‑silicon validation. Minimum Qualifications (Verification Experience) Master's/Bachelor's degree in Electrical Engineering, Computer Engineering, or related field. 5+ years ASIC design verification, Pre‑Silicon Verification or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, and others. Preferred Qualifications Experience with Pre‑Silicon Verification, Low power design verification, Formal verification and Gate level simulation at IP/SS level. Experience in scripting languages (Python, or Perl). Experience with mixed‑signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Converters (DAC, ADC), or sensors will be Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑accommodations@qualcomm.com or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to Rx requests for updates on applications or resume inquiries).))/ Qualcomm expects its employees to abide by all applicable policies and procedures, including but (), commercial not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualified is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering As a leading technology innovator, Qualcomm pushes the boundaries to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, validate digital/analog designs and develop a comprehensive validation/verification testbench environment for projects that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions that meet performance, security, technology, and feature requirements. As a Design Verification Engineer, you will work with Chip Architects to validate the concepts of core and sub-system level micro-architectures. You will work on a selected part of the subsystem Design Verification to ensure that it functions to the standards of being launch ready for the end Product. Role and Responsibilities Work with subsystem and SOC Architects to understand the concepts and high-level system requirements. Develop detailed Test and Coverage plans based on the Architecture and Micro-architecture. Develop Verification Methodology, ensuring scalability and portability across environments. Develop Verification environment, including all the respective components such as Stimulus, Checkers, Monitors Assertions, and Coverpoints. Develop Verification Plans and Testbenches for your functional domain. Execute Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures. Track and report DV progress using a variety of metrics, including Bugs and Coverage. Preferred Qualifications Deep knowledge of APB/AXI/SPI protocols, handshake mechanisms, cross-clock domains and clock gating. Solid understand of memory organization, fault-tolerant design, parity schemes, error detection and error correction schemes. Advance techniques such as: Formal, Assertions, and Silicon bring-up, is helpful. In-depth knowledge of Micro-processor functions, Network-on-Chip Architectures, and Micro-architectures. Experience in writing Testplans, portable Testbenches, Transactors, and Assembly code. Experience with different Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Mixed signal Verification. Ability to develop and work independently on a Block/Unit of the design. Qualifications Minimum Experience Level should be 2+ years in SOC-level or core-level verification with good understanding of debugging either ARM-based or RISC-V based processors, good understanding of APB/AHB/AXI protocols. Must have solid understanding of SV/UVM concepts. Prior experience in any cryptographic algorithm is preferred. Must have basic understand on UNIX commands and Python/Perl scripting Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. #J-18808-Ljbffr

A leading semiconductor company in California is seeking a Design Verification Engineer to join a high-performance design team. The role involves developing verification environments, designing verification components, and analyzing simulation failures. Candidates should have over 12 years of experience and a Bachelor's degree in a relevant field. Strong knowledge of System Verilog and UVM is required. Competitive salary and benefits offered. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Analog Mixed Signal Design Qualcomm's Mixed‑Signal PHY design team is actively looking for an analog and mixed‑signal circuit designer to work on SerDes PHY designs. This designer will be involved in delivering next‑generation PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading‑edge CMOS process technology nodes at 7nm and beyond. Design goals also include low‑power analog designs to address Qualcomm's wireline interface need. Job Description: The primary responsibility of this position entails working within a team to deliver analog and mixed‑signal transistor‑level circuit designs along with supervising physical layouts of the high‑speed, low‑power PHY SerDes blocks. Experience with >32Gbps transceiver or clocking design is highly desired. Minimum Qualifications: Bachelor's Degree in Electrical Engineering with 2+ years of experience with analog or mixed‑signal integrated circuit design in nanometer planar CMOS or FinFET and 2+ years of ASIC design, verification, or related work experience. OR Master's degree in Electrical Engineering or related field and 2+ years of ASIC design, verification, or related work experience. OR PhD in Electrical Engineering or related field. 2+ years of experience using one or more design tools (e.g., CADENCE, SPICE, MATLAB, and/or Verilog/VHDL). Preferred Qualifications: PhD in Electrical Engineering or related field. 2+ years of experience in analog/mixed‑signal integrated CMOS circuit design for a specific area (e.g., VCO, PLL, and DLL design, Audio CODEC and Class D Audio amplifier design, Delta‑Sigma, SAR ADCs, Current‑Steering DACs, high‑speed DDR PHYs, high‑speed SERDES). Principal Duties and Responsibilities: Uses appropriate tools or databases to contribute to architecture and circuit designs for one or more blocks; participates in design reviews. Works with layout teams to oversee block‑level layout of one or more blocks. Defines and runs own simulations and analyses (e.g., power, performance) on designs; documents and utilizes results to improve and verify designs. Programs and runs tests to identify bugs in own work and helps more junior team members with the same; debugs most issues and escalates highly complex issues. Consults with internal or external users as directed to assist with implementation and achieve goal alignment. Maintains understanding of one's technical domain and builds understanding of other domains to ensure integration with different components. Writes detailed technical documentation and design descriptions to guide users and/or customers. Collaborates with team members to generate ideas. Level of Responsibility: Working under some supervision. Taking responsibility for own work and making decisions with limited impact; impact of decisions is readily apparent; errors made typically only impact timeline (i.e., require additional time to correct). Using verbal and written communication skills to convey basic, routine factual information about day‑to‑day activities to others who are fully knowledgeable in the subject area. Working within prescribed budget and resources. Completing most tasks with multiple steps which can be performed in various orders; some planning and prioritization must occur to complete the tasks effectively; mistakes may result in some rework. Exercising creativity to draft original documents, imagery, or work products within established guidelines. Using deductive problem solving to solve moderately complex problems; most problems have defined processes of diagnosis/detection; some limited data analysis may be required. May be solicited during strategic planning period. The responsibilities of this role do not include: Providing supervision/guidance to others. Influence over key organizational decisions. Equal Opportunity Employer Statement: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability-accomodations@qualcomm.com or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Pay range and Other Compensation & Benefits: $115,600.00 - $173,400.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering As a Design Engineer, you'll play a critical role in shaping cutting‑edge digital designs. Your responsibilities will include: Micro‑Architecture: Designing micro‑architecture for both simple and complex digital interface blocks. RTL Development: Developing RTL (Register Transfer Level) code using industry best practices. This includes handling multi‑clock designs, high‑frequency requirements, low power, and low latency considerations while ensuring high performance. Debugging and Post‑Silicon Bring‑Up: Troubleshooting and debugging issues during the development process and supporting post‑silicon bring‑up activities. Documentation: Creating comprehensive design documentation to ensure clarity and maintainability. Design Optimization: Optimizing designs for key metrics such as area, power, and performance. Cross‑Functional Collaboration: Collaborating with cross‑functional teams, including DFT (Design for Testability), Implementation, Verification, Emulation, and Firmware teams. Must be in San Diego full time, 5 days a week Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. Must be a U.S. citizen and eligible to receive a U.S. Government security clearance. Ideal candidate will have: 6‑10+ years of work experience with RTL/FPGA design (Verilog, System Verilog), embedded system architecture and Verification. Bachelor's degree in computer science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR Master's degree in computer science, Electrical/Electronics Engineering, Engineering, or related field and 5+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Preferred Qualifications: Positive Attitude: Bring a fun‑loving attitude and a passion for inclusively solving problems. Experience: 5+ years of ASIC design experience. RTL Expertise: System Verilog Design, Linting, CDC, Synthesis (FPGA and ASIC). Testing: Building the test suites for design validation. Emulation: Understanding of Emulation and prototyping flows for the design and validation in Lab is a big plus. Complex Digital Logic Design: Experience with designing complex digital logic blocks and sub systems (CPU, GPU, DSP, Always on Systems, Digital interfaces (PCIe, UART, I2C, DDRx, SPI, USB). ISA Familiarity: Knowledge of ISAs (Instruction Set Architectures) such as ARM THUMB or RISC‑V. Processor/Microcontroller System Design: Understanding of processor or microcontroller system design. Multi‑Power Domain and Multi‑Clock Domain Designs: Experience with designs spanning multiple power domains and clock domains. Scripting/Automation Languages: Proficiency in scripting or automation languages like Python or Perl. Industry Standard Digital Tools: Familiarity with state‑of‑the‑art industry‑standard digital design tools. Challenges of Lower Node Technologies: Awareness of challenges faced when working with lower node technologies. If you're excited about pushing the boundaries of digital design and collaborating with diverse teams, we encourage you to apply! Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. Disability accommodations may be requested by emailing disability‑************************** or calling Qualcomm's toll‑free number. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $147,600.00 - $246,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. Must be a U.S. citizen and eligible to receive a U.S. Government security clearance We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands‑on experience in RTL‑to‑GDSII flow, with a strong focus on Floor‑planning, Clock Tree Synthesis, Place‑n‑Route (PnR), DRC and Timing closure. This role involves architecting and implementing robust, low‑skew, power‑efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals. This role requires full‑time onsite work in San Diego, CA (5 days per week). Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Key Responsibilities: Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry‑standard tools (e.g., Innovus, ICC2). Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing, congestion, and DRC issues. Optimize design for power, performance, and area (PPA). Conduct formal equivalence checks between RTL and netlist. Support physical verification including DRC, LVS, and antenna checks. Work closely with backend teams for tapeout preparation and signoff. Excellent scripting skills (TCL, Python, Perl) for reference flow automation. Execute full‑chip and block‑level physical verification including DRC, LVS, ERC, antenna, and density checks using industry‑standard tools (e.g., Calibre, Pegasus, ICV). Customize and optimize reference physical verification flows to align with project needs and foundry requirements. Perform GDS‑to‑GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness. Debug and resolve physical verification violations, working closely with layout, design, and CAD teams. Collaborate with foundries to ensure compliance with latest design rule manuals (DRMs) and tapeout checklists. Support signoff verification, including multi‑corner/multi‑mode analysis and ECO validation. Develop and maintain automation scripts for verification flows, reporting, and regression testing. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability. Ensure timely delivery of clean GDSII for tapeout, with full verification signoff. Perform full‑chip and block‑level static timing analysis (STA) using industry‑standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners. Collaborate with RTL, synthesis, and physical design teams to ensure timing‑aware design practices. Debug and resolve setup, hold, and transition violations across various PVT corners. Drive timing closure through iterative optimization and ECO implementation. Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability. Analyze clock tree timing, including skew, latency, and jitter impacts. Support signoff timing verification, including cross‑domain timing and false/multicycle path handling. Define and implement low‑power architecture using CLP methodology across RTL and physical design stages. Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications. Customize and optimize low‑power reference flows to meet project‑specific requirements. Collaborate with RTL, synthesis, and physical design teams to integrate power‑aware features such as power gating, retention, isolation, and level shifting. Perform power‑aware static checks, simulation, and formal verification to validate power intent. Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing. Support signoff verification including power‑aware LVS/DRC, STA, and EM/IR analysis. Ensure compliance with foundry low‑power guidelines and contribute to successful tapeout. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 4+ years of experience in physical design, with a focus on clock tree design and implementation. Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design. Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime). Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies. Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis. Familiarity with low‑power design techniques, including clock gating and multi‑voltage domains. Preferred Skills: Experience with custom clock tree architectures such as H‑tree, mesh, or spine‑based topologies. Knowledge of EM/IR analysis, thermal‑aware clocking, and reliability modeling. Exposure to high‑speed interface clocking (e.g., SerDes, DDR, PCIe). Understanding of package‑level clock planning and signal integrity. Principal Duties & Responsibilities: Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system‑level requirements. Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of complex process flow from high‑level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages. Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects. Level of Responsibility: • Works independently with minimal supervision. • Provides supervision/guidance to other team members. • Decision‑making is significant in nature and affects work beyond immediate work group. • Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. • Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). • Tasks do not have defined steps; planning, problem‑solving, and prioritization must occur to complete the tasks effectively. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑************************** or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. ** Must be a U.S. citizen and eligible to receive a U.S. Government security clearance ** We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands‑on experience in RTL‑to‑GDSII flow, with a strong focus on floor‑planning, clock tree synthesis, place‑and‑route, DRC and timing closure. This role involves architecting and implementing robust, low‑skew, power‑efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals. This role requires full‑time onsite work in San Diego, CA (5 days per week). Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field. Key Responsibilities: Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry‑standard tools (e.g., Innovus, ICC2). Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing, congestion, and DRC issues. Optimize design for power, performance, and area (PPA). Conduct formal equivalence checks between RTL and netlist. Support physical verification including DRC, LVS, and antenna checks. Work closely with backend teams for tapeout preparation and signoff. Excellent scripting skills (TCL, Python, Perl) for reference flow automation. Execute full‑chip and block‑level physical verification including DRC, LVS, ERC, antenna, and density checks using industry‑standard tools (e.g., Calibre, Pegasus, ICV). Customize and optimize reference physical verification flows to align with project needs and foundry requirements. Perform GDS‑to‑GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness. Debug and resolve physical verification violations, working closely with layout, design, and CAD teams. Collaborate with foundries to ensure compliance with the latest design rule manuals (DRMs) and tapeout checklists. Support signoff verification, including multi‑corner/multi‑mode analysis and ECO validation. Develop and maintain automation scripts for verification flows, reporting, and regression testing. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability. Ensure timely delivery of clean GDSII for tapeout, with full verification signoff. Perform full‑chip and block‑level static timing analysis (STA) using industry‑standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners. Collaborate with RTL, synthesis, and physical design teams to ensure timing‑aware design practices. Debug and resolve setup, hold, and transition violations across various PVT corners. Drive timing closure through iterative optimization and ECO implementation. Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability. Analyze clock tree timing, including skew, latency, and jitter impacts. Support signoff timing verification, including cross‑domain timing and false/multicycle path handling. Interface with EDA vendors to resolve tool issues and improve flow robustness. Participate in design reviews, providing insights on timing risks and mitigation strategies. Define and implement low‑power architecture using CLP methodology across RTL and physical design stages. Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications. Customize and optimize low‑power reference flows to meet project‑specific requirements. Collaborate with RTL, synthesis, and physical design teams to integrate power‑aware features such as power gating, retention, isolation, and level shifting. Perform power‑aware static checks, simulation, and formal verification to validate power intent. Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing. Support signoff verification including power‑aware LVS/DRC, STA, and EM/IR analysis. Interface with EDA vendors to resolve tool issues and improve low‑power flow robustness. Participate in design reviews, providing insights on power architecture, risks, and mitigation strategies. Ensure compliance with foundry low‑power guidelines and contribute to successful tapeout. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 3+ years of experience in physical design, with a focus on clock tree design and implementation. Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design. Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime). Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies. Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis. Familiarity with low‑power design techniques, including clock gating and multi‑voltage domains. Preferred Skills: Experience with custom clock tree architectures such as H‑tree, mesh, or spine‑based topologies. Knowledge of EM/IR analysis, thermal‑aware clocking, and reliability modeling. Exposure to high‑speed interface clocking (e.g., SerDes, DDR, PCIe). Understanding of package‑level clock planning and signal integrity. Principal Duties & Responsibilities: Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates architectures, circuit specifications, logic designs, and/or system simulations based on system‑level requirements. Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of process flow from high‑level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package. Writes detailed technical documentation for EDA/IP/ASIC projects. Level of Responsibility: Works independently with minimal supervision. Decision‑making may affect work beyond immediate work group. Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions). Tasks require multiple steps which can be performed in various orders; some planning, problem‑solving, and prioritization must occur to complete the tasks effectively. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits $115,600.00 - $173,400.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

A leading technology corporation in San Diego seeks an experienced engineer to join the Multimedia Video Hardware Design team. The role involves implementing video codec standards and collaborating across teams to design advanced IP cores. Candidates should possess a strong background in multimedia hardware development and be proficient in Verilog/SystemVerilog. A competitive salary, bonus opportunities, and comprehensive benefits are offered. #J-18808-Ljbffr

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements. The engineer will be responsible for a variety of advanced verification tasks such as: verification environment development using modern verification techniques (System Verilog and UVM); designing verification components such as UVM agents, and behavioral models; implementing coverage and assertions using System Verilog; and developing random & directed test cases against the specification. This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing coverage results. Candidate must be a highly productive individual contributor with a demonstrated technical capability in system and sub-block level verification. Job Requirements: A Bachelor's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent 12+ year's relevant industry work experience. Experience in verifying designs at system level and block level. Fluent knowledge of RTL verification methodologies including System Verilog. Strong experience in ASIC design verification flows and DV methodologies Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills. Strong and independent design debugging capability. Strong verbal and written communication skills. Must be comfortable working in a team environment with verification team and design team members. Demonstrated ability to analyze and resolve complex verification trade-off scenarios. Must have legal authorization to work in the US The candidate should have expertise in some (or preferably all) of the following areas: Experience with hardware design and debug, C++/SystemC and other programming languages are a strong plus. Experience working with Emulators and FPGA based prototyping is a plus. Familiarity with overall chip design methodologies and tools Knowledge of CPU, DDR, Bus Protocol, Network Protocol or DSP design preferred Additional Job Description: Compensation and Benefits The annual base salary range for this position is $141,300 - $226,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements. The engineer will be responsible for a variety of advanced verification tasks such as: verification environment development using modern verification techniques (System Verilog and UVM); designing verification components such as UVM agents, and behavioral models; implementing coverage and assertions using System Verilog; and developing random & directed test cases against the specification. This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing coverage results. Candidate must be a highly productive individual contributor with a demonstrated technical capability in system and sub-block level verification. Job Requirements: * A Bachelor's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent * 12+ year's relevant industry work experience. * Experience in verifying designs at system level and block level. * Fluent knowledge of RTL verification methodologies including System Verilog. * Strong experience in ASIC design verification flows and DV methodologies * Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills. * Strong and independent design debugging capability. * Strong verbal and written communication skills. Must be comfortable working in a team environment with verification team and design team members. * Demonstrated ability to analyze and resolve complex verification trade-off scenarios. * Must have legal authorization to work in the US The candidate should have expertise in some (or preferably all) of the following areas: * Experience with hardware design and debug, C++/SystemC and other programming languages are a strong plus. * Experience working with Emulators and FPGA based prototyping is a plus. * Familiarity with overall chip design methodologies and tools * Knowledge of CPU, DDR, Bus Protocol, Network Protocol or DSP design preferred Additional Job Description: Compensation and Benefits The annual base salary range for this position is $141,300 - $226,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

**Please Note:** **1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)** **2. If you already have a Candidate Account, please Sign-In before you apply.** **:** **** Broadcom's Central Engineering Design Correlation team is looking for an energetic and self-driven professional to join our team to help with silicon technology evaluation in advanced process nodes for IP and product designs. Our mission is to assess foundry technology offerings, help define new technology platforms for IP and product designs, risk assessment, and provide Broadcom's design communities with insights into design and process-technology interactions especially during co-development in advanced process nodes. The candidate will have the opportunity to participate in new technology platform definition, PPAC (power performance area cost) assessment and benchmarking, test structure design, silicon characterization and model to silicon correlation in most advanced foundry technology nodes. The candidate will work closely with other experts in the fields of CMOS process technology, device & modeling, process and device reliability, digital & analog IP design, design sign-off flow for timing and power, CAD & EDA tools, as well as chip designers from various product lines. Primary duties will include assessment of technology offerings and capabilities to meet design needs and drive alignment with IP/product requirements. This role will involve active participation with foundry and internal teams on new technology enablement including help ensuring robustness of technology platforms. Candidate must have the ability to prioritize well, communicate clearly, deliver solutions on time, and possess excellent data analysis & foundry interaction skills. The candidate expected to work across multiple facets of projects and juggle multiple responsibilities at the same time. The position is in Broadcom's Irvine facility in California. **Responsibilities** : Candidate will support IP and Chip teams with technology evaluation including reliability and design enablement. Responsibilities as part of technology evaluation will involve test structure layout, verification, extraction, simulation, and silicon evaluation. The job scope will include a) cross-functional quality assurance of designs and tape-outs, b) EDA & RCX tool quality and predictability, and c) custom device infrastructure readiness & robustness. Candidate will engage in collaborative team projects involving design, platform technology, and operations teams and foundry partner **Qualifications** **:** Advanced degree in EE, Material Science, Physics or related field with 10+ years of industry experience after MS or 7+ years after PhD with recent work in advanced FINFET (or GAA) nodes. 1. Strong background in advanced CMOS technology (FEOL, MEOL, BEOL) including understanding of design-technology interactions 2. Proficient in interacting with design teams and foundry partner 3. Familiarity with analog and digital design flows and CAD tools 4. Hands-on experience with device/circuit level test structure designs, verification (DRC, LVS), extraction, spice simulation, silicon characterization (DC/AC/RF) and data analysis 5. Extremely detail oriented with strong analytical, communication, and multitasking skills 6. Mix of hands-on and project management skills **Additional Job Description:** **Compensation and Benefits** The annual base salary range for this position is $127,100 - $203,400 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. **Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.** **If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.** Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library (******************************* and check out our Connected by Broadcom (************************************************************************************************************************************************* series. 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Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : Broadcom's Central Engineering Design Correlation team is looking for an energetic and self-driven professional to join our team to help with silicon technology evaluation in advanced process nodes for IP and product designs. Our mission is to assess foundry technology offerings, help define new technology platforms for IP and product designs, risk assessment, and provide Broadcom's design communities with insights into design and process-technology interactions especially during co-development in advanced process nodes. The candidate will have the opportunity to participate in new technology platform definition, PPAC (power performance area cost) assessment and benchmarking, test structure design, silicon characterization and model to silicon correlation in most advanced foundry technology nodes. The candidate will work closely with other experts in the fields of CMOS process technology, device & modeling, process and device reliability, digital & analog IP design, design sign-off flow for timing and power, CAD & EDA tools, as well as chip designers from various product lines. Primary duties will include assessment of technology offerings and capabilities to meet design needs and drive alignment with IP/product requirements. This role will involve active participation with foundry and internal teams on new technology enablement including help ensuring robustness of technology platforms. Candidate must have the ability to prioritize well, communicate clearly, deliver solutions on time, and possess excellent data analysis & foundry interaction skills. The candidate expected to work across multiple facets of projects and juggle multiple responsibilities at the same time. The position is in Broadcom's Irvine facility in California. Responsibilities: Candidate will support IP and Chip teams with technology evaluation including reliability and design enablement. Responsibilities as part of technology evaluation will involve test structure layout, verification, extraction, simulation, and silicon evaluation. The job scope will include a) cross-functional quality assurance of designs and tape-outs, b) EDA & RCX tool quality and predictability, and c) custom device infrastructure readiness & robustness. Candidate will engage in collaborative team projects involving design, platform technology, and operations teams and foundry partner Qualifications: Advanced degree in EE, Material Science, Physics or related field with 10+ years of industry experience after MS or 7+ years after PhD with recent work in advanced FINFET (or GAA) nodes. 1. Strong background in advanced CMOS technology (FEOL, MEOL, BEOL) including understanding of design-technology interactions 2. Proficient in interacting with design teams and foundry partner 3. Familiarity with analog and digital design flows and CAD tools 4. Hands-on experience with device/circuit level test structure designs, verification (DRC, LVS), extraction, spice simulation, silicon characterization (DC/AC/RF) and data analysis 5. Extremely detail oriented with strong analytical, communication, and multitasking skills 6. Mix of hands-on and project management skills Additional Job Description: Compensation and Benefits The annual base salary range for this position is $127,100 - $203,400 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.