Qualification engineer job description

With our strong investment in research and development and our culture of continuous improvement, Hexcel is the industry leader in the manufacturing of advance composite materials, including carbon fiber, woven reinforcements, resins, prepregs, honeycombs and additive manufactured parts. We invite you to join the Hexcel team at various manufacturing sites, sales offices and R&T centers around the globe. Become a part of the "strength within."
Hexcel is currently seeking a Composite Qualification Engineer for our Salt Lake City, UT, USA location.

The selected individual will be responsible for but not limited to the following obligations:

Coordinating with Product Management and External Customers to define the scope of work required to qualify new or modified products to customer specifications. This requires coming to a complete understanding of customer expectations and translating them into the various technical tasks that need to be completed to finish the qualification on time. Coordinating with ISC to manufacture pre-qualification and qualification batches of material. This requires placing orders for the required quantities of materials of each type to carry out all required testing; assuring that Process Control Documents are in place and in some cases, coordinating and attending customer witnessing of manufacturing runs. Assuring that all customer expectations for testing have been communicated to the plants and that they are ready to carry out any required testing to meet specification requirements. Defining Statements of Work (SOW's) for the testing required at the plants, at other Hexcel labs, or at outside test labs. This requires assuring that the various test labs are fully capable of exactly meeting the test requirements and in cases where deviations are required, obtaining negotiated and written confirmation for any necessary changes. Coordinating the shipment of required test materials to the appropriate labs; verifying that the materials have passed any acceptance or release test requirements before using them for qualification work; assuring that the materials are preserved, protected, and stored appropriately prior to use with documented information available to prove they are acceptable for use. Writing test panel fabrication instruction paperwork for laminates, sandwich panels, or any other material forms required for testing, then supervising the manufacturing of the required test panels and assuring that post-manufacturing verification tests are acceptable for the test panels to move into testing. Reviewing testing progress and updating expected completion dates, elevating any lack of priority to management for resolution in order to complete testing on time. Reviewing test results for correctness and in some cases, statistical conformity with historical data. Making decisions as to how and when testing must be repeated, to comply with customer expectations. Maintaining complete traceability of all elements of a qualification project, then converting those elements into a complete qualification report. Interfacing with customers to provide status updates, resolution of any conflicts, and facilitating reviews of reports to achieve timely placement on the qualified products list.



Qualifications:


Bachelor's degree in Chemistry, Chemical Engineering, Material Science, Mechanical Engineering, Aerospace Engineering, or related field from a four-year college or university and one to two years related experience and/or training; or equivalent combination of education and experience. Previous knowledge of composites, fiber, honeycomb, plastics, and ceramics material properties is desirable, especially for aerospace applications. Familiar with material specifications and their applications. Working knowledge of PC's and related software, specifically MS-Word, Excel, Project, PowerPoint and statistical software. Excellent oral and written communication skills. Prior supervisory experience leading a small team or managing a work shift is preferred. Experience in project management helpful and ability to maintain a high level of attention to detail required.


Eligible candidate must be: U.S. citizen, U.S. national, a person lawfully admitted for permanent residence, a temporary resident under sections 210(a) or 245(A) of the Act, a person admitted in refugee status, a person granted asylum. Hexcel (NYSE: HXL) is a global leader in advanced composites technology, a leading producer of carbon fiber, and the world leader in honeycomb manufacturing for the commercial aerospace industry.

Hexcel is an Equal Opportunity Employer of Minorities/Females/Protected Veterans/Individuals with Disabilities/Sexual Orientation/Gender Identity. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, age, national origin, physical or mental disability, status as protected veteran, or any other protected class.

Minimum qualifications:

+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.

+ 3 years of experience working on DIMMs or other volatile/non-volatile memory solutions.

+ Experience with memory interfaces (e.g. DDR4/DDR5) and requirements to test.

+ Experience with testing requirements, best practices, algorithms, and collecting/organizing data to reproduce and explain results.

Preferred qualifications:

+ Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.

+ Knowledge of lab equipment (e.g. scopes and analyzers).

+ Knowledge of the appropriate data needed to collect to facilitate quick and accurate failure analysis from the vendor.

+ Ability to use scripting and automation to execute test algorithms and analyze results.

Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability.

With your technical expertise, you create test plans for highly complex platforms (e.g. validating the interaction of multiple pieces of equipment at the networking and subsystem levels), and using your deep knowledge of component design characteristics, you diagnose highly complex hardware or software issues.

As a Memory Test and Qualification Engineer you will qualify Dual In-Line Memory Modules (DIMMs) and memory solutions for Google's data centers.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

+ Create test plans and coordinate resources across test environments.

+ Perform electrical, functional, performance, and reliability testing for memory products and analyze results to ensure that they meet Google's requirements.

+ Report bugs and drive corrective action where needed with external suppliers, internal supply quality engineers, commodity teams, and developers.

+ Maintain and improve the qualification process.

+ Work with Original Design Manufacturers and Joint Design Manufacturers to ensure testing is up to Google standards.

Come join Intel's Design Engineering Group responsible for designing Client SoCs that make up more than half of Intel's annual revenue. We envision the future of computing and design for the next generation of laptops and desktop computers.

The DDG (Device Development Group) SOC design team is looking for an IP handoff qualification engineer who will enjoy engaging in the full spectrum of IP and SOC design development and is interested in having exposure to the entire lifecycle of SOC projects, while taking a fast-paced, empowered, hands-on engineering approach. As part of our team, you will work with IP providers and SOC customers to review and certify IP quality that prevent downstream escapes to SOC customers.

In this role, you will be responsible for ensuring a high-level IP quality for delivery to SOC involving both Intel and external IP providers. This responsibility includes understanding program and process technology requirements for IP delivery for both back end and front end domains. It also requires enforcing quality checking rules and debugging misalignments between spec and IP delivery.
An ideal candidate will:
Identify gaps in tools, flows, and methodologies and drive enhancements through various Intel wide work group engagement to improve quality within the IP, the SOC, and IntelCoordinating interactions between IP providers, the IP office team, and the various SOC design domain owners Interest and proficiency in scripting to automate and innovate for productivity improvement and enhanced capabilities is also valued Willing to understand what it takes to root cause issues by learning and understanding IP standardizations, level of quality per a given milestone, understanding IP handoff tools (Ship, Riptide, Crossfire, etc.).The candidate should have solid debugging skills and eye for finding potential issues Technical understanding of SOC or IP design development across front end and back end domains, tools/methods, or have a keen interest in growing knowledge in all such domains The ideal candidate will possess a Si design background and be interested in leveraging that technical experience to ensure smooth high quality IP delivery for SOC integration and design convergence.

The candidate should also be strong in the behavioral skillset needed to tackle the breadth of challenges that arise when operating with broad scope, high complexity, and large stakeholder networks such as:
Excellent written, verbal, and presentation communication skills with an willingness to articulate technical problems, solutions, and issues as they arise.Attention to detail with solid problem solving and organizational skills to manage multiple complex tasks, define and leverage indicator data, and proactively drive issue closure at a technical level.Motivation to take on new tasks which require continuous technical and organizational learning and to find ways to improve pain points and innovate work-models for greater productivity.Willing to work with a variety of teams across GEOs and desire to influence for results.The role has potential to expand into technical program management as skills grow in the IP handoff domain.The candidate may assist more senior program managers as they negotiate commitments, align requirements, define methodology, verify quality, and manage performance to schedule.

Qualifications:
You must possess the below qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:

Candidate must possess a Bachelor's degree in Electrical or Computer Engineering or a related field and 1+ years' experience; OR a Master's degree in Electrical or Computer Engineering or a related field and 3+ years' experience Experience in silicon development.Experience in SOC or IP development.
Preferred Qualifications:

Familiarity with Intel SOC/IP ecosystem tools and process including Carbon, HSD, PLC, IP Handoff flows and SIP/HIP handoff/integ standards.Knowledge in multiple SOC and IP design domains including Timing, Layout, Low Power (mpp/upf), DFx, Analog, Memory and associated design/verification/quality flows.Proficiency with scripting in Unix Env using Python/Perl/Shell.Previous experience and/or desire to grow program management skills.

Job Type:
Experienced Hire

Shift:
Shift 1 (United States of America)

Primary Location:
US, California, Folsom

Additional Locations:

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust
N/A

Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.