Seagate Technology jobs in Fremont, CA - 674 jobs

About our group: You will be working in the HAMR Media Recording Physics and Advanced Development group at the Seagate Recording Media Research Center in Fremont, CA, where we develop the state of art magnetic, optical and thermal, spin-stand recording characterization for recording Physics understanding and design directions for HAMR magnetic recording media to further extend data storage capacity. The team works closely with other teams in the organization such as the Sputter, testing, metrology and equipment groups, the materials science lab, and collaborators in the various Seagate organizations around the world. Together we develop the next generation of storage devices for cloud storage and other emerging applications. About the role - you will: The candidate will work under the supervision of Technical lead engineers in the Recording Physics and Advanced Development group at Seagate Recording Media R&D center to develop and improve existing magnetic characterization, spin-stand recording testing and data analytics for studying the media magnetic and thermal properties, and compare with simulations and recording data to understand recording physics of HAMR (Heat Assited Magnetic Recording) and future novel recording media. Responsibilities include: * Understand and utlize the existing magnetics characterization tools (PPMS VSM and MOKE) * Utilize existing and develop new spin-stand testing and other recording characterization techniques for HAMR media. * Capability to develop characterization or testing techniques for novel magnetic recording schemes to boost areal density. * Other responsibilities include data analysis to compare experimental measurements with modeling results to understand the underlying media design direction and recording Physics * Apply the learnings for innovative design to improve the magnetic and thermal design of HAMR media * Using data mining techniques to understand the key trends and correlations to underpin key direction for media design improvements About you: * Proven background in Magnetism and Data Analytical skills * Proficient communication * Able to work independently and as part of a team in a creative environment Your experience includes: * Proven experience and skill sets using magnetic (PPMS and MOKE) and electrical characterization techniques, experience with high field magnetic, electrical, optical and mechanical measurement equipments * Demonstrated experience and capability of developing and integrating new metrology or testing tools to perform novel characterization for magnetic materials * Robust physics background in magnetism * Hands on experience with high field magentic (PPMS and MOKE), electrical, optical, and thermal measurements tools * Familiar with optics, recording physics understanding * Proficient programming skills with Python, Labview, Visual Basics or related * Experiences with designing and integrating novel instruments * Ph.D. or MS in Physics, Applied Physics, Electrical Engineering, Applied Optics, Mechanical Engineering, or related field is preferred Location: Our Gold LEED-certified Fremont product-design campus drives innovation, bringing together a diverse set of engineering, design, operations, support, and administrative teams. The site is equipped with a state-of-the-art clean room and lab space. On-site social activities are popular, including our annual BBQ, ice cream social, and holiday events. Wellness programs, gaming rooms, and the on-site fitness center help round out and balance your Seagate work-life experience, along with opportunities to give back to our local community. The estimated base wage range for this position is $41 - $48/hr. The individual base wage is based on work location and additional factors, including job-related skills, experience, and relevant education or training. Seagate offers comprehensive benefits to its eligible Interns, including, but not limited to, medical, dental, vision, and participation in the employee stock purchase plan. Seagate also offers Interns 12 paid holidays and a minimum of 48 hours of paid sick leave. The benefits for this position are based on a 24 to 40-hour-per-week schedule for a full calendar year and may differ depending on work location and tenure with the Company. Location: Fremont USA Research Center Travel: None About Us With more than four decades of storage innovation, Seagate empowers humanity to thrive in the data age and helps people and businesses navigate the ever-expanding data landscape. We craft precision-engineered, cutting-edge solutions that help the world store and manage exponential data growth. Seagate is powered by our talented and passionate workforce of 29,000 employees across the globe who embody our core values: integrity, innovation, and inclusion. Striving towards excellence every single day, we show up with these values for our customers, business partners, shareholders, and communities alike. Join us and get inspired to make a difference in the datasphere! Seagate is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, race, color, ancestry, national origin, citizenship status, physical or mental disability, genetic information, marital status, sex (which includes pregnancy, childbirth, breastfeeding, or related medical conditions), gender, gender identity, gender expression, sexual orientation, religion, military and veteran status, or other status protected by applicable law. We will consider for employment qualified applicants with arrest and conviction records. EEO Know Your Rights Poster Seagate will provide reasonable accommodation with the application process upon request as required to comply with applicable laws. If you need assistance or accommodation due to a disability, you may contact us at accommodations@seagate.com. All Seagate jobs will remain open for a minimum of seven days. For information on how Seagate collects and uses your personal information during the application process, please review the Applicant Privacy Statement.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are seeking an engineer with strong hands‑on experience in FPGA build flows, design qualification, and developing infrastructure for platform regressions. This role is focused on developing robust smoke tests, functional test cases, and qualification workloads used to validate both FPGA designs and the associated platform software/toolchain flows. THE PERSON: The successful candidate will architect and implement daily and nightly regression pipelines, integrate them into a unified infrastructure, and ensure continuous quality and reliability of FPGA based platform design flows at scale. This role sits at the intersection of FPGA engineering, software automation, and infrastructure‑level validation. KEY RESPONSIBILITIES: FPGA Design & Build Flow Own FPGA compile/build flows (synthesis, place & route, timing closure, bitstream generation). Develop and maintain reference FPGA designs for build flow validation. Diagnose issues across RTL, constraints, tools, and platform dependencies. Platform Qualification & Toolchain Validation Develop targeted test cases for FPGA build flows, toolchain stability, and edge cases. Build scripts and automation for software stack validation (drivers, runtimes, APIs). Validate tool and environment changes, partner with vendors and internal teams on root cause and fixes. Define scalable design qualification criteria and coverage. Regression Infrastructure Design and maintain automated daily/nightly regression systems for FPGA and software toolchain validation. Enable distributed, scalable runs across on‑prem or cloud resources. Automate result collection, triage, and failure classification. Infrastructure & CI/CD Integration Integrate FPGA regressions into the unified infrastructure and CI/CD pipelines. Interface with shared services (e.g., build orchestration, monitoring, logging). Enable standardized reporting, dashboards, and notifications for regression health. PREFERRED EXPERIENCE: Large-scale FPGA farm or datacenter‑style validation. Monitoring/logging tools (e.g., Grafana, Prometheus, ELK). Operating unified build/validation infrastructures across multiple teams. Hardware bring‑up or silicon pre‑/post‑silicon validation. Cross‑functional and geographically distributed team collaboration. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA This role is not eligible for Visa sponsorship Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE: Be part of AMD's analog/mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDR5, DDR5, gDDR6, HBM2/HBM3, chip‑to‑chip,…) and chip‑to‑chip Gbps proprietary PHY IP solutions. Responsibilities include THE PERSON: The ideal candidate has experience leading others in technical settings. You also have excellent communication, writing, and presentation skills. KEY RESPONSIBLITIES: Definition, review and sign‑off on IP top level and component level specifications AMS components circuit and layout design Supervise pre‑silicon layout, post‑silicon characterization and debug. Support product bring‑up and debug, and Sign‑off on test‑plans and characterization reports. Interface with SOC teams, system HW/SW teams, and global manufacturing teams. PREFERRED EXPERIENCE: Experience in high speed serial and/or parallel mixed signal PHY/IO designs Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking. Hand‑on design experience in multi‑Gbps serial (PCIe, USB, …), parallel high BW memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3, gDDR5/gDDR6, …) and chip‑to‑chip links PHY IPs such as UCIe. Experience in mixed signal design circuit blocks such as digital/analog DLLs, duty cycle corrector, clock and data recovery, clock mixer, … Experience in low power design techniques for high speed/custom digital circuit (e.g. CMOS/CML high speed design for counters, dividers, …) design and analysis including transistor level timing sign‑off Solid understanding of power, area and performance trade‑offs in mixed signal IP design Design Experience in FinFET advanced CMOS process nodes 7nm and below coupled with a solid understanding of transistor device performance and fundamentals Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools Work with project‑manager, system architects, IC designers and physical designers to guarantee quality/timely deliverables meeting project's schedule and technical requirements Track record of successfully taking designs to production Excellent written and verbal communication skills able to operate without direct supervision but also work cross‑functionally, cross‑geographies collaborating and being part of a multi‑disciplinary team in a dynamic/fast paced environment. Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge ACADEMIC CREDENTIALS: BS, MS or PhD in Electrical Engineering, Computer Engineering or related equivalent LOCATION: San Jose, California This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available. This posting is for an existing vacancy. #J-18808-Ljbffr

A global technology leader is seeking an experienced product marketing professional in Santa Clara, California. This role requires over 15 years of experience in product marketing, a strategic mindset, and a deep understanding of market trends. Responsibilities include leading marketing initiatives for diverse products and collaborating with various internal teams to enhance market presence. The position offers competitive compensation and opportunities for career growth. #J-18808-Ljbffr

A leading technology company is seeking a Principal / Senior GPU Software Performance Engineer in San Jose, CA. This role involves optimizing GPU workloads for training performance, enhancing throughput, and resolving bottlenecks in distributed systems. The ideal candidate will have strong skills in GPU performance engineering and experience with deep learning frameworks, particularly PyTorch. This position offers a chance to work in a collaborative environment focused on innovation and inclusivity. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. The Role This role is an exciting opportunity in SBIO team to create FPGA hardware validation platforms and debugging complex issues involving both hardware and software. Collaborate with design and firmware teams to define validation plans and execute on FPGA prototyping platforms. This role requires a proven track record of successfully bringing complex FPGA designs from concept through production quality, with strong debugging and problem-solving capabilities. The Person Strong analytical and problem solving skills with a pronounced attention to detail Strong communication, mentoring and leadership skills Self-driven, Methodical and attention to detail in troubleshooting and problem-solving Can work well with cross functional teams Excellent verbal and written communication skills Responsibility Design, develop, and implement complex FPGA architectures using Xilinx devices (UltraScale, UltraScale+, Versal, etc.) Create RTL designs using Verilog/SystemVerilog for high-performance applications Perform FPGA prototype design, implementation, and bring‑up activities Create comprehensive design documentation, specifications, and technical reports Perform timing analysis, closure, and optimization using Vivado tools Conduct board-level bring‑up and system integration testing Debug complex hardware/firmware issues using logic analyzers, oscilloscopes, and other test equipment Validate FPGA designs against specifications and performance requirements Independently troubleshoot and resolve challenging technical issues Work closely with hardware, software, and systems engineering teams Participate in design reviews and technical discussions Communicate project status, risks, and technical challenges to stakeholders Preferred Skill Set & Experience Extensive experience in field of FPGA hardware prototyping Have worked with prototyping platforms such as Xilinx reference boards, Synopsys HAPS platforms etc Experience with Xilinx Versal ACAP or UltraScale+ devices Knowledge of FPGA synthesis tools and methodologies Familiarity with Python/TCL scripting for design automation Knowledge of FPGA-based system architecture and hardware/software co‑design Familiarity with board design and hardware debugging tools (logic analyzers, oscilloscopes, protocol analyzers) Fluent in System Verilog and a familiarity with simulation and debug Familiarity with industry standard high-speed protocols such as USB and PCIE is a plus EDUCATION BS (or higher) degree in Electrical or Computer Engineering desired LOCATION Santa Clara, CA This role is not eligible for visa sponsorship. #LI‑SC3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career. THE ROLE: This Senior Manager role is a high-visibility position within AMD's Finance organization located in Austin, TX.This role is critical to the success of the business and reports directly to Senior Director, Compute & Enterprise AI Business Unit Finance. The role will be supporting the Enterprise AI and HPC group. Key responsibilities include partnering with the business to ensure performance obligations and strategic deals while maximizing return on investment. This role will perform strategic financial analyses and provide necessary guidance (accounting and economic feasibility) and executive reporting (e.g., pricing, strategic deal financials, product business case / P&L etc.) to influence business decisions. The role will work cross-functionally with BU, finance counterparts, technical accounting, and legal. THE PERSON: The ideal candidate should have a bias for action, high sense of teamwork, and ability to speak up and make recommendations in a fast-moving environment. Additionally, we are looking for a teammate with leadership experience that will take ownership of the role, drive process improvements, and implement standardized work. Role requires someone with capability to grow within the position and in the future, rotate to Finance leadership positions within the Company. KEY RESPONSIBILITIES: Serve as the Finance lead for AMD's Enterprise AI and HPC business unit Directly support the business unit General Manager and leadership team Engage/Lead core finance processes including Long-range planning, Annual Operating Plans, and intra-quarter Outlooks Perform financial analysis and provide decision analysis support for customer programs and special projects Coordinate with and provide operational finance guidance to various organizations and individuals across cross-functional teams such as Corporate Financial Planning, Accounting, Sales & Regional Finance, and Business Unit Operations Prepare and disseminate timely and accurate financial information to allow the business to plan, forecast, and make decisions using controlled and consistent data Take full ownership of and accountability for on-going reports providing validation and supporting documentation to business partners as required Perform scenario analysis & planning to be used for decision making and approvals (e.g. pricing deals, revenue & gross margin analysis etc.). Identify potential opportunities for process improvement to existing processes and cadence Assist in providing value-added management decision support, driving key business goals, identify major trends and corresponding business issues PREFERRED EXPERIENCE: Self-starter with excellent interpersonal communication, teaming, and problem-solving skills Demonstrated financial leadership effectively supporting Sales and/or Business leaders in a high-growth environment Preferred experience in a global fast-paced competitive multi-site high-tech environment Must be able to thrive in a fast-paced dynamic environment Robust analytical skills required and the ability to turn complex data and concepts into valuable information to present in a simple/understandable manner Eager to learn and adapt to new things in the fast paced and high-pressured environment Enthusiastic, proactive, and dynamic individual with ability to work in teams and with all levels of an organization as well as work independently Proficiency in Excel, AI tools, MSFT Co-Pilot, and ERP systems experience (SAP, SAP HANA) ACADEMIC CREDENTIALS: Bachelor's degree in finance, accounting or equivalent MBA preferred LOCATION: Santa Clara, CA This role is not eligible for visa sponsorship. #LI-SD1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading technology company located in San Jose is seeking an engineer specialized in FPGA build flows and software automation. The candidate will own FPGA compile/build processes, develop robust regression pipelines, and ensure quality throughout the design and validation phases. An ideal candidate will possess strong experience in toolchain validation and collaboration across teams. This position offers an innovative environment focused on advancing technology and collaboration within a diverse team. #J-18808-Ljbffr

About our group: We are seeking a motivated and detail-oriented Intern to join our Global Identity and Access Management (IAM) team. This is an excellent opportunity to gain hands-on experience with enterprise-level IAM technologies and learn how global IT teams collaborate across regions to secure a global manufacturing organization. You will contribute to real-world projects that enhance security, compliance, and identity governance, while understanding why identity systems are critical to protecting intellectual property and operational continuity. About the role - you will: * Assist in the administration and maintenance of On-Premises Active Directory (AD) and LDAP environments. * Support the configuration and monitoring of Azure Entra ID (formerly Azure Active Directory) and related identity services. * Participate in Multifactor Authentication (MFA) implementation and monitoring to strengthen security posture. * Explore and learn Office 365 services, including email systems and email security features, to understand their role in identity and access management. * Contribute to Public Key Infrastructure (PKI) operations, including certificate lifecycle management. * Help troubleshoot and resolve IAM-related incidents and service requests. * Document processes, configurations, and troubleshooting steps. * Collaborate with senior engineers and global IT teams to implement IAM best practices and automation. * Support access reviews, audit preparation, and compliance reporting. What you will gain: * Practical experience with Azure Entra ID, On-Prem Active Directory, Multifactor Authentication technologies, and Office 365 services including email security. * Exposure to global IT operations and how teams across different regions collaborate to deliver secure identity solutions. * Insight into why identity systems are foundational to security in a global manufacturing company. * Mentorship from experienced IAM professionals and the opportunity to contribute to impactful projects. About you: * Excellent analytical and problem-solving skills. * Good communication and teamwork abilities. * Eagerness to learn and adapt in a fast-paced environment. Your experience includes: * Basic understanding of identity management concepts and directory services. * Familiarity with Windows Server, PowerShell scripting, or cloud platforms is a plus. * Currently pursuing a Bachelor's or Master's degree in Computer Science, Information Security, or a related field and returning to classes in Fall 2026. Location: Our Gold LEED-certified Fremont product-design campus drives innovation, bringing together a diverse set of engineering, design, operations, support, and administrative teams. The site is equipped with a state-of-the-art clean room and lab space. On-site social activities are popular, including our annual BBQ, ice cream social, and holiday events. Wellness programs, gaming rooms, and the on-site fitness center help round out and balance your Seagate work-life experience, along with opportunities to give back to our local community. The estimated base wage range for this position is $29 - $41/hr. The individual base wage is based on work location and additional factors, including job-related skills, experience, and relevant education or training. Seagate offers comprehensive benefits to its eligible Interns, including, but not limited to, medical, dental, vision, and participation in the employee stock purchase plan. Seagate also offers Interns 12 paid holidays and a minimum of 48 hours of paid sick leave. The benefits for this position are based on a 24 to 40-hour-per-week schedule for a full calendar year and may differ depending on work location and tenure with the Company. Location: Fremont USA Research Center Travel: None About Us With more than four decades of storage innovation, Seagate empowers humanity to thrive in the data age and helps people and businesses navigate the ever-expanding data landscape. We craft precision-engineered, cutting-edge solutions that help the world store and manage exponential data growth. Seagate is powered by our talented and passionate workforce of 29,000 employees across the globe who embody our core values: integrity, innovation, and inclusion. Striving towards excellence every single day, we show up with these values for our customers, business partners, shareholders, and communities alike. Join us and get inspired to make a difference in the datasphere! Seagate is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, race, color, ancestry, national origin, citizenship status, physical or mental disability, genetic information, marital status, sex (which includes pregnancy, childbirth, breastfeeding, or related medical conditions), gender, gender identity, gender expression, sexual orientation, religion, military and veteran status, or other status protected by applicable law. We will consider for employment qualified applicants with arrest and conviction records. EEO Know Your Rights Poster Seagate will provide reasonable accommodation with the application process upon request as required to comply with applicable laws. If you need assistance or accommodation due to a disability, you may contact us at accommodations@seagate.com. All Seagate jobs will remain open for a minimum of seven days. For information on how Seagate collects and uses your personal information during the application process, please review the Applicant Privacy Statement.

A leading semiconductor company in California is looking for a Senior Silicon Design Verification Engineer to innovate in the verification of high-speed Crypto and Network-on-Chip designs. You will lead a team, develop verification strategies, and collaborate with cross-functional engineering teams. The ideal candidate has a strong leadership background, is proficient in UVM and System Verilog, and has a passion for fostering a collaborative environment. The role requires a relevant degree and strong communication skills. Competitive benefits are included. #J-18808-Ljbffr

A leading technology firm in San Jose is seeking a Physical Design Engineer to work on advanced ASIC products. Responsibilities include the design layout implementation of power grids and interconnects, alongside DRC and electrical checks. The ideal candidate has strong scripting skills and extensive experience in electrical engineering. This role offers a competitive salary range of $120,000 - $192,000 with a comprehensive benefits package including 401(K) matching. #J-18808-Ljbffr

Software Principal Engineer The Software Engineering team delivers next-generation application enhancements and new products for a changing world. Working at the cutting edge, we design and develop software for platforms, peripherals, applications and diagnostics - all with the most advanced technologies, tools, software engineering methodologies and the collaboration of internal and external partners. Join us to do the best work of your career and make a profound social impact as a Software Principal Engineer on our Software Engineering Team in Santa Clara, California. (Local Candidates Only) As a Software Principal Engineer, you will be responsible for developing sophisticated systems and software based on the customer's business goals, needs and general business environment creating software solutions. Design, develop, and maintain different components of a Data Protection storage appliance Debug and resolve complex software, hardware, and network issues in production environments Take part in the full software development life cycle, including development, test, continuous delivery, and support Be an active member of an agile team, collaboratively realizing features through development, test, and delivery 8+ years of experience in all phases of software development: feasibility, design, implementation, integration, test, delivery, and automation ~ Strong Linux/Distributed system knowledge and hands-on experience, with experience in designing and implementing complex systems ~ Proficient programming and debugging skills in C/C++ or Go, along with knowledge of version control (Git) and bug tracking systems (JIRA) ~ Experience in developing software for storage appliances Strong problem solving, troubleshooting, diagnostic skills with knowledge of performance analysis tools and techniques for multi-threaded distributed systems If you're looking for an opportunity to grow your career with some of the best minds and most advanced tech in the industry, we're looking for you. Dell Technologies is a unique family of businesses that helps individuals and organizations transform how they work, live and play. Read the full Equal Employment Opportunity Policy here .

Senior Principal Software Engineer The Software Engineering team delivers next-generation software application enhancements and new products for a changing world. Working at the cutting edge, we design and develop software for platforms, peripherals, applications and diagnostics - all with the most advanced technologies, tools, software engineering methodologies and the collaboration of internal and external partners. Join us to do the best work of your career and make a profound social impact as a Senior Principal Software Engineer on our Software Engineering Team in Santa Clara, California . (Local Candidates Only) What you'll achieve As a Senior Principal Software Engineer, Distributed Systems you will be responsible for building world-class storage appliances You will: Lead the end-to-end software development lifecycle, including feasibility evaluation, architecture design, implementation, integration, testing and delivery Architect and implement complex storage subsystems for distributed environments Collaborate with cross-functional teams to ensure robust, high-quality solutions Take the first step towards your dream career Every Dell Technologies team member brings something unique to the table. Here's what we are looking for with this role: Essential Requirements 12+ years of experience across all phases of software development, with proven technical leadership Strong proficiency in C/C++/Go with deep expertise in Linux and distributed system programming Expert-level knowledge of Linux, distributed systems, and storage technologies, including experience with complex system design and implementation Skilled in Kubernetes for container orchestration, and familiarity with tools like Git (version control) and JIRA (issue tracking) Exceptional design, debugging, and problem-solving skills, with advanced knowledge of performance evaluation for multi-threaded distributed systems Desirable Requirements Degree in Computer Engineering or related field Compensation Dell is committed to fair and equitable compensation practices. The salary range for this position is $239,700 - $310,200. Who we are We believe that each of us has the power to make an impact. That's why we put our team members at the center of everything we do. If you're looking for an opportunity to grow your career with some of the best minds and most advanced tech in the industry, we're looking for you. Dell Technologies is a unique family of businesses that helps individuals and organizations transform how they work, live and play. Join us to build a future that works for everyone because Progress Takes All of Us. Dell Technologies is committed to the principle of equal employment opportunity for all employees and to providing employees with a work environment free of discrimination and harassment. Read the full Equal Employment Opportunity Policy here . Job ID: R282875

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD/Xilinx programmable devices. THE PERSON: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware and firmware engineers to understand the new features to be verified Take ownership of block level verification tasks Define test plans, test benches, and tests using System Verilog and UVM Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes Review functional and code coverage metrics to meet the coverage requirements Develop and improve existing verification flows and environments PREFERRED EXPERIENCE: Strong understanding of computer architecture and logic design Knowledge of Verilog, system Verilog and UVM is a must Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification Working knowledge of C/C++ and Assembly programming languages Exposure to scripting (python preferred) for post-processing and automation Experience with gate level simulation, power and reset verification ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

The Software Engineering team delivers next-generation application enhancements and new products for a changing world. Working at the cutting edge, we design and develop software for platforms, peripherals, applications and diagnostics - all with the most advanced technologies, tools, software engineering methodologies and the collaboration of internal and external partners. Join us to do the best work of your career and make a profound social impact as a Principal Software Development Build Engineer in Santa Clara, California . What you'll achieve As a Principal Software Development Build Engineer, you will own and evolve CI/CD pipelines, build automation and release processes for our scale-out storage and data protection platform. You'll drive modernization of build systems, ensure fast/reliable releases and mentor junior engineers while collaborating closely with development, QA and operations. You will: Architect and optimize build/release pipelines for complex, distributed software Lead improvements in CI/CD workflows, automation, and developer productivity Troubleshoot build failures and enforce branching, versioning, and governance standards Integrate test automation and security checks into pipelines Mentor engineers and drive adoption of modern build tools and practices Take the first step towards your dream career Every Dell Technologies team member brings something unique to the table. Here's what we are looking for with this role: Essential Requirements 8+ years experience in build/release engineering or DevOps (or equivalent skill) Expertise with CI/CD platforms e.g. Jenkins, GitLab CI, GitHub Actions Proficiency in Python, Bash or Groovy for automation Experience with Git-based SCM, artifact management (Artifactory/Nexus), and containerized builds (Docker/K8s) Desirable Skills: Bachelor's or Master's degree in Computer Science, Engineering or related field Knowledge of modern build systems e.g. Bazel, CMake and cloud CI/CD Compensation Dell is committed to fair and equitable compensation practices. The base salary range for this position is $205,700-$266,200 . Benefits and Perks of working at Dell Technologies Your life. Your health. Supported by your benefits. You can explore the overall benefits experience that awaits you as a Dell Technologies team member - right now at MyWellatDell.com Who we are We believe that each of us has the power to make an impact. That's why we put our team members at the center of everything we do. If you're looking for an opportunity to grow your career with some of the best minds and most advanced tech in the industry, we're looking for you. Dell Technologies is a unique family of businesses that helps individuals and organizations transform how they work, live and play. Join us to build a future that works for everyone because Progress Takes All of Us. Dell Technologies is committed to the principle of equal employment opportunity for all employees and to providing employees with a work environment free of discrimination and harassment. Read the full Equal Employment Opportunity Policy here . Job ID: R283658

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE We are seeking a Senior Finance Manager to join the Adaptive and Embedded Computing Group (AECG) finance team, reporting to the Director of AECG finance. The candidate will be a key finance partner to the AECG General Manager, providing critical support in budgeting, planning, and consolidation activities specifically focused on OpEx and CapEx. In this position, you will work closely with the AECG BU senior leadership team and other stakeholders to provide valuable financial insights and guidance. THE PERSON The ideal candidate should be an experienced finance leader, have a bias for action, high sense of teamwork, and ability to speak up and make recommendations in a fast‑moving environment. This individual coaches and develops teams, embraces continuous improvement, and approaches challenges with a proactive mindset. KEY RESPONSIBILITIES Partner with senior leadership team to lead development of Annual Operating Plan and long‑term financial plan, including operating expense, headcount, and capital expenditures. Drive discussions on financial targets, resource allocation and perform scenario analysis to facilitate the decision‑making process. Lead and manage a team of financial analysts, overseeing budgeting and analysis activities while providing ongoing coaching and mentorship to ensure high performance and growth. Work closely with business unit leaders on monthly and quarterly forecast updates. Serve as a trusted finance partner to help business partners deliver financial targets. Drive monthly NRE (Non‑Recurring Engineering) program level updates, with a solid understanding of NRE accounting; gather inputs from program managers and track changes across versions. Prepare and disseminate timely and accurate financial information to allow the business to plan, forecast, and make decisions using controlled and consistent data. Continuously evaluate and enhance financial processes, tools, and methodologies to streamline budgeting, planning, and consolidation activities. Provide value‑added management decision support, driving key business goals, identify major trends and corresponding business issues. PERFERRED EXPERIENCE Progressive experience in financial analysis, budgeting, and planning, ideally within the semiconductor or related technology sector Deep expertise in OpEx/CapEx management, accounting standards, and financial reporting Prior experience managing and developing a team of financial analysts Advanced skills in financial modeling, forecasting, and ERP tools (SAP/SAC) Demonstrated financial leadership supporting business and engineering teams Strong analytical ability to interpret complex data, identify trends and communicate insights. Excellent interpersonal and communication skills; effective collaborator and influencer across functions. Proven self‑starter who thrives in fast‑paced, dynamic environments and manages multiple priorities independently. Eager, proactive learner with a positive team‑oriented approach. ACADEMIC CREDENTIALS Bachelor's degree in finance, accounting or equivalent MBA or CPA preferred This role is not eligible for visa sponsorship. #LI‑SD1 #LI‑Hybrid Benefits offered are described. AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

About our group: We are the backbone of Seagate's media development and technology integration efforts, specializing in sputter deposition coating systems. Our team ensures equipment reliability, performance validation, and process optimization for breakthrough storage technologies. Collaborating globally, we deliver solutions that enable the future of data management. We are currently recruiting to fill multiple roles based out of our Fremont office. About the role - you will: * Lead vacuum system maintenance and troubleshooting for advanced sputter deposition equipment. * Manage reconfiguration projects, preventive maintenance schedules, and system readiness for R&D. * Collaborate with engineers, technologists, and operators to resolve complex technical issues. * Ensure compliance with cleanroom protocols and safety standards. * Drive continuous improvement in equipment performance and reliability. About you: * Safety-First Mindset - You consistently prioritize safety in all operations and decision-making, ensuring compliance with protocols and fostering a secure work environment. * Collaborative Problem Solver - You work effectively across cross-functional teams, demonstrating strong communication skills and a proactive approach to resolving technical challenges. * Adaptability and Continuous Learning - You thrive in a dynamic R&D environment, quickly adapting to changing priorities and embracing new technologies and processes to drive innovation. Your experience includes: * Vacuum Technology Expertise: High/Ultra-high vacuum principles, leak detection, gas flow dynamics. * Pump Systems: Rotary vane, scroll, turbomolecular, cryogenic pumps. * Instrumentation: Pirani, cold cathode, ion gauges; calibration and interpretation. * Leak Detection: Helium leak testing and troubleshooting. * Electrical & Control Systems: Power supply troubleshooting, PLC interface understanding. * Preventive Maintenance: Scheduling, documentation, and performance reporting. * Able to work 11.5-hour shifts * Able to travel locally occasionally You might also have: * Experience with sputter deposition systems. * Familiarity with automation and transport systems troubleshooting. Location: Our Gold LEED-certified Fremont product-design campus drives innovation, bringing together a diverse set of engineering, design, operations, support and administrative teams. The site is equipped with state-of-the-art clean room and lab space. On-site social activities are popular, including our annual BBQ, ice cream social, and holiday events. Wellness programs, gaming rooms and the on-site fitness center help round out and balance your Seagate work-life experience, along with opportunities to give back to our local community. The estimated base wage range for this position is $31.00 - $45.00/hr. The individual base wage is based on work location and additional factors, including job-related skills, experience, and relevant education or training. Seagate offers comprehensive benefits to its eligible employees, including, but not limited to, medical, dental, vision, and life insurance, short- and long-term disability, eligibility to participate in discretionary bonus program, 401(k), employee stock purchase plan, flexible and dependent care spending accounts, and health care spending accounts. Seagate also offers paid time off, including 12 holidays, 120 hours of vacation, a minimum of 48 hours of paid sick leave, and 16 weeks of paid parental leave. The benefits for this position are based on a full-time schedule for a full calendar year and may differ depending on work location and tenure with the Company. Location: Fremont USA Research Center Travel: Up to 10% About Us With more than four decades of storage innovation, Seagate empowers humanity to thrive in the data age and helps people and businesses navigate the ever-expanding data landscape. We craft precision-engineered, cutting-edge solutions that help the world store and manage exponential data growth. Seagate is powered by our talented and passionate workforce of 29,000 employees across the globe who embody our core values: integrity, innovation, and inclusion. Striving towards excellence every single day, we show up with these values for our customers, business partners, shareholders, and communities alike. Join us and get inspired to make a difference in the datasphere! Seagate is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, race, color, ancestry, national origin, citizenship status, physical or mental disability, genetic information, marital status, sex (which includes pregnancy, childbirth, breastfeeding, or related medical conditions), gender, gender identity, gender expression, sexual orientation, religion, military and veteran status, or other status protected by applicable law. We will consider for employment qualified applicants with arrest and conviction records. EEO Know Your Rights Poster Seagate will provide reasonable accommodation with the application process upon request as required to comply with applicable laws. If you need assistance or accommodation due to a disability, you may contact us at accommodations@seagate.com. All Seagate jobs will remain open for a minimum of seven days. For information on how Seagate collects and uses your personal information during the application process, please review the Applicant Privacy Statement.

A leading technology company seeks an Analog/Mixed Signal Verilog Modeling Design Engineer to develop models for various analog IPs and work closely with design teams. Candidates must have at least 8 years of experience, proficiency in SystemVerilog, and knowledge of analog circuits. This role offers a competitive salary and a comprehensive benefits package, promoting an inclusive work environment. #J-18808-Ljbffr

A leading technology company in San Jose is seeking an experienced engineer to join their analog/mixed signal IP design team. This role involves designing next generation I/O interfaces, with a strong emphasis on mixed signal design and leading technical projects. The ideal candidate will possess a degree in Electrical Engineering and have hands-on experience with high speed designs and communication tools. This position offers competitive benefits and is not eligible for visa sponsorship. #J-18808-Ljbffr