Senior verification engineer job description

Blackstone Talent Group, an award-winning technology consulting and talent agency is seeking a Senior Digital ASIC/FPGA Verification Engineer to join our team at our client’s site in El Segundo, CA.
Responsibilities

Title: Senior Digital ASIC/FPGA Verification Engineer Utilize high-level architectural documentation along with algorithm descriptions to create self-checking and reusable test benches from scratch Develop Functional Coverage Models and Closing Code Coverage Utilize UVM to create drivers, monitors, predictors, and scoreboards


Required Qualifications

Minimum of 15 years experience in Digital ASIC verification with at least 5 years focused on UVM Experience with ASIC development including architectural definition, and detailed design implementation and functional verification using SystemVerilog Experience with design architecture and detailed specification generation


Preferred Skills

Experience with hardware emulators (Palladium) Proficiency with hardware verification languages: System Verilog, System Verilog Assertions Ability to executable test plans Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc. Experience developing Functional Coverage Models and Closing Code Coverage Proficient in scripting languages: Make, Perl, Python, etc. Revision Control Systems: svn, cvs, git Proficient in Linux Environments Demonstrated history of 1st pass success with ASIC designs. Functional Safety methodology and tools


EDUCATION

All candidates MUST hold a Bachelor' s degree (or higher) in Engineering.

Hybrid (must be local to the area), meaning we only anticipate remote work at this time, but if there’s an issue that requires on-site support, e.g. working with hardware, we’ll need the contractor to come in to support that.

Blackstone Talent Group is a division of Blackstone Technology Group, a global IT services and solutions firm that implements technological solutions across commercial industry verticals and the US Federal Government. Blackstone’s global talent augmentation practice was founded in 1998. Blackstone Talent Group has offices in San Francisco, Denver, Houston, Colorado Springs, and Washington, DC. We specialize in providing clients the best talent across a variety of industries and sectors.


EOE of Minorities/Females/Veterans/Disabilities

Senior Digital Verification Engineer
What You Will Do:
At Allegro Microsystems we architect, design and deploy advanced technology mixed signal power devices. We currently have an opening for senior level digital verification design engineer to join our expanding team in Milan (Italy), Manchester, NH (US), Buenos Aires, Argentina (S.America), and Edinburgh, Scotland (UK). This opportunity will allow an individual to contribute within the framework of a broader experienced analog, mixed-signal and digital team. We are looking for a motivated candidate that can leverage the group's experience to begin quickly contributing to the success of the team.
The primary focus for the individual will be using cutting edge tools to verify state of the art products in Allegro's Model Based Design flow for digital signal processing applications. Knowledge of Universal Verification Methodology, SystemVerilog assertions and Cadence verification tools is the key knowhow. As a member of product development team, you will also be exposed to variety of tools including MathWorks Simulink, embedded microprocessor coding, MATLAB scripting and Jama Requirements Management.
Typical tasks for a sr. Digital Design Verification engineer include:
· Preparation of digital design test plan from requirements using Cadence-vManager/vPlanner
· Definition and creation of UVM-SV test environment, test plans, tests and functional coverage
· Verification of signal processing and control algorithms using Cadence and MathWorks tools
· Analysis of test results, improving test coverage and debug of unexpected design behavior
· Running and maintenance of regression runs
· Preparation and/or leading of verification reviews
· Modification and/or debug of Simulink models in mixed signal test environment
· Coordination of verification activities with abroad team members
· Cooperation with System Engineering team on Jama Requirements

Education and Experience Requirements
The successful candidate will possess a Bachelor's / Master's degree of 5+ / 3+ years of experience in Digital Design and/or Verification. Excellent communication, documentation, problem-solving and analytical skills are required. Knowledge of SystemVerilog and UVM is a must. Experience with the usage of Jama, MATLAB/Simulink, Python is a strong plus.

Job DescriptionSenior Digital Verification Engineer If you are a Senior Digital Verification Engineer with experience, please read on!

Based in the Boston or Rochester area, we are a leading provider of biometric identification technologies offering simple, secure and personal authentication. We help people make payments, prove their identity, gain access to information or unlock devices.What You Will Be DoingYou will work closely with colleagues in the silicon organization as well as with the R&D, system engineering, software engineering, and sensor development teams to deliver high-volume products based on cutting-edge sensor technologies into the smart card, mobile, and IoT markets.

- Lead the architecture development of verification environment; interpret requirements, analyze potential solutions, debug and document results.

- Writing scripts, test benches, and tests; documenting flows, procedures, and results of the verification methodology.

- Perform design verification with SystemVerilog and UVM, potentially from both a sub-block level and top level.

- Provide or develop a vision for verification that incorporates early software development and readily translates to the silicon validation phase.

- Apply creative approaches to achieving functional coverage and ensuring overall design quality. Recommend and evaluate EDA tools that support such processes.

- Create abstract simulation models for analog and/or sensor components as necessary to improve the fidelity of the digital test bench.

- Verify/certify licensed IP as appropriate.What You Need for this Position- BS / MS in Electrical or Computer Engineering, or related field.
- At least 2 years experience in design, development, and/or verification of digital ASICs.
- Experience in writing Verilog and System Verilog, within a UVM-based environment
- Knowledgeable of the multiple microcontroller core architectures.
- Knowledge of Encryption/Decryption and Hash algorithms and of various serial port communication interfaces such as SPI, UART, and I2C.What's In It for You- Competitive Base Salary ($100k - $200k DOE)
- Vacation/PTO
- Medical
- Dental
- Vision
- 401k Benefits- Vacation/PTO
- Medical
- Dental
- Vision
- 401k So, if you are a Senior Digital Verification Engineer with experience, please apply today! -
Applicants must be authorized to work in the U.S.



CyberCoders, Inc is proud to be an Equal Opportunity Employer


All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.


Your Right to Work
– In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification document form upon hire.