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Top 50 Senior Verification Engineer Skills

Below we've compiled a list of the most important skills for a Senior Verification Engineer. We ranked the top skills based on the percentage of Senior Verification Engineer resumes they appeared on. For example, 13.2% of Senior Verification Engineer resumes contained Test Cases as a skill. Let's find out what skills a Senior Verification Engineer actually needs in order to be successful in the workplace.

These are the most important skills for a Senior Verification Engineer:

1. Test Cases

demand arrow
high Demand
Here's how Test Cases is used in Senior Verification Engineer jobs:
  • Developed and implemented test cases, system level test plans, and integration for both internal and external customers.
  • Designed and executed complete test plans, test cases and scripts, scheduled and assigned team roles.
  • Developed Test Plan, Test scope, Test cases, Test effort estimation and customer escalation handling.
  • Created BFM, checkers and test cases to debug the root cause of simulation failures.
  • Reported on ambiguous and superfluous requirements, gaps of testing after developed test cases.
  • Executed Manual test cases for smoke, functional, system, and regression testing.
  • Develop Test cases and Test procedures using per the DO-178B (Level B).
  • Test cases developed are now used at various Intel locations around the world.
  • Created Test Design and Test Cases for features without Requirement Specification.
  • Design and execute test cases for validation of software tools.
  • Created test cases, phases, and defects in TestDirector.
  • Created test plan and developed all test cases.
  • Document test plan and test cases.
  • Update Test cases and Test Procedures.
  • Developed regression, progression and Assura Dracula compatibility test cases for all products.
  • Created test cases to test reactor protection system for Hainan nuclear power plant.

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2. Functional Coverage Model

demand arrow
high Demand
Here's how Functional Coverage Model is used in Senior Verification Engineer jobs:
  • Developed functional coverage model from Hub Matrix feature list for Hub Verification.

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1 Functional Coverage Model Jobs

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3. Verilog

demand arrow
high Demand
Here's how Verilog is used in Senior Verification Engineer jobs:
  • Instantiated and integrated Denali memory models to replace many verilog models.
  • Project 3: CAN protocol Verification using systemverilog UVM methodology.
  • Implemented function coverage points for DisplayPort Transmitter in system Verilog.
  • Achieved Functional Verification using UVM and System Verilog.
  • Implemented Verilog Infrastructure for SoC verification.
  • Created random and directed test scenarios in System Verilog and uncovering critical bugs found in the IP core.
  • Worked on verification of GCAS2 a gene sequencing chip using UVM and system verilog.
  • Converted simulation environment and test cases from Verilog/Vera to SystemVerilog for the 10GBASE_T PHY.
  • Verified the PCH at the system level using System Verilog and OVM TB.
  • Implemented System Verilog Assertion (SVA) for LTSSM checkers on various scenarios.
  • Developed verilog ATA-IDE and UART simulation models including timing checks.
  • Test bench and test cases created in Verilog.
  • Develop system verilog assertions for interfaces 3.
  • Developed a new System Verilog testbench for an AXI-to-AHB and AHB-to-APB bridge that consists of a cache unit.
  • Verified DisplayPort Transmitter using system verilog testcases and found critical bugs in the DUT for main stream.
  • Verified the Queue Engine on the Harrier Processor using a UVM testbench implemented in System Verilog.
  • Have written verilog testcase for doing a JTAG access to efuse controller.
  • Develop the Stand alone test bench to verify the DFi System Verilog Assertions
  • Ported the HSD32 teal/truss based system verilog testbench into a UVM based system verilog testbench.

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25 Verilog Jobs

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4. Test Bench

demand arrow
high Demand
Here's how Test Bench is used in Senior Verification Engineer jobs:
  • Developed and owned the subsystem test bench for a clocking, reset and power management complex.
  • Develop test bench and test sequences in random and constraint random method.
  • Developed complete test bench using interface UVCs.

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8 Test Bench Jobs

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5. RTL

demand arrow
high Demand
Here's how RTL is used in Senior Verification Engineer jobs:
  • Assisted logic designers in integrating RTL features into simulation models.
  • Developed infrastructure to automate regressions and RTL coverage.
  • Developed BFM to issue flushes at L3 cache cluster using AVM methodology to validate RTL functionality such as evictions and coherency.
  • Verified Low Power RTL Design such as clock gating control logic and found many bugs in the logic.
  • Worked with designers and other verification engineers to resolve all the issues with RTL and fix the bugs.
  • Debugged failing tests to faulty microcode or RTL code and worked with logic designers to correct problems.
  • Replicated silicon bugs in simulation environment and validated RTL fixes and SW workarounds in very short time.
  • Implemented tag, state, LRU and data arrays in scoreboard to check RTL functionality.
  • Web-based applications for logging and documenting RTL bugs (UbiTrack).
  • Created RTL FSM Guide for Designers.
  • Acted as a RTL designer for modifying a SD/MMC host controller to support DDR and eMMC 4.3 and 4.4 standards.
  • Integrated JESD204 Verification IP into test environment, and designed tests to exercise and verify RTL and synthesized netlist functionality.
  • Managed RTL design of DC Offset Module and MATLAB implementation of Antenna Diversity algorithm for 802.11a baseband.
  • Consulted with Sbox RTL and validation experts to help with the Sbox fault analysis.
  • Create VHDL models of different blocks like LDOs, DACs, ADCs and amplifiers as part of RTL Verification.
  • Evaluated and implemented several RTL Coverage tools including Summit Design HDLScore, Verisity Surecov and Cadence NCCov.

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10 RTL Jobs

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6. Perl

demand arrow
high Demand
Here's how Perl is used in Senior Verification Engineer jobs:
  • Verified the back plane and created distributed simulation environment to test 8 boards using co-simulation methodology of VERILOG/PERL.
  • Utilized Perl for debugging large log files, EMACS editor, and a VI editor when required.
  • Created various Perl scripts to ease the Manual work done in Verification Flow.
  • Developed Perl scripts for single runs, and regression runs.
  • Developed PERL scripts for automating assertions.
  • Created PERL Coverage regression scripts.
  • Shell scripting experience (Unix, Perl).
  • Developed a runscript and regression script using Perl.

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1 Perl Jobs

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7. SOC

demand arrow
high Demand
Here's how SOC is used in Senior Verification Engineer jobs:
  • Managed remote site verification consultant groups in achieving the SoC level verification objectives.
  • Created comprehensive verification plan and strategy for on-time delivery of high quality SoCs.
  • Documented of internal procedures and information associated with the SIS verification organization.
  • Delivered SoC level verification methodology for different projects.
  • Identified socket configuration coverage gaps and channelized debug and test writing efforts to bring up the coverage uniformly across all instances.
  • Developed test plans and test cases to verify unit, subsystem and chip level functionality in a complex SOC environment.
  • Verified crucial blocks of the Wi-Fi SoC projects and found 30+ bugs on the legacy codes.
  • Owned SOC verification for the camera cluster and the video block.
  • Worked as SOC Verification Engineer, in Smart Grid Project.
  • Led verification of the second SOC.
  • Verified two SOCs targeting surveillance applications.
  • Created system images for automated deployment of IDbox and its associated software.
  • Worked on verification of the Antcreak SOC.
  • Reviewed and fixed HSD's for Rlink to drop to SPM/SOC.
  • Lead design verification of NAND flash memory controller SoCs used in Sandisk's flash memory cards and SSDs.
  • Trouble-shooted cross-functionally to lead execution of deliverables across project's value streams associated with GIS.

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16 SOC Jobs

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8. Asic

demand arrow
high Demand
Here's how Asic is used in Senior Verification Engineer jobs:
  • Verified TCP offload engine ASIC with PCI interface, routing tables, TCP protocol engine, and direct data placement.
  • Developed a PERL script to auto generate basic register tests, like walking-1 walking0, random read write.
  • Worked as ASIC verification engineer, verifying the latest Intel Processor Platform Controller Hub (PCH).
  • Create test benches and test software to provide verification of all the FPGA and ASIC functions.
  • Worked on Firmware/Software validation for the St. Jude Medical Merlin Basic at Home System.
  • Collaborated with the ASIC team, DFT team, architects and design team.
  • Core Competencies / Technical Skills ==================================== ASIC / CPU Design Verification.
  • Sole Design Verification engineer supporting the entire ASIC team.
  • Write test cases to verify the ASIC logic.
  • Post silicon RF ASIC test and verification
  • Implemented the ASIC verification processes.
  • Worked on verifying UMTS modem for Femto Cell ASIC.
  • Developed large multiprocessor hardware test benches to verify the functionality of FPGAs and ASICs being developed.
  • Architected the system environment to verify an asic integration that includes an embedded ARM7TDMI processor.
  • Created verification plans and built testbench and testcases for Voice Over IP signal processing ASICs.

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15 Asic Jobs

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9. Fpga

demand arrow
high Demand
Here's how Fpga is used in Senior Verification Engineer jobs:
  • Recreated failures seen in Lab on FPGA platform to simulation for Bugs fixing purpose.
  • Initial bring up for FPGA emulator.
  • Design using Altera FPGA for memory access and vector set control needed for Chip testing.
  • Authored test plan and implemented functional coverage for Stratix IV Mixed Signal FPGA.
  • Updated Vera Testbench to implement new FPGA.
  • Created Fault Coverage testbench with scoreboard using Verisity e for FPGA BIST project.
  • Implemented Summit Design HDLScore and Verisity Surecov on several FPGAs Discussed/solved many problems with AE.

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16 Fpga Jobs

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10. UVM

demand arrow
high Demand
Here's how UVM is used in Senior Verification Engineer jobs:
  • Modified and created new UVM sequences to exercise the DUT according to the specification.
  • Project 2: Optical Transport Network (OTN) verification using UVM.
  • Create and modify the existing UVM agents and scoreboards and monitors.
  • Project 4: AHB2AHB Bus Matrix Verification using UVM methodology.
  • Developed testbench based on UVM-e methodology.
  • Integrated various VIPs and created UVC like uvm_agent, score board and reference model.
  • Ensured that new UVM simulation results in Cadence IUS is consistent with the original testbench simulation results using Synopsys VCS.

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42 UVM Jobs

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11. PCI

demand arrow
high Demand
Here's how PCI is used in Senior Verification Engineer jobs:
  • Supported customer developments and integration of Intel s server based PCIE core into SOC/FPGA designs.
  • Used Denali PCIE RC Model interfacing with a LSI PCIE Core.
  • Worked with IBM Burlington, Vermont in PCIX Core Verification.
  • Project: MOSSBERG - PCIE Gen3 Device.
  • Developed verification methodology and e Verification Component (eVC) for PCI-Express and HP Proprietary interface for Root Complex chip.
  • Worked on verification of PCIe in various configurations used in a server chip set.
  • Studied PCIe Spec and developed DLLP and TLP layer compliance test plan.

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12. Full Chip

demand arrow
high Demand
Here's how Full Chip is used in Senior Verification Engineer jobs:
  • Owned timely building and releasing full chip models, providing side models with specific capabilities to other teams.
  • Created web based global infrastructure for full chip regression data collection and reporting.
  • Created Full Chip tests to exercise modules in full chip environment.
  • Involved in full chip emulation.
  • Developed UVM based testbench infrastructure and full chip level directed and random tests.
  • Led block and full chip level testbench architecture and component development.
  • Generated 400+ testcases on Block and Full Chip level.

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8 Full Chip Jobs

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13. IP

demand arrow
high Demand
Here's how IP is used in Senior Verification Engineer jobs:
  • Participated in process and staff improvement.
  • Review of the software test procedures and test scripts as per the checkpoint guidelines mentioned in DO-178B.
  • Coordinate, Manage and successfully run regression in multiple sites to get more regression cycles.
  • Developed a script to auto generate the OVM agent skeleton.
  • Design and code the models which interact with chip logic.
  • Performed module and chip level verification and test case development.
  • Develop Coverage model for the VIP and also BFM development.
  • Power resources in the chip and other power management blocks.
  • Ensured our schedule stayed on track through multiple issues.
  • Achieved multiple bug-free projects in real silicon successfully.
  • Automated test stimulus with scripting.
  • Chip level modeling using SystemC.
  • Debugged chip and board issues.
  • Developed Automation scripts and test APIs to verify requirements for Infusion devices and Intravenous Clinical Integration (IVCI) software platform.
  • Acted as Coordinator for VIPER, the integration testing point of Tivoli's core products.
  • Test personal computer south bridge and north bridge IC (Integrated Circuit) chipsets.
  • Develop IC chipset test programs mainly use C language and some Assembly programming.
  • Project Description Wholesale Settlements (WS) is a telecom product, which gives End to End Roaming Billing solution.
  • Led the co-simulation validation effort of an Intel X58 express desktop chipset and Itanium 9300 series Tukwila processor.
  • company went IPO in 1998 ) Successfully led several verification projects to tapeout.

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9 IP Jobs

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14. Verification Environment

demand arrow
high Demand
Here's how Verification Environment is used in Senior Verification Engineer jobs:
  • Involved in converting the existing block and system level verification environment into an OVM based and industry standard verification infrastructure.
  • Evaluated RVM verification methodology and set up verification environment.
  • Leveraged third-party verification IP in verification environments.
  • Implement more test scenarios to fill coverage holes, if required or enhance verification environment to hit missing cover points.
  • Helped and trained Junior level engineers to understand the verification environment and how to debug the failures from regression.
  • Team Size: 12 Technology used: Verification environment is in SystemVerilog and C language.
  • Involved in project planning, strategy development, architect the Verification Environment.
  • Defined testbench architecture per UVM and set up layered reusable verification environment.
  • Owned development of bus cluster verification environment for multi-core microprocessor.
  • Team Size: 4 Technology used: Verification environment is in System Verilog and C language.
  • Implemented Transactor, Scoreboard and Monitor in the Verification environment and Test cases with SCV
  • Developed verification environment and testcases including functional coverage groups/items using Specman 'e'.

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16 Verification Environment Jobs

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15. Code Coverage

demand arrow
average Demand
Here's how Code Coverage is used in Senior Verification Engineer jobs:
  • Generate Code Coverage using LDRA, Structural coverage analysis and update Code/Requirements/Tests/Analysis Reports.
  • Championed functional and code coverage automation.
  • Executed verification plan from inception to completion making sure it achieved 100% code coverage.
  • Utilized Cadence s Incisive Metrics Center (IMC) for verification code coverage.
  • Conducted Random Simulations, Code Coverage, and Gate Level Simulations.
  • Managed regression coverage to help acheived function and code coverage goals.

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9 Code Coverage Jobs

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16. Architecture

demand arrow
average Demand
Here's how Architecture is used in Senior Verification Engineer jobs:
  • Develop test cases based on requirements, architecture and interface control descriptions of the signaling system solutions.

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14 Architecture Jobs

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17. Verification Plan

demand arrow
average Demand
Here's how Verification Plan is used in Senior Verification Engineer jobs:
  • Developed verification plan for verifying sub modules and interfaces.
  • Developed Measurement and Verification Plans for each customer site.
  • Developed verification plan, created test cases, SV assertion checkers and function coverage model for coverage closure.
  • Involved in generation of Software verification plan (SVP) for the subsystem PSC.
  • Develop and execute the verification plan.
  • Directed / Random Testcase Development Verification Planning.
  • Created verification plans and built testbench and testcases for synthesizable PowerPC microprocessor.

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5 Verification Plan Jobs

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18. Test Procedures

demand arrow
average Demand
Here's how Test Procedures is used in Senior Verification Engineer jobs:
  • Executed verification & validation test procedures and protocols.
  • Prepared product verification and validation test plans, test procedures, & protocols for neurotherapy delivery catheters and neuro stimulation leads.

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19. Block Level

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average Demand
Here's how Block Level is used in Senior Verification Engineer jobs:
  • Developed test environments for IFP block level TCAM key generation with three levels of extraction and End-2-End checks in the test.

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4 Block Level Jobs

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20. OVM

demand arrow
average Demand
Here's how OVM is used in Senior Verification Engineer jobs:
  • Presented the pilot project, and received positive feedback and wider acceptance of the OVM methodology.
  • Ported and modified the existing OVM sequences to the new environment.
  • Led an OVM pilot project.

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10 OVM Jobs

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21. SVA

demand arrow
average Demand
Here's how SVA is used in Senior Verification Engineer jobs:
  • Write SVA assertion and functional coverage.
  • Set up formal verification flow and created property/SVA to assist post_Si debug.

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22. Ethernet

demand arrow
average Demand
Here's how Ethernet is used in Senior Verification Engineer jobs:
  • Involved in both Block and Chip levels Verification with stimulus such as Ethernet Packets switching at Layer2 and Layer3.
  • Project: LACE - 8-Ports 10-Gigabit Ethernet Chip with Congestion Detection Capability.

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23. VCS

demand arrow
average Demand
Here's how VCS is used in Senior Verification Engineer jobs:
  • Run simulation with VCS and generated Codes Coverage with its embedded feature.
  • Defect Analysis and tracking using IBM RQM/RTC and PVCS Tools.

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24. System Level

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average Demand
Here's how System Level is used in Senior Verification Engineer jobs:
  • Directed the System level Low power and gate level verification activities.
  • Create requirement traceability matrix to ensure the links from the detailed design to software requirements and system level requirements are complete.
  • Plan technical interchange meetings with various Responsible Engineers (RE's) for resolutions/concurrence of system level requirements for verification.

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15 System Level Jobs

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25. DMA

demand arrow
average Demand
Here's how DMA is used in Senior Verification Engineer jobs:
  • Involved in project planning, strategy development for GPDMA Verification.
  • Develop firmware drivers to verify mobile phone chipset, specialized in LPDDR1/LPDDR2 and Data Mover (DMA engine) blocks.
  • Verified CDMA modem for Femto Cell ASIC.
  • Verified USB3.0 Device and application DMA using third party BFM and System Verilog testcases.
  • Develop testbench, verification environment, testcases and sequences for GPDMA using AHB and AXI VIPs using UVM.

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26. Full Chip Verification

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average Demand

27. Python

demand arrow
average Demand
Here's how Python is used in Senior Verification Engineer jobs:
  • Saved manual test execution time while automating them using Python unit testing.
  • Used Python to automate much of the conversion.
  • Utilize custom and developed automated test tools & specialty test equipment; develop &validate automated test scripts with python 3.5.2.
  • Automated regressions using python to dump waveforms of failing test using random seed.

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28. Functional Verification

demand arrow
average Demand
Here's how Functional Verification is used in Senior Verification Engineer jobs:
  • Authored multiple functional verification test plans, focusing on behavioral coverage and risk mitigation.
  • Perform Functional Verification/Validation Testing as per the features of the product.

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29. C++

demand arrow
average Demand
Here's how C++ is used in Senior Verification Engineer jobs:
  • Worked on various block and sub module level verification in UVM/OVM, SystemC and C++.
  • Completed debugging and bug fixing in architecture SystemC/C++ code files used as a reference module.
  • Develop embedded firmware/software codes for embedded MIP/ARM processor using C/C++.
  • Migrated TCL/C/C++ tests into new Python/Oroboro environment.
  • Developed auto-Scan Stitching script for top module of CORE chips(C++) Coded a few Java Application programs
  • Develop Windows applications to automate QA tasks using mainly C++, Jython and Shell Programming.
  • Performed pre and post silicon verification in a Verilog/C++ test-bed environment.
  • Developed VC1/MPEG2 Packetized Elementary Stream (PES) protocol checking tools that used C++ model, Specman, and Perl script.

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30. Design Verification

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low Demand
Here's how Design Verification is used in Senior Verification Engineer jobs:
  • Developed the physical design verification and extraction tools.

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31. BFM

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low Demand

32. Modems

demand arrow
low Demand

33. Setup

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low Demand
Here's how Setup is used in Senior Verification Engineer jobs:
  • Configured different system setups to emulate customer sites, which involved changing the system carrier path (downstream and upstream).
  • Configured the Nanosim setup so as to get the accurate results and with fast speed.
  • Performed Mylex RAID GAM setup and tests for Buslogic SCSI HBA product line.

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34. CPU

demand arrow
low Demand
Here's how CPU is used in Senior Verification Engineer jobs:
  • Started participating next generation of SOC CPU testbench framework environment development via UVM methodology.

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35. Coverage Analysis

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low Demand

36. Rational Requisite Pro

demand arrow
low Demand

37. DUT

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low Demand
Here's how DUT is used in Senior Verification Engineer jobs:
  • Implemented RCX_SB scoreboard to perform automatic verification of DUT.
  • Report DUT issues to Design Engineer (cross site) and close them.
  • Developed tests, simulated and debugged the DUTs using Directed as well as constraint random tests using cadence's irun simulator.

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38. Specman

demand arrow
low Demand
Here's how Specman is used in Senior Verification Engineer jobs:
  • Developed an emulation environment for next-generation PowerPC microprocessors Implementing VERA coverage groups for the above environment Trained in Specman testbench tool.
  • Enabled the cosim teams to run several random CSI protocol exerciser tests by developing new sequences using Specman e-language.

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39. Linux

demand arrow
low Demand
Here's how Linux is used in Senior Verification Engineer jobs:
  • Implemented and executed tests on Windows and Linux platforms.

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40. FDA

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low Demand
Here's how FDA is used in Senior Verification Engineer jobs:
  • Performed heavy FDA-compliant documentation following new process documents.
  • Design and execute test cases for verification of software requirements, within an FDA regulated environment.
  • Assisted independent reviewers with verifying that test procedures met FDA guidelines and audits.

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41. I/O

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low Demand
Here's how I/O is used in Senior Verification Engineer jobs:
  • Led the I/O and link training verification of the memory controller for 3D Xpoint memory.

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42. QA

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low Demand
Here's how QA is used in Senior Verification Engineer jobs:
  • Develop Windows applications to automate QA tasks.
  • Serve as the QA Lead for the Informatics Current Business Team.
  • Perform static analysis on code using Polyspace/QAC tools.
  • Serve as the QA Lead for the Remisol Driver Core Team.

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43. Control Systems

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low Demand
2 Control Systems Jobs

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44. AHB

demand arrow
low Demand
Here's how AHB is used in Senior Verification Engineer jobs:
  • Project 5: AMBA AXI/AHB Bus protocol verification Responsibilities:.
  • Ported over AHB/APB bus functional models.
  • Modelled plug and play & easily configurable features for AHB.
  • Created test plan to support all the functionalities of AHB including SV Assertions, coverage plan and scoreboarding.

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45. Jude

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low Demand

46. SQL

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low Demand
Here's how SQL is used in Senior Verification Engineer jobs:
  • Created data archives to a SQL data base for future trend analysis.
  • Performed SQL query on backend database.

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47. I2C

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low Demand

48. SV

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low Demand
Here's how SV is used in Senior Verification Engineer jobs:
  • Involved in generation of SVCP, STM and SVR artifacts in Software verification life cycle.

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49. Simulator

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low Demand
Here's how Simulator is used in Senior Verification Engineer jobs:
  • Team leader for message generator traffic simulator (MGTS) and Sentinel product.
  • Execute integration tests on simulator; maintaining proper test results and records.
  • Moderate experience on Agilent 8960 and Anritsu 8475 network simulators.

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50. Software Development

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low Demand
2 Software Development Jobs

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Senior Verification Engineer Jobs

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20 Most Common Skills For A Senior Verification Engineer

Test Cases

19.2%

Functional Coverage Model

11.1%

Verilog

6.7%

Test Bench

5.3%

RTL

5.0%

Perl

4.7%

SOC

4.4%

Asic

4.3%

Fpga

4.3%

UVM

4.0%

PCI

3.8%

Full Chip

3.7%

IP

3.4%

Verification Environment

3.4%

Code Coverage

3.3%

Architecture

2.8%

Verification Plan

2.7%

Test Procedures

2.7%

Block Level

2.6%

OVM

2.6%
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Typical Skill-Sets Required For A Senior Verification Engineer

Rank Skill
1 Test Cases 13.2%
2 Functional Coverage Model 7.6%
3 Verilog 4.6%
4 Test Bench 3.6%
5 RTL 3.4%
6 Perl 3.2%
7 SOC 3.0%
8 Asic 2.9%
9 Fpga 2.9%
10 UVM 2.7%
11 PCI 2.6%
12 Full Chip 2.5%
13 IP 2.3%
14 Verification Environment 2.3%
15 Code Coverage 2.2%
16 Architecture 1.9%
17 Verification Plan 1.9%
18 Test Procedures 1.9%
19 Block Level 1.8%
20 OVM 1.8%
21 SVA 1.6%
22 Ethernet 1.6%
23 VCS 1.6%
24 System Level 1.6%
25 DMA 1.5%
26 Full Chip Verification 1.5%
27 Python 1.4%
28 Functional Verification 1.4%
29 C++ 1.3%
30 Design Verification 1.3%
31 BFM 1.2%
32 Modems 1.1%
33 Setup 1.1%
34 CPU 1.0%
35 Coverage Analysis 1.0%
36 Rational Requisite Pro 1.0%
37 DUT 1.0%
38 Specman 1.0%
39 Linux 0.9%
40 FDA 0.9%
41 I/O 0.9%
42 QA 0.8%
43 Control Systems 0.8%
44 AHB 0.7%
45 Jude 0.7%
46 SQL 0.7%
47 I2C 0.7%
48 SV 0.7%
49 Simulator 0.7%
50 Software Development 0.7%
{[{skill.rank}]} {[{skill.name}]} {[{skill.percentageDisplay}]}%
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17,093 Senior Verification Engineer Jobs

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