Senior verification engineer jobs in San Diego, CA

Embedded Software Engineer ***Must be Local to San Diego CA and able to work onsite in a hybrid capacity*** Temp to Hire We are seeking an Embedded Software Engineer to design, develop, test, and support embedded and PC-based software solutions. This role focuses on firmware and application development across microcontroller platforms and real time systems, with responsibilities spanning embedded controller development, system integration, software validation, and cross-functional collaboration. Essential Job Functions Develop embedded software for microcontroller-based systems using both bare metal and real time operating systems. Create board bring up code, device drivers, boot loaders, firmware update mechanisms, and software interfaces for sensors and peripherals. Design, implement, test, and debug embedded device controllers and related software components. Develop PC applications that support diagnostics, device testing, production testing, and test automation. Conduct unit tests, integration tests, system level debugging, and code reviews to ensure quality and reliability. Diagnose and resolve hardware and software issues in real time environments. Integrate software modules, third party libraries, and APIs into existing or new systems. Perform software validation, functional testing, and system compatibility checks across environments. Ensure compliance with applicable safety standards, industry norms, and internal policies. Optimize software for performance, memory utilization, and power efficiency. Support planning, task definition, and estimation as part of development efforts. Collaborate with engineering teams (electrical, mechanical, quality) to ensure seamless product integration. Analyze, document, and track software defects and improvements to resolution. Contribute to continuous improvement of development processes, tools, and procedures. Support software deployment, configuration, and technical requirements. Use version control (e.g., Git), build systems, and CI/CD workflows to streamline development. Assist production teams in troubleshooting and improving system performance. Provide engineering support where needed across departments. Perform additional engineering duties as assigned. Minimum Qualifications Bachelor's degree in Engineering, Computer Science, or a related technical field. 3+ years of hands-on experience in embedded systems development. Proficiency in C or C++ programming with experience in multithreaded code and hardware-software integration. Experience with microcontrollers (Cortex-M family preferred) in both real time operating system and bare metal environments. Experience with board bring up and developing low-level drivers for interfaces such as SPI, I2C, UART, ADC, DAC, USB, and display interfaces. Practical experience with debugging tools and test equipment (e.g., JTAG, GDB, logic analyzers, scopes). 2+ years of developing PC-based applications using C# and integrating with databases. Familiarity with setting up toolchains, build systems, and debugging environments. Knowledge of software engineering best practices and tools, including version control and issue tracking. Ability to read and interpret schematics, datasheets, and hardware documentation. Strong problem solving, debugging, and analytical skills. Excellent communication and interpersonal skills. A positive attitude and ability to work collaboratively in team environments.

Hanwha Vision America, an affiliate of the Fortune Global 500 Hanwha Group, is a global leader in advanced network video surveillance and access control solutions. We deliver end-to-end security products-including access control systems, IP cameras, storage, and video management software-serving critical sectors such as retail, transportation, education, healthcare, finance, and critical infrastructure. We are seeking a Senior C++ application developer to join our team, dedicated to pioneering the next generation of building access control solutions. You will be instrumental in developing high-performance, secure, and reliable firmware across our entire product line. Key Responsibilities You will act as a key technical leader, driving the strategic design and full-lifecycle delivery of the end-to-end solution, focusing on high-quality firmware application. Architect High-Performance Systems: Design and lead the implementation of scalable, C++ applications that maximize efficiency, reliability, and speed across multi-layered systems. Secure software Development: Design, implement, and maintain the secure software foundation for our products, ensuring robust integration with SDKs, storage systems, and cloud services. Vulnerability Analysis & Mitigation: Proactively analyze firmware and system architecture for potential security vulnerabilities and design robust, scalable countermeasures, driving a security-first development mindset. End-to-End Product Engineering: Drive the development, integration, and deployment of firmware across multiple hardware platforms, ensuring high quality and performance from prototype to mass production. Testing, Automation & CI/CD: Develop and maintain comprehensive unit, integration, and performance tests. Significantly contribute to the build and production test infrastructure, owning key components of the CI/CD pipeline. Code Quality & Architectural Refactoring: Conduct rigorous code reviews, champion best practices for maintainability, and proactively lead the refactoring of existing codebase components to ensure future feature readiness and technological longevity. Required Qualifications Education: Bachelor's or Master's degree in Computer Science, Computer Engineering, or a closely related technical field. Experience: A minimum of 8+ years of progressive professional experience as a C++ application developer, or in a similar leadership role. Proficiency: Expert-level proficiency C++ is mandatory. Core Expertise & Technical Skills Category Key Technologies & Areas of Expertise Networking MQTT/HTTPS Embedded Stack Linux, Yocto, C++ Toolchains & Infra Cross-Platform Compilation (Toolchain), CMake/Make, Debuggers (GDB). Achievements & Leadership Deployment Scale: Proven track record of developing and successfully deploying firmware to mass-market devices. Automation: Direct experience building and optimizing a sophisticated firmware CI/CD pipeline for continuous integration and automated testing. Troubleshooting Mastery: Proven ability to troubleshoot and diagnose complex, intermittent issues end-to-end across hardware, firmware, and network layers.

Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love to have you join us. As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all fields (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design u0026 micro-architecture teams. A key component to the job is understanding the functional u0026 performance goals of the design and you use this knowledge to test effectively. You develop test plans, tests u0026 coverage plans as well as define our next generation verification methodology u0026 testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP: - Neural Engine hardware - DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec formats such as VP9, AV1 - Hardware security, including cryptographic algorithm implementations - High-Speed IO standards such as PCI Express, DisplayPort, MIPI - Power management and fabric infrastructure - Memory cache management - Display Subsystem for variety of panels and products These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It's up to you! Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology u0026 philosophy Knowledge of SystemVerilog, digital simulation and debug Knowledge of computer architecture and digital design fundamentals Good SW programming skills with knowledge of data structures and algorithms Experience with Python, Perl, or similar scripting language Ability to work independently to deliver the project goals Knowledge of verification methodologies like UVM Experience with C/C++, assembly is a plus. Excellent interpersonal and communication skills and the dream to take on diverse challenges. Minimum of BS + 10 years relevant industry experience.

Arm is the industry's leading supplier of microprocessor technology, offering the widest range of microprocessor cores to address the performance, power, and cost requirements for almost all application markets. With a vibrant ecosystem of over 1,000 partners and more than 150 billion processors shipped, our technology is at the heart of a computing and connectivity revolution that continues to transform the way people live and businesses operate. Job Overview: Join our dynamic FPGA Prototyping team, a key part of Arm's Solutions Engineering group, as a Verification Engineer! We are a dedicated group of engineers providing a robust platform to build and test software on Arm's brand-new subsystems and System-on-Chips (SoCs). Our mission is to accelerate the development process by offering a versatile and high-performance prototyping environment that enables seamless software integration and validation. These solutions target a wide range of market segments including mobile, server, IoT, automotive, and more. As a member of this team your day-to-day work will consist primarily of driving verification of SoC RTL designs that are modified for FPGA implementation, developing and maintaining SoC verification testbench, integrating third party VIPs & FPGA specific IP models, writing Testcases in C, reusing C Testcases from internal IP/ SoC frontend team, creating test-plans, developing tools using scripting languages like Python, Perl, Shell for automation of tasks. If you are looking for a role that combines hardware and software skills in an environment where you can make a meaningful contribution, we'd love to hear from you! Join our committed team that builds innovative FPGA solutions and collaborates closely to achieve great results. Responsibilities: * Implement verification strategies to ensure detailed testing of the assigned Subsystem or SoC module. * Work closely with design engineers, architects, and other verification engineers to understand design requirements and plan verification. * Apply excellent verbal and written communication skills to report verification progress, issues, and results to customers. * Automate test cases and regression suites to improve verification efficiency and coverage. Required Skills and Experience: * Solid understanding of SoC Verification (using C Testcases), hardware description and verification languages e.g. SystemVerilog, Verilog, VHDL. * Understanding of Computer architecture, bus protocols (e.g., AXI, AHB), and peripherals. * Experience with Tcl, Python or other scripting languages. "Nice To Have" Skills and Experience: * Experience with ARM-based designs and/or ARM System Architectures. * Familiarity with ARM debugger and trace features e.g ARM DS, DSTREAM. * Knowledge of memory subsystems and/or high speed peripherals (e.g. PCIe/CXL) will be a plus, including integration of these IP models into a design. Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: ************************************** #LI-RJ1 Salary Range: $156,500-$211,700 per year We value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm's approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team's needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don't discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Introduction to the job We are looking for a Design Verification Engineer to serve as a technical leader driving verification strategy and execution for highly complex FPGA designs. This role will architect advanced verification environments, define methodologies, and ensure best-in-class quality for ASML's EUV Source systems. It requires deep technical expertise, leadership in verification practices, and the ability to influence design and verification decisions across teams. Role and responsibilities Define and own verification strategy for large-scale, multi-block FPGA systems. Architect and implement advanced, reusable verification environments using SystemVerilog UVM and UVMF. Develop sophisticated test benches, constrained-random tests, and coverage models to achieve full functional and code coverage. Drive requirement traceability and compliance through robust documentation and reporting. Collaborate with architects, design engineers, and cross-functional teams to ensure design integrity and verification completeness. Lead debug efforts for complex system-level issues and root-cause analysis. Establish and enforce best practices for verification methodology, automation, and regression management. Mentor and guide junior and mid-level engineers; provide technical leadership and training. Influence tool adoption, methodology improvements, and process optimization across the organization. Other duties as assigned. Software Engineer 3- Education and Experience Bachelors' degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields. 2+ years' experience with a Bachelor's degree. 0 + years' experience with a Master's degree. Understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification. Experience with UVM for modular and reusable verification IP development. Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks. The current base annual salary range for this role is currently: $106,500-177,500. Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members. Senior Software Engineer 1 - Education and Experience Bachelors' degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields. 5+ years' experience with a Bachelor's degree. 2 + years' experience with a Master's degree. 1+ years' experience with a PhD. Extensive experience with simulation tools (e.g., QuestaSim, VCS, or similar) and regression management. Strong understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification. Experience with UVM for modular and reusable verification IP development. Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks. The current base annual salary range for this role is currently: $132,000 - $220,000 Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members. Senior Software Engineer 2 - Education and experience Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields. 8+ years' experience with a Bachelor's degree. 5 + years' experience with a Master's degree. 3+ years' experience with a PhD. Must possess industry experience in FPGA design verification; equivalent experience in ASIC workflows acceptable. Proven track record of leading verification for complex SoC or FPGA systems, including hardware bring-up and test. Expert-level proficiency in SystemVerilog UVM, including architecting environments and building custom components from scratch. Extensive experience with simulation tools (e.g., QuestaSim, VCS, or similar) and regression management. Strong understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification. Deep experience with UVM for modular and reusable verification IP development. Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks. The current base annual salary range for this role is currently: $144,000-$240,000 Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members. Preferred: Proficiency in scripting languages (Python, Perl, or similar) for automation and flow optimization. Experience with UVMF for modular and reusable verification environments. Exposure to formal verification techniques and advanced debug methodologies. Skills Ability to architect and optimize complex verification environments for scalability and reuse. Advanced problem-solving and debugging skills for system-level and multi-block designs. Strong leadership and mentoring capabilities; able to guide teams and influence technical direction. Excellent communication and collaboration skills for cross-functional engagement. Expertise in coverage analysis and closure strategies. Strong organizational and planning skills for managing large verification projects. Experience driving methodology improvements and automation initiatives. Familiarity with FPGA-specific verification strategies and hardware validation. Ability to innovate and implement process enhancements for efficiency and quality. Other Information This position is located on-site in San Diego, CA . It requires onsite presence to attend in-person work-related events, trainings and meetings and to further ensure teamwork, collaboration and innovation. A flexible workplace arrangement may be available to employees working in roles conducive to remote work (up to two days a week). Routinely required to sit; walk; talk; hear; use hands to keyboard, finger, handle, and feel; stoop, kneel, crouch, twist, reach, and stretch. Occasionally required to move around the campus. Occasionally lift and/or move up to 20 pounds. Specific vision abilities required by this job include close vision, color vision, peripheral vision, depth perception, and ability to adjust focus. Must be willing to work in a clean room environment, wearing coveralls, hoods, booties, safety glasses and gloves for entire duration of shift. While performing the duties of this job, the employee routinely is required to sit; walk; talk; hear; use hands to keyboard, finger, handle, and feel; stoop, kneel, crouch, twist, reach, and stretch. EOE AA M/F/Veteran/Disability Potential candidates will meet the education and experience requirements provided on the above job description and excel in completing the listed responsibilities for this role. All candidates receiving an offer of employment must successfully complete a background check band any other tests that may be required. #LI-MO1 The current base annual salary range for this role is currently: $0-0 Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members. The Company offers employees and their families, medical, dental, vision, and basic life insurance. Employees are able to participate in the Company's 401k plan. Employees will also receive eight (8) hours of vacation leave every month and (13) paid holidays throughout the calendar year. For more information, please contact the Recruiter or click on this link Compensation & Benefits in the US. All new ASML jobs have a minimum application deadline of 10 days. This position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology. Inclusion and diversity ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions. Request an Accommodation ASML provides reasonable accommodations to applicants for ASML employment and ASML employees with disabilities. An accommodation is a change in work rules, facilities, or conditions which enable an individual with a disability to apply for a job, perform the essential functions of a job, and/or enjoy equal access to the benefits and privileges of employment. If you are in need of an accommodation to complete an application, participate in an interview, or otherwise participate in the employee pre-selection process, please send an email to USHR_Accommodation@asml.com to initiate the company's reasonable accommodation process. Please note: This email address is solely intended to provide a method for applicants to initiate ASML's process to request accommodation(s). Any recruitment questions should be directed to the designated Talent Acquisition member for the position.

Introduction to the job We are looking for a Design Verification Engineer to serve as a technical leader driving verification strategy and execution for highly complex FPGA designs. This role will architect advanced verification environments, define methodologies, and ensure best-in-class quality for ASML's EUV Source systems. It requires deep technical expertise, leadership in verification practices, and the ability to influence design and verification decisions across teams. Role and responsibilities * Define and own verification strategy for large-scale, multi-block FPGA systems. * Architect and implement advanced, reusable verification environments using SystemVerilog UVM and UVMF. * Develop sophisticated test benches, constrained-random tests, and coverage models to achieve full functional and code coverage. * Drive requirement traceability and compliance through robust documentation and reporting. * Collaborate with architects, design engineers, and cross-functional teams to ensure design integrity and verification completeness. * Lead debug efforts for complex system-level issues and root-cause analysis. * Establish and enforce best practices for verification methodology, automation, and regression management. * Mentor and guide junior and mid-level engineers; provide technical leadership and training. * Influence tool adoption, methodology improvements, and process optimization across the organization. * Other duties as assigned. Software Engineer 3- Education and Experience * Bachelors' degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields. * 2+ years' experience with a Bachelor's degree. * 0 + years' experience with a Master's degree. * Understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification. * Experience with UVM for modular and reusable verification IP development. * Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks. The current base annual salary range for this role is currently: $106,500-177,500. Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members. Senior Software Engineer 1 - Education and Experience * Bachelors' degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields. * 5+ years' experience with a Bachelor's degree. * 2 + years' experience with a Master's degree. * 1+ years' experience with a PhD. * Extensive experience with simulation tools (e.g., QuestaSim, VCS, or similar) and regression management. * Strong understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification. * Experience with UVM for modular and reusable verification IP development. * Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks. The current base annual salary range for this role is currently: $132,000 - $220,000 Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members. Senior Software Engineer 2 - Education and experience * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields. * 8+ years' experience with a Bachelor's degree. * 5 + years' experience with a Master's degree. * 3+ years' experience with a PhD. * Must possess industry experience in FPGA design verification; equivalent experience in ASIC workflows acceptable. * Proven track record of leading verification for complex SoC or FPGA systems, including hardware bring-up and test. * Expert-level proficiency in SystemVerilog UVM, including architecting environments and building custom components from scratch. * Extensive experience with simulation tools (e.g., QuestaSim, VCS, or similar) and regression management. * Strong understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification. * Deep experience with UVM for modular and reusable verification IP development. * Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks. The current base annual salary range for this role is currently: $144,000-$240,000 Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members. Preferred: * Proficiency in scripting languages (Python, Perl, or similar) for automation and flow optimization. * Experience with UVMF for modular and reusable verification environments. * Exposure to formal verification techniques and advanced debug methodologies. Skills * Ability to architect and optimize complex verification environments for scalability and reuse. * Advanced problem-solving and debugging skills for system-level and multi-block designs. * Strong leadership and mentoring capabilities; able to guide teams and influence technical direction. * Excellent communication and collaboration skills for cross-functional engagement. * Expertise in coverage analysis and closure strategies. * Strong organizational and planning skills for managing large verification projects. * Experience driving methodology improvements and automation initiatives. * Familiarity with FPGA-specific verification strategies and hardware validation. * Ability to innovate and implement process enhancements for efficiency and quality. Other Information * This position is located on-site in San Diego, CA . It requires onsite presence to attend in-person work-related events, trainings and meetings and to further ensure teamwork, collaboration and innovation. * A flexible workplace arrangement may be available to employees working in roles conducive to remote work (up to two days a week). * Routinely required to sit; walk; talk; hear; use hands to keyboard, finger, handle, and feel; stoop, kneel, crouch, twist, reach, and stretch. Occasionally required to move around the campus. * Occasionally lift and/or move up to 20 pounds. * Specific vision abilities required by this job include close vision, color vision, peripheral vision, depth perception, and ability to adjust focus. * Must be willing to work in a clean room environment, wearing coveralls, hoods, booties, safety glasses and gloves for entire duration of shift. * While performing the duties of this job, the employee routinely is required to sit; walk; talk; hear; use hands to keyboard, finger, handle, and feel; stoop, kneel, crouch, twist, reach, and stretch. EOE AA M/F/Veteran/Disability Potential candidates will meet the education and experience requirements provided on the above job description and excel in completing the listed responsibilities for this role. All candidates receiving an offer of employment must successfully complete a background check band any other tests that may be required. #LI-MO1 The current base annual salary range for this role is currently: $0-0 Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members. The Company offers employees and their families, medical, dental, vision, and basic life insurance. Employees are able to participate in the Company's 401k plan. Employees will also receive eight (8) hours of vacation leave every month and (13) paid holidays throughout the calendar year. For more information, please contact the Recruiter or click on this link Compensation & Benefits in the US. All new ASML jobs have a minimum application deadline of 10 days. This position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology. Inclusion and diversity ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions. Request an Accommodation ASML provides reasonable accommodations to applicants for ASML employment and ASML employees with disabilities. An accommodation is a change in work rules, facilities, or conditions which enable an individual with a disability to apply for a job, perform the essential functions of a job, and/or enjoy equal access to the benefits and privileges of employment. If you are in need of an accommodation to complete an application, participate in an interview, or otherwise participate in the employee pre-selection process, please send an email to USHR_Accommodation@asml.com to initiate the company's reasonable accommodation process. Please note: This email address is solely intended to provide a method for applicants to initiate ASML's process to request accommodation(s). Any recruitment questions should be directed to the designated Talent Acquisition member for the position.

Our Team: Semtech Corporation is a leading supplier of analog and mixed-signal semiconductors for high-end consumer, enterprise computing, communications, and industrial equipment. As our future market opportunities have increased in recent years, we have continued to invest in disruptive analog platforms and have created innovative new solutions for a wide range of leading edge products. The Sensing Product Group located in our San Diego office has unique expertise in system level platform solutions for Sensing Products including Touch & Proximity. These are leading edge low power touch-interface solutions integrated with highly accurate ADCs for enhanced sensing performance. These ultra-small, feature-rich sensing systems are optimized for a wide range of battery-powered, portable applications such as smartphones, laptops, tablets, wearables, handheld devices and other consumer or ITA control applications. Job Summary: The Sr. Integrated Circuit (IC) Verification Engineer is responsible for developing and implementing verification plans for a variety of mixed-signal integrated circuit blocks and systems. The Sr. Integrated Circuit (IC) Verification Engineer will closely collaborate with system, digital & physical design, embedded firmware, analog, and cross functional teams. The role also includes technical leadership, mentoring and supervision of junior verification engineers, pre-silicon validation, and support to silicon validation, production test and application engineers. Responsibilities: Define, develop and optimize comprehensive verification plans and test strategies for digital/mixed-signal IP blocks, subsystems, and full integrated circuits. Work closely with design teams to understand micro-architecture and functional specifications. Create and maintain detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews. (30%) Design and implement complex testbenches using SystemVerilog and UVM methodology. Perform block and chip-level register-transfer level (RTL), gate-level and analog/mixed-signal (AMS) verification. Develop directed test cases, constrained-random verification environments and reusable verification components. Debug complex simulation failures and identify root causes in design or verification environments. Improve verification scalability and portability from project to project by environment enhancement and tools automation. Generate and manage continuous integration, regression testing, scoreboards, monitors, and checkers. (30%) Interface with system, digital hardware, embedded firmware, analog and cross functional teams. (10%) Supervise and mentor junior verification engineers. (15%) Drive adoption of advanced verification methodologies, best practices and tool evaluation. (5%) Support silicon lab evaluation, performance characterization and debug. (5%) Technical support to test, product and application engineers. (5%) Minimum Qualifications: 8+ years of industry experience in integrated circuit design verification (DV) B.S. or M.S. in Electrical or Computer Engineering Strong analytical, synthesis and problem solving skills In-depth knowledge and experience in digital IC verification for mixed-signal ICs with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, embedded signal processing, external IPs, and analog peripherals. Proficiency in SystemVerilog as High-level Verification Language and UVM implementation, Verilog/VHDL, scripting languages (Python, Perl), debugging capabilities, and industry leading EDA verification tools (Synopsys, Cadence, Siemens) Demonstration of technical leadership Experience with standard hardware protocols (I2C, I3C, SPI, MIPI) Independent, self-motivated, rigorous, innovating, team player and able to follow through Excellent verbal and written communication skills Desired Qualifications Knowledge of system-level aspects: signal processing, mixed-signal, digital hardware, embedded firmware, analog, modelling, test and application Experience with analog block behavioral modelling with SV RNM/Verilog/VHDL Experience with consumer and/or ITA market circuit developments The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description. All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities. We are proud to be an EEO employer M/F/D/V. We maintain a drug-free workplace. A reasonable estimate of the pay range for this position is $130,000 - $183,206. There are several factors taken into consideration in determining base salary, including but not limited to: job-related qualifications, skills, education and experience, as well as job location and the value of other elements of an employee's total compensation package. #li-hybrid #LI-RB1

The Senior V&V Engineer plays a critical role in ensuring Carlsmed's medical device software systems meet safety, performance, and regulatory requirements. This role is responsible for planning, executing, and documenting verification and validation activities across software systems. The engineer will collaborate closely with R&D, Software Engineering, Mechanical Engineering, Operations, and Regulatory teams to ensure products comply with FDA, ISO, and IEC design control standards. The ideal candidate has deep experience in software based medical device V&V, strong technical test skills, exceptional documentation discipline, and the ability to work across complex, multidisciplinary product architectures. Key Responsibilities Test Strategy & Planning Develop and maintain comprehensive V&V plans, including Verification Plans, Validation Plans, Test Protocols, Test Reports, and Traceability Matrices. Define system-level test strategies for software, hardware, and integrated platforms in compliance with FDA 21 CFR 820.30, ISO 13485, IEC 62304, etc. Contribute to risk management activities (hazard analysis, FMEA) and ensure test coverage aligns with risk controls. Execution & Documentation Execute verification and validation test protocols, including functional, regression, performance, and usability testing. Document objective evidence and maintain high-quality engineering records suitable for regulatory audits and submissions. Ensure full traceability between user needs, system/software requirements, risk controls, and test cases. Cross-Functional Collaboration Work closely with Mechanical Engineering and Operations to clarify requirements and ensure they are testable and unambiguous. Partner with Software, Clinical, and Quality teams to identify defects early and improve design robustness. Support Regulatory and Quality teams by contributing to 510(k) and technical documentation packages. Tools & Process Ownership Manage test environments-including configurations for hardware, imaging datasets, and software builds. Use and improve test management tools such as Jira, TestRail, Jama, etc. Drive continuous improvement in V&V processes, including automation opportunities, documentation templates, and design control workflows. System-Level Testing Conduct integrated testing across imaging, planning software, and hardware subsystems. Support image-based testing (CT, MRI, X-ray) and anatomical model validation as needed. Perform root-cause analysis in collaboration with engineering teams for system failures or anomalies. Qualifications Bachelor's or Master's degree in Biomedical Engineering, Systems Engineering, Computer Science, Mechanical Engineering, or related field. 5+ years of experience in V&V for medical devices or other regulated industries. Strong knowledge of FDA, ISO 13485, IEC 62304, etc. standards and Design Controls. Hands-on experience writing V&V documentation (test plans, protocols, reports, trace matrices). Proficiency in testing complex systems that combine software, hardware, and clinical workflows. Familiarity with defect tracking and test management tools (e.g., Jira, TestRail, Jama). Strong analytical, troubleshooting, and communication skills. Experience with imaging-based systems, surgical workflows, or cloud-connected devices is a plus. (Preferred) Background supporting regulatory submissions such as 510(k). Equal Opportunity Employer Carlsmed is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran, or disability status. Carlsmed is committed to providing reasonable accommodation for candidates with disabilities in our recruitment process. If you need assistance or accommodation due to a disability, please let us know. Compensation We are pleased to provide a competitive salary and benefits. Our benefits reflect our investment in the overall health and well-being of our employees and their families. including paying 100% of monthly healthcare, dental and vision insurance premiums, a 401(k) plan with employer matching, and unlimited PTO. The expected pay range is $145,000 to $165,000. Compensation may vary based on related skills, experience, and relevant key attributes.

Mirafra is a global product engineering services company with expertise in semiconductor design, embedded and application software. Job Title : Design Verification Engineer Job Type : Full time Location : San Diego And Bay Area Job Description : Strong verification skills: test planning, problem solving, debug, adversarial testing. Multimedia Camera Image processing, Video or graphics hardware experience is preferred. Strong working knowledge of HVLs: System Verilog, VERA/e-Specman, System C. Experience with methodologies like RVM/VMM/OVM/UVM. RTL design experience and/or very strong OOPs programming experience is also a plus. Good written and oral communications skills required. Experience with simulation acceleration tool like Veloce/Palladium is a plus. Skill required: CPU, (MC: middle core, ARM architecture) Decent knowledge of assertions. SV and decent UVM knowledge Code coverage. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. Additional Information All your information will be kept confidential according to EEO guidelines.

Description About the Company Balboa Water Group is the health and wellness industry's leading provider of electronic control systems, electronic accessories, pumps, jets, and other therapy products. Our dedication to excellence and quality for five decades has made us the premier, single-source provider of innovative and reliable designs, state-of-the-art manufacturing, and outstanding customer service worldwide. Due to our rapid growth, we are looking for passionate and talented team members that want to work in an organization that values integrity, diversity, intellectual curiosity and accountability. Job Summary As a Design Validation Engineer, you will be responsible for designing, developing, and executing test plans and procedures to ensure the quality and reliability of our products. You will work closely with the engineering team to identify, analyze, and resolve issues throughout the development lifecycle. Key Job Responsibilities * Develop and execute test plans, test cases, and procedures for software and hardware products. * Perform functional, regression, integration, and system testing to verify product requirements. * Generate report from Design Validation Plan (DVP) * Identify, document, and track defects using tools like Azure DevOps or Jira, and collaborate with engineering teams to resolve them. * Collaborate with software and hardware engineers to troubleshoot and resolve issues. * Participate in design and code reviews to assess product testability and quality. * Maintain comprehensive test documentation, including test reports, specifications, and metrics. * Contribute to continuous improvement by refining testing methodologies and identifying process improvements. * Coordinate DFMEA (Design Failure Mode and Effects Analysis) and ECN (Engineering Change Notice) processes. * Engineering documentation drawing, specifications * Special characteristics: Fit, form, function, durability * Ensure compliance with industry regulations and safety standards. * Establish lines of communication with customers, suppliers and R&D Qualifications Education Requirements BSEE degree in a related science or technology field of study. Experience Requirements * 3+ years of professional experience in product design process and life of product support. * Proven experience in software and hardware verification and validation testing (V&V). * Proficiency in writing technical engineering documents, test plans, and test cases. * Experience with agencies regulation, and compliance test and certification process (UL,FCC,CE). Required Skills/Abilities * Hands-on experience with end-to-end product testing, from concept to design completion. * Working knowledge of APQP methodology * Understand NPI Gate Process * Ability to interpret product requirements, propose test strategies, and identify risks. * Expertise in developing and executing functional, regression, and performance tests. * Proficient in using issue-tracking tools such as Azure DevOps, Jira, or similar platforms. * Excellent verbal and written communication skills, with the ability to convey technical details clearly. * Strong attention to detail, problem-solving skills, and a sense of urgency. * Ability to learn new tools and testing methodologies quickly. * Comfortable working independently and collaboratively with minimal supervision. Salary Range: $85,000 - $105,000 EEO Statement Balboa Water Group is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Title: Sr. Embedded S/W Engineer: ETH PHY/MAC Layer Term: Long Term Contract/Potential Perm Must Have: RTOS Extensive Embedded Linux background Extensive background in lower Networking Layers: ETH PHY/L1 C/C++ (17/20/23) Solid experience with Controller/Sensor Areas of experience in 1 or more of the following: SatCom/ Software Defined Radios/Modem Design/Automotive/Avionics/AI/EV Charging/Aerospace Nice to have MAC Layer/L2 Yocto PetaLinux BareMetal C#/Golang Benefits A2e Does NOT Accept Unsolicited Resumes or Referrals from any source other than the candidate, and, as a result, we will not be considering any unsolicited referrals or resumes sent to us as a fee -based candidate submittal. Any unsolicited resumes sent to A2e, including unsolicited resumes sent to a A2e mailing address, fax machine or email address, directly to A2e employees, or to A2e's resume database will be considered A2e property. A2e will NOT pay a fee for any placement resulting from the receipt of an unsolicited resume.

General Atomics (GA), and its affiliated companies, is one of the world's leading resources for high-technology systems development ranging from the nuclear fuel cycle to remotely piloted aircraft, airborne sensors, and advanced electric, electronic, wireless and laser technologies. General Atomics Electromagnetic Systems (GA-EMS) designs and manufactures first-of-a-kind electromagnetic and electric power generation systems. GA-EMS' expanding portfolio of specialized products and integrated system solutions support critical fleet, space systems and satellites, missile defense, power and energy, and process and monitoring applications for defense, industrial, and commercial customers worldwide. We currently have an exciting opportunity for a Senior System Engineer to join our team located in San Diego, CA. DUTIES AND RESPONSIBILITIES: * Perform and lead multiple integrated product teams for the development of prototype systems through design, integration and test. * Using a SysML tool, like Cameo, to produce system models which includes developing the standard 9 diagrams of activity, block definition, internal block, package, parametric, requirement, sequence, state machine and use cases. * Provides adaptable support to the systems engineering organization. Responsibilities may include direct program systems engineering support, proposal development, or support to internal development tasks. * Perform analysis and decomposition of system, segment, subsystem and assembly requirements. * Lead system engineering team through development of system requirements, ICDs, test plans/procedures and other system engineering artifacts. * Lead multiple integrated product teams through system analysis, assembly, integration and testing. * Lead the design and development of prototype systems through design, integration, and test. * Collaborate with all levels of program and engineering staff on design, integration and test matters and support other teams/disciplines as necessary including to develop deployment, block definition, internal block definition, activity, state & sequence diagrams, perform requirement capture and characterization, develop parametric analysis, enable all SysML-based artifact development and use in a model-based systems engineering (MBSE) environment, test plans and procedures including environmental testing. * Support program design and readiness reviews including presenting at these reviews. * Supports operation of engineering systems and documents any problems. * Opportunities will arise to support internal development and new business opportunities. * Devises new approaches to resolve unusual or complex engineering problems. * Troubleshoot conflicting design/development requirements, difficult coordination requirements, and special material requirements. * Provides documentation and makes technical presentations as required. * May represent the organization as the prime technical contact on small contracts or single component projects. * Interface with customers during program shaping, ConOps development, and requirements derivation activities. * Provides direction to design or technical staff and may lead a team of moderately experienced professional staff. * Maintains the strict confidentiality of sensitive information. * Performs other duties as assigned. * Responsible for observing all laws, regulations and other applicable obligations wherever and whenever business is conducted on behalf of the Company. Expected to work in a safe manner in accordance with established operating procedures and practices. We recognize and appreciate the value and contributions of individuals with diverse backgrounds and experiences and welcome all qualified individuals to apply. Job Category Engineering Travel Percentage Required 0% - 25% Full-Time/Part-Time Full-Time Salary State California Clearance Level Top Secret Pay Range Low 116,480 City San Diego Clearance Required? Desired Pay Range High 208,505 Recruitment Posting Title Senior Systems Engineer Job Qualifications * Typically requires a bachelors degree, masters degree or PhD in engineering or a related technical discipline from an accredited institution and progressive engineering experience as follows; twelve or more years of experience with a bachelors degree, ten or more years of experience with a masters degree, or seven or more years with a PhD. May substitute equivalent engineering experience in lieu of education. * Demonstrates an extensive technical expertise and application of engineering principles, concepts, theory, and practice with the ability to organize, plan, schedule, conduct, and coordinate workloads to meet established deadlines or milestones with experience in project leadership. * Experience leading the development, assembly, integration and testing for a system which will undergo verification and validation including creation of system engineering and test artifacts. * Must possess the ability to understand new concepts quickly and apply them accurately throughout an evolving environment. * Strong communication, presentation, and interpersonal skills are required enabling an effective interface with other departments and/or professionals, and capable of representing the organization as a prime technical contact, as well as providing leadership and guidance to less experienced professionals. * Customer focused, formulates plans based on the development of innovative new designs in resolving advanced technical engineering problems. * Familiarity with digital engineering and toolsets including SysML-based enterprise and performance evaluation tools. * Must be able to work both independently and in a team environment. Able to work extended hours as required. * The ability to obtain and maintain a Top Secret clearance is required. DESIRED SKILLS AND EXPERIENCE: * Experience working with MagicDraw, DOORS, Confluence, Teams and JIRA. * Has past experience as an Integrated Product Team Lead. * Has laser or similar technology development experience. * Has hands on integration experience. * Has experience developing test plans, procedures and reports. * A Professional Engineering License, original work(s) published in professional engineering journals, and invited to present one or more original works to an engineering symposium. * Previous experience working with the Department Of Defense. US Citizenship Required? Yes Experience Level Senior (8+ years) Relocation Assistance Provided? Yes Workstyle Onsite

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. **Meet the Team** The ASIC Group works closely with other development teams within Cisco, including marketing, system hardware, software, product engineering, and manufacturing. Through this collaboration, members of our group play a major role in defining, developing and bringing new products to market across Cisco's product line. Open-minded, driven, diverse and deeply creative people at Cisco craft the hardware that makes the internet work. Bring your knowledge of computers and networking and take it to a new level in any one of the following product categories including: cloud, social, mobile/wireless, video, VoIP, collaboration, web, Internet of Things, routing, switching, IPv6, data center, HPC, TelePresence and many more. Your work will affect billions globally. **Your Impact** ** ** Join our award-winning ASIC team, where you'll collaborate with top industry talent to design and deliver ground breaking communications and network processing silicon. You'll contribute to system and processor architecture, high-speed logic design and verification, digital signal processing, memory and custom library development, physical design, DFT, signal integrity, and advanced packaging. Work with the latest VLSI techniques and deep submicron technologies, owning projects from concept to in-house physical implementation. **Minimum Qualifications** ** ** + Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelor's degreeprogram.Familiaritywith hardware description languages (HDLs), such as Verilog or VHDL. + Experience with RTL design and simulation tools (e.g., Synopsys, Cadence, Mentor Graphics). + Exposure to scripting languages (e.g., Python, Perl, TCL) for automation. + Familiarity with ASIC/SoC design flow including synthesis, place & route, and timing closure. **Preferred Qualifications** ** ** + Experience with ASIC verification methodologies (e.g., UVM, SystemVerilog) + Understanding of physical design and DFT (Design for Test) principles + Familiarity with Linux-based development environments + Ability to adapt to new technologies and problem-solve sophisticated engineering challenges + Excellent organizational, teamwork, and communication skills **Why Cisco** ** ** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. **Why Cisco?** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. **Message to applicants applying to work in the U.S. and/or Canada:** Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: + 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees + 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco + Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees + Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) + 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next + Additional paid time away may be requested to deal with critical or emergency issues for family members + Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: + .75% of incentive target for each 1% of revenue attainment up to 50% of quota; + 1.5% of incentive target for each 1% of attainment between 50% and 75%; + 1% of incentive target for each 1% of attainment between 75% and 100%; and + Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $94,200.00 - $137,500.00 Non-Metro New York state & Washington state: $84,000.00 - $122,200.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements. Cisco is an Affirmative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records.

Responsibilities MaxLinear is seeking a Staff ASIC Verification Engineer to join our team. In this role, you will focus on the following: * Define SoC verification strategies, test plans, and execution plan with ASIC Verification team * Own IP level ASIC verification efforts toward SOC T/O * Implement best industry practices for SoC verification; improve and harmonize verification methodologies across the organization to maximize efficiency and predictability of outcome * Deliver test bench architecture, functional models, complete test environments, and test suites meeting coverage targets to ensure first-time silicon success * Collaborate with design team and project stakeholders on testability improvements and on debug process during test bench bring up Qualifications * Track record in verification strategy development and execution for large SoCs and signoff with coverage metrics * Hands-on knowledge of UVM methodology, System Verilog, C/C++ * Implementation of directed and constrained random test benches for communication physical layer, Ethernet networking, packet processing, PCIE and multi-CPU environments * Knowledge of verification IP and functional coverage techniques * Experience with gate level simulations of delay annotated netlists * Exposure to FPGA emulation and lab validation * Self-motivated, excellent communication skills, and ability to excel and to provide leadership in a fast-paced environment * BS in Electrical Engineering or related + 5 years of experience, or MS + 3 years of experience, or Ph.D. Compensation and Benefits MaxLinear has a Total Compensation philosophy which includes base salary and annual discretionary bonus eligibility and many positions also include stock-based compensation. MaxLinear expects to offer a starting base salary within the range of: $104,728 to $162,656 Annually We offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off. The actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience. Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status. Company Overview MaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world's communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications. We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world's most challenging communication technology problems in the most efficient and effective manner. MaxLinear began by developing the world's first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn't achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we've developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we've expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel's Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers' needs. Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore. We have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market. Responsibilities MaxLinear is seeking a Staff ASIC Verification Engineer to join our team. In this role, you will focus on the following: - Define SoC verification strategies, test plans, and execution plan with ASIC Verification team - Own IP level ASIC verification efforts toward SOC T/O - Implement best industry practices for SoC verification; improve and harmonize verification methodologies across the organization to maximize efficiency and predictability of outcome - Deliver test bench architecture, functional models, complete test environments, and test suites meeting coverage targets to ensure first-time silicon success - Collaborate with design team and project stakeholders on testability improvements and on debug process during test bench bring up

Responsibilities MaxLinear is seeking a Staff ASIC Verification Engineer to join our team. In this role, you will focus on the following: Define SoC verification strategies, test plans, and execution plan with ASIC Verification team Own IP level ASIC verification efforts toward SOC T/O Implement best industry practices for SoC verification; improve and harmonize verification methodologies across the organization to maximize efficiency and predictability of outcome Deliver test bench architecture, functional models, complete test environments, and test suites meeting coverage targets to ensure first-time silicon success Collaborate with design team and project stakeholders on testability improvements and on debug process during test bench bring up Qualifications Track record in verification strategy development and execution for large SoCs and signoff with coverage metrics Hands-on knowledge of UVM methodology, System Verilog, C/C++ Implementation of directed and constrained random test benches for communication physical layer, Ethernet networking, packet processing, PCIE and multi-CPU environments Knowledge of verification IP and functional coverage techniques Experience with gate level simulations of delay annotated netlists Exposure to FPGA emulation and lab validation Self-motivated, excellent communication skills, and ability to excel and to provide leadership in a fast-paced environment BS in Electrical Engineering or related + 5 years of experience, or MS + 3 years of experience, or Ph.D. Compensation and Benefits MaxLinear has a Total Compensation philosophy which includes base salary and annual discretionary bonus eligibility and many positions also include stock-based compensation. MaxLinear expects to offer a starting base salary within the range of: $104,728 to $162,656 Annually We offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off. The actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience. Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status. Company Overview MaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world's communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications. We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world's most challenging communication technology problems in the most efficient and effective manner. MaxLinear began by developing the world's first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn't achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we've developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we've expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel's Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers' needs. Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore. We have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market. We can recommend jobs specifically for you! Click here to get started.

We are **the makers of possible** BD is one of the largest global medical technology companies in the world. Advancing the world of health is our Purpose, and it's no small feat. It takes the imagination and passion of all of us-from design and engineering to the manufacturing and marketing of our billions of MedTech products per year-to look at the impossible and find transformative solutions that turn dreams into possibilities. We believe that the human element, across our global teams, is what allows us to continually evolve. Join us and discover an environment in which you'll be supported to learn, grow and become your best self. Become a **maker of possible** with us. **Job Summary:** The Staff Design Quality Engineer will play a crucial role in ensuring the quality and regulatory compliance of CareFusion 303, Inc.'s medical devices throughout their entire product lifecycle, from design and development through to market release. This position will involve active participation in design control activities, risk management, and fostering a culture of quality within the engineering teams. **Job Responsibilities** Design Control & Development: + Actively participate in product design and development activities, providing quality engineering support and guidance. + Review and approve design inputs, design outputs, design verification, and design validation plans and reports. + Ensure compliance with design control procedures, medical device regulations (e.g., FDA 21 CFR Part 820, ISO 13485), and company policies. + Contribute to the development and maintenance of Design History Files (DHFs). Risk Management: + Lead and facilitate risk management activities, including the development and maintenance of risk management plans, hazard analyses, and FMEAs (Failure Mode and Effects Analyses). + Ensure appropriate risk mitigation strategies are implemented and verified. Post-Market Surveillance & CAPA: + Support post-market surveillance activities by analyzing complaint data and identifying potential quality issues. + Participate in root cause analysis and corrective and preventive action (CAPA) investigations related to design quality. + Contribute to the effectiveness verification of CAPA actions. Compliance & Audits: + Support internal and external audits (e.g., FDA, ISO) by providing documentation and technical expertise related to design quality. + Ensure ongoing compliance with all applicable quality system regulations and standards. Training & Mentorship: + Provide guidance and training to engineering teams on design control, risk management, and quality system requirements. + Act as a mentor to junior quality engineers. **Job Qualifications** **Education:** + Bachelor's degree in Engineering (Biomedical, Mechanical, Electrical, or related field) required. Master's degree preferred. **Experience:** + 5+ years of experience in Design Quality Engineering within the medical device industry. + Demonstrated experience with medical device design controls (21 CFR Part 820.30) and risk management (ISO 14971). + Strong understanding of ISO 13485 quality management system requirements. + Experience with Design Verification and Validation activities including software, system, and human factors testing. + Experience in requirements decomposition, traceability, and test strategy development. + Understanding of change impact analysis and regression test scoping methods. **Skills:** + Excellent analytical and problem-solving skills. + Strong communication (written and verbal) and interpersonal skills, with the ability to effectively collaborate with cross-functional teams. + Proficiency in statistical analysis and quality tools. + Ability to interpret and apply complex regulatory requirements. + ASQ certifications (e.g., CQE, CRE) preferred. + Proficiency in relevant software tools (e.g., TeamCenter, Polarion, AzureDevOps, PLM systems). At BD, we prioritize on-site collaboration because we believe it fosters creativity, innovation, and effective problem-solving, which are essential in the fast-paced healthcare industry. For most roles, we require a minimum of 4 days of in-office presence per week to maintain our culture of excellence and ensure smooth operations, while also recognizing the importance of flexibility and work-life balance. Remote or field-based positions will have different workplace arrangements which will be indicated in the job posting. For certain roles at BD, employment is contingent upon the Company's receipt of sufficient proof that you are fully vaccinated against COVID-19. In some locations, testing for COVID-19 may be available and/or required. Consistent with BD's Workplace Accommodations Policy, requests for accommodation will be considered pursuant to applicable law. **Why Join Us?** A career at BD means being part of a team that values your opinions and contributions and that encourages you to bring your authentic self to work. It's also a place where we help each other be great, we do what's right, we hold each other accountable, and learn and improve every day. To find purpose in the possibilities, we need people who can see the bigger picture, who understand the human story that underpins everything we do. We welcome people with the imagination and drive to help us reinvent the future of health. At BD, you'll discover a culture in which you can learn, grow, and thrive. And find satisfaction in doing your part to make the world a better place. To learn more about BD visit ********************** Becton, Dickinson, and Company is an Equal Opportunity Employer. We evaluate applicants without regard to race, color, religion, age, sex, creed, national origin, ancestry, citizenship status, marital or domestic or civil union status, familial status, affectional or sexual orientation, gender identity or expression, genetics, disability, military eligibility or veteran status, and other legally-protected characteristics. Required Skills Optional Skills . **Primary Work Location** USA CA - San Diego TC Bldg C&D **Additional Locations** **Work Shift** At BD, we are strongly committed to investing in our associates-their well-being and development, and in providing rewards and recognition opportunities that promote a performance-based culture. We demonstrate this commitment by offering a valuable, competitive package of compensation and benefits programs which you can learn more about on our Careers Site under Our Commitment to You (********************************************* . Salary or hourly rate ranges have been implemented to reward associates fairly and competitively, as well as to support recognition of associates' progress, ranging from entry level to experts in their field, and talent mobility. There are many factors, such as location, that contribute to the range displayed. The salary or hourly rate offered to a successful candidate is based on experience, education, skills, and any step rate pay system of the actual work location, as applicable to the role or position. Salary or hourly pay ranges may vary for Field-based and Remote roles. **Salary Range Information** $124,700.00 - $205,800.00 USD Annual Becton, Dickinson and Company is an Equal Opportunity/Affirmative Action Employer. We do not unlawfully discriminate on the basis of race, color, religion, age, sex, creed, national origin, ancestry, citizenship status, marital or domestic or civil union status, familial status, affectional or sexual orientation, gender identity or expression, genetics, disability, military eligibility or veteran status, or any other protected status.

· 3years minimum experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies. · Extensive hand on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using reg Model (UVM_REG) API, drivers, monitors, scoreboard, functional coverage, assertions (SVA), simulations, regression, debug, bug reporting/tracking. · Experience in debugging RTL & Gate level simulations · Part of multiple tapeouts with high quality verification. Qualifications · Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering or equivalent experience Additional Information To discuss on this opportunity feel free to reach Praveen and My Number is ************ . Thanks

RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE TYPE: SecretTRAVEL: Yes, 10% of the TimeDescriptionAt Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work - and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. Northrop Grumman Aeronautics Systems is looking to add a Sr. Staff Electronics Engineer - Payloads to join our team supporting the RQ-4 Global Hawk Program. This position is location in Rancho Bernardo, CA. We are seeking a highly experienced Radar Payloads Subject Matter Expert to serve as the technical authority across contracts. The candidate will provide industry knowledge, drive innovation, improve field support, and mentor engineering talent while maintaining critical relationships with customers, suppliers, and government partners. Key Responsibilities Technical Leadership Serve as the definitive expert on radar payloads, advising customers, suppliers, and integrated product teams (IPTs). Coordinate inputs and secure buy-in from all stakeholders for design and support strategies. Conveys complex technical concepts to non-technical audiences. Problem Solving & Innovation Resolve complex sensor performance, stability, reliability, and repair-turn-around issues through root-cause analysis. Develop alternative approaches that reduce field return rates and shorten repair cycles. Design new support equipment, procedures, and processes to improve fault isolation, troubleshooting precision, accuracy, and efficiency. Testing & Development Direct troubleshooting test points and part removal strategies to support sustainment. Review and define requirements for new payload capabilities and integration of supporting functions. Mentorship & Knowledge Sharing Mentor junior payload engineers and facilitate knowledge-sharing sessions. Create and disseminate best-practice guides and technical materials for payload troubleshooting, sustainment, and development. Customer & Government Relations Act as the primary technical liaison for USAF, NATO, key partners and suppliers Provide 24/7 real-time support via the Operations Support Center, answering calls and delivering troubleshooting dispositions for fielded systems. Prepare and deliver technical and non-technical work products and presentations to senior leadership Basic Qualifications Bachelor of Science in a Science, Technology, Engineering, or Math (STEM) field and 14 years related engineering experience to include a background in radar payloads and related sensor systems, or Masters of Science in a STEM field and 12 years experience to include a background in radar payloads and related sensor systems or PhD in a STEM field and 9 years experience to include a background in radar payloads and related sensor systems. Active DoD Secret (or higher) clearance with a background investigation completed within the past 6 years or currently in a Continuous Evaluation (CE) process. Must have the ability to obtain and maintain a DoD Top Secret clearance. Must have the ability to obtain and maintain Special Access Program (SAP) clearance. This SAP must be obtained within a reasonable amount of time as determined by the company to meet its business needs. Preferred Qualifications Active DoD Top Secret clearance Prior clearance to SAP or SCI MPR-TIP sensor experience Exceptional written and verbal communication skills; ability to convey complex technical concepts to non-technical audiences. Track record of innovative solutions that improve system reliability and reduce field return rates. Experience across research & design, product development, production, and sustainment phases. Primary Level Salary Range: $192,800.00 - $289,200.00The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit *********************************** U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.

Turning Space into a Transportation Layer for Earth Who We Are: Eras of humanity can often be defined by a dominant transportation mode - horse-drawn chariots, ocean-going boats, or aircraft. These were spurred by a small group of people rigorously focused on building technology to achieve faster access to more of the world. We seek to usher in a new era of humanity defined by universal access to the whole globe, free of borders and the presence of a routine way from space to Earth. To do this, we are building highly maneuverable re-entry vehicles that can loiter in orbit before precision landing back on Earth. What you'll do: Inversion's lifting-body reentry platform will create a highly maneuverable, highly accurate, and low-cost vehicle that will be industry-first. The Staff Mission Design Engineer will be responsible for developing a workflow to support the flight simulation data products required for flight safety analysis. This role will also aid in designing and executing system-level performance trade studies to drive key architecture decisions for current and conceptual reentry vehicles. You will own customer-facing performance predictions and safety analysis and be a key contributor to Inversion's advanced development efforts. Required Qualifications: Bachelor's degree in Aerospace or Mechanical Engineering or equivalent experience Typically 12+ years of aerospace system performance analysis Strong knowledge of 3-DOF and 6-DOF flight simulation Experience using flight simulation environments to determine impact dispersions and estimated casualty values in support of flight safety analysis. Familiarity with debris catalog generation Familiarity with trajectory design for space launch, reentry, or hypersonic systems Familiarity with handbook and medium fidelity aerodynamic prediction tools (e.g,. DATCOM, CBAERO, Cart3D, etc.) Familiarity with trajectory optimization tools (POST, OTIS, QuickShot, etc.) Experience using programming languages like Python, MATLAB, etc. to automate workflows and accelerate data analysis. Proven ability to work in a fast-paced environment, including prototyping and rapid iteration of new products. Desired Qualifications: Master's degree in Aerospace or Mechanical Engineering, or equivalent experience End-to-end space mission analysis includes launch, orbital operation, and reentry Strong knowledge of low / mid / high fidelity estimation of aerodynamics of hypersonic vehicles. Significant experience with trajectory optimization tools, including their modification and the creation of custom toolchains around them to accelerate workflows. Experience driving space system architectures using trajectory optimization software tools Space constellation design experience, including familiarity with STK (Systems Tool Kit) for space mission design and ground coverage assessments Our office headquarters is located in Playa Vista, CA. This position requires in-office presence. The California annual base salary for this role is currently $169,000-$199,000. Pay Grades are determined by role, level, location, and alignment with market data. Individual pay will be determined on a case-by-case basis and may vary based on the following considerations: interviews and an assessment of several factors that are unique to each candidate, job-related skills, relevant education and experience, certifications, abilities of the candidate and internal equity. ITAR Compliance: To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here. Equal Employment Opportunity: Inversion provides equal employment opportunities to all employees and applicants without regard to race, color, religion, age, sex, gender identity, sexual orientation, national origin, veteran status, or disability. Inversion collects and processes personal data in accordance with applicable data protection laws. If you are a US Job Applicant see the CCPA Privacy Policy Notice for further details.