Senior verification engineer jobs in Saratoga, CA - 1,635 jobs

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD/Xilinx programmable devices. THE PERSON: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware and firmware engineers to understand the new features to be verified Take ownership of block level verification tasks Define test plans, test benches, and tests using System Verilog and UVM Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes Review functional and code coverage metrics to meet the coverage requirements Develop and improve existing verification flows and environments PREFERRED EXPERIENCE: Strong understanding of computer architecture and logic design Knowledge of Verilog, system Verilog and UVM is a must Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification Working knowledge of C/C++ and Assembly programming languages Exposure to scripting (python preferred) for post-processing and automation Experience with gate level simulation, power and reset verification ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

About Voltai Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits. About the Team Backed by Silicon Valley's top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents. About this Role We are building next- generation tools for silicon design by combining deep verification expertise with modern AI systems. As a Senior Verification Engineer, your role isn't just verifying chips but redefining how teams verify chips. If you want to build tools that scale with the new era of complexity in hardware, this role offers high ownership and direct impact on real-world chip development. What You'll Do Own verification strategy across multiple IP blocks and subsystems, from testbench architecture to signoff. Design and develop AI assisted workflows that accelerate verification, coverage closure, and debug. Build reusable verification frameworks using SystemVerilog, UVM, Python and custom automation tooling. Collaborate with ML and software teams to integrate AI models into existing DV environments. Contribute to product direction by exploring how automation can reshape verification methodologies. Work with customers in a forward deployed capacity when needed, translating real design challenges into product features. Drive tapeout readiness with full accountability for quality metrics, regression health, and coverage targets. Mentor junior engineers and help define best practices for next generation verification teams. What Makes This Role Unique Opportunity to influence the future of tooling and AI guided verification flows. High ownership from day one including technical decisions, roadmap input, and customer interactions. Exposure to both engineering and product thinking. Fast-moving environment built for builders who take initiative rather than wait for direction. Qualifications 4 to 6 years of hands‑on verification experience. Strong SystemVerilog and UVM skills with proven debug depth. Familiarity with Python or similar scripting languages. Curious mindset toward AI or automation in verification, even if not an expert yet. Ability to work across domains and communicate clearly with software or ML teams. Comfortable interacting with clients, architects, and leadership when needed. Thrives in a high responsibility environment and enjoys creating solutions that did not exist before. Bonus Skills Experience with formal verification, co‑simulation or stimulus generation frameworks. Background in ML, LLMs, data pipelines, or tool development. Previous involvement in customer facing or forward deployed engineering roles. Demonstrated ability to build tools that others actually use. #J-18808-Ljbffr

Technical Lead Design Verification Engineer San Jose, CA Astera Labs (NASDAQ: ALAB)provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ****************** . We are looking fora Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You'll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms. Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Masters is preferred. ≥5 years' experience verifying and validating complex SoC for Server, Storage, and Networking applications. Knowledge of industry-standard simulators, revision control systems, and regression systems. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision. Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! Authorized to work in the US and start immediately. Required Experience Experience with full verification lifecycle based on System Verilog/UVM/C/C++. Proven ability to mix and deploy hybrid techniques as in both directed and constrained random. Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus. Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures. Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out. Preferred Experience Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc. Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Experience with directed test based methodologies, cache verification and formal methods. The base salary range is USD 147,000.00 - USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. Apply for this job * indicates a required field First Name * Last Name * Preferred First Name Email * Phone Resume/CV Enter manually Accepted file types: pdf, doc, docx, txt, rtf Enter manually Accepted file types: pdf, doc, docx, txt, rtf LinkedIn Profile Website How many years of full-time experience do you have relevant to the role? Select... Are you open to relocation and if so, to what location(s)? * I have reviewed and consented to the privacy policies. Select... #J-18808-Ljbffr

Our client is a world-leading technology company at the forefront of semiconductor innovation, powering some of the most advanced digital systems in the industry. Their work touches billions of users globally, driving next‑generation performance and efficiency across highly complex hardware and software ecosystems. They are seeking a Design Verification Engineer with deep expertise in SystemVerilog/UVM and digital ASIC verification. This role is critical for ensuring robust, reusable verification environments, achieving high functional coverage, and supporting rapid innovation in complex hardware designs that operate at massive scale. What You'll Do Develop comprehensive Core Verification Plans based on unit micro‑architecture and design specifications. Architect and implement reusable verification environments using SystemVerilog/UVM. Create and execute constrained‑random and directed tests to achieve high functional and code coverage for core units. Analyze simulation results, debug complex failures, and collaborate with design teams to root‑cause and resolve issues. Develop and maintain scripts (Python/Perl) to automate verification flows and regression management. Support verification of digital systems using standard IP components and interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Act as a technical leader within verification teams, providing feedback to RTL designers and IP architects. Requirements SystemVerilog/UVM expertise is mandatory. At least 7 years of hands‑on expertise. Strong grasp of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Proven ability to work autonomously and demonstrate technical confidence when engaging with, and providing constructive feedback to, FE RTL design teams and CPU/IP micro‑architects. Proficiency with industry‑standard EDA simulation and debug tools. Solid abilities in debugging and root‑cause analysis. Experience with scripting (Python, Perl). Excellent written and verbal communication skills in English are required. Nice‑to‑Have Qualifications (Not required, but beneficial) Experience in high‑performance computing or large‑scale SoC verification. Familiarity with emerging verification methodologies and flows. Prior involvement in multi‑team or cross‑site verification projects. Why This Role Matters This position is central to delivering high‑performance, reliable digital hardware at global scale. You will have the opportunity to shape verification strategies, implement reusable test environments, and contribute to cutting‑edge projects that power complex systems used by millions worldwide. This is an environment where technical expertise meets massive real‑world impact. #J-18808-Ljbffr

Title Design Verification Engineer - Internal IP About the Company A fast-growing AI startup designing next-generation compute hardware. The company specializes in building high-performance IP blocks and accelerators, aiming to enable leading‑edge AI workloads with custom silicon and software stacks. Role Overview You will lead verification efforts on internal IP blocks that power the company's compute architecture. Working closely with design engineers and systems teams, you'll define verification strategies, develop testbenches, write directed and random stimulus, debug failures, and sign off quality IP for integration into larger systems. Key Responsibilities Review IP specifications and architecture to understand functional, performance, and integration requirements. Develop verification plans, create functional coverage models, define corner cases and failure modes. Build testbenches using SystemVerilog (or similar HDL), UVM or equivalent methodology, and integrate into simulation/acceleration/emulation flows. Automate regressions, monitor coverage metrics, identify gaps, and work with design teams to close them. Debug and triage simulation/emulation failures, analyze waveforms/traces, provide meaningful feedback to design and physical teams. Collaborate with RTL designers, synthesis and physical teams, CAD and systems/firmware teams to ensure smooth handoff and tape‑out readiness. Mentor or collaborate with other engineers to drive verification best practices and process improvements. Qualifications Strong experience (typically 5 + years) in design verification of digital IP in a hardware environment. Proficiency in SystemVerilog (or equivalent HDL), and verification methodologies (UVM/UVM‑like frameworks). Deep understanding of digital logic, microarchitecture (e.g., pipelines, memory subsystems, AXI/AMBA interconnects), timing, and clocking domains. Experience with functional coverage, constrained‑random verification, assertions, and testbench development. Familiar with simulation tools, emulation/prototyping flows, and regression automation. Excellent debug skills, ability to drive issues to resolution across cross‑functional teams. Bachelor's or Master's in Electrical Engineering/Computer Engineering or equivalent; advanced degree preferred. Strong communication and collaboration skills; ability to lead in a fast‑paced startup environment. Nice to Have Experience in AI/hardware accelerator domain (e.g., tensor cores, matrix engines, AI pipelines). Familiarity with low‑power design, clock gating, power domains, and verification of power/clock islands. Experience working with mixed‑signal or analog/mixed‑signal IP verification, or prototyping on FPGA/emulation platforms. Background in physical verification, synthesis flow, timing closure or floorplanning. What's in It for You Opportunity to design and verify cutting‑edge compute IP for AI workloads. Early‑stage startup with high autonomy, ownership and the ability to shape architecture and process. Competitive compensation, equity participation and benefits aligned with high‑growth startup norms. Collaborative, high‑velocity culture driven by innovation and ambitious goals. #J-18808-Ljbffr

About Etched Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain‑of‑thought reasoning agents. Job Summary We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware‑software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. Key responsibilities End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors Understand vendor IP configurations and handle handshake with internal IP team Develop and maintain UVM/SystemVerilog‑based verification environments to ensure functional correctness, performance, and compliance with IP specifications. Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture. Drive coverage closure and sign‑off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios. You may be a good fit if you have: 5+ years of design verification experience You enjoy digging deep into complex verification challenges and finding creative ways to expose corner‑case bugs. You have hands‑on experience with industry‑standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches. You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs. You thrive in a fast‑paced startup environment and can take ownership of projects with minimal direction. You collaborate naturally with cross‑functional teams - from RTL design to software and emulation - and can clearly communicate technical insights. Strong candidates may also have experience with: Experience handling vendors and integration of IP/VIP's UVM/System Verilog Benefits Full medical, dental, and vision packages, with generous premium coverage Housing subsidy of $2,000/month for those living within walking distance of the office Daily lunch and dinner in our office Relocation support for those moving to San Jose (Santana Row) How we're different Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model‑specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single‑model ASICs. We are a fully in‑person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. #J-18808-Ljbffr

Altera .Design Verification page is loaded## Design Verificationlocations: San Jose, California, United Statestime type: Full timeposted on: Posted Yesterdayjob requisition id: R01697# **Job Details:**### ## **Job Description:**Altera is a leading FPGA (Field-Programmable Gate Array) company that delivers programmable hardware, software, and development tools to drive innovation from cloud to edge. With over four decades of experience in programmable logic, our broad portfolio includes FPGAs, CPLDs, IP, SmartNICs, IPUs, and System on Modules-supported by industry-leading tools like the Quartus development suite.Recently re-established as an independent business (with Intel retaining a minority interest), Altera is focused on accelerating programmable compute in AI, networking, communications, industrial, automotive, aerospace/military, and edge-computing domains.Our mission is to provide leadership programmable solutions that are easy to design and deploy, and our vision is to pioneer innovation that unlocks extraordinary possibilities.We are seeking a Sr Silicon Design Verification Engineer (on-site) who can perform the following functions* Performs functional logic verification at multiple levels ( block, subsystem and full chip )* Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.* Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.* Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.* Collaborates and communicates with Architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.* Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.* Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.* Maintains and improves existing functional verification infrastructure and methodology.* Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products### ## **Qualifications:**Minimal Qualification:* Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 3-5+ years of technical experience.* Validation/Verification. Related technical experience should be in/with: Pre Silicon* OVM/UVM, System Verilog, constrained random verification methodologies. Preferred Qualification* Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.* The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).* Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.* Scripting experience with TCL/PERL/Python etc.,* Formal verification experience,* Experience in either Ethernet / PCIe / MACSEC / IPSEC protocols & FPGA architecture or FPGA prototyping### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr

Nextgen Technologies Inc., has openings for Design Verification Engineer in San Jose, CA: Job Title: Design Verification Engineer Job Duration: 40 Hours / Week, Permanent position, Full time Job Duties: Collaborate with design and development teams to understand product requirements and specifications. Create a comprehensive verification plan detailing the strategies, methodologies, and tools for verifying the design. Develop standards and guidelines to ensure design quality and performance. Drive design verification to closure based on defined verification metrics, including the test plan, functional coverage, and code coverage. Define, maintain, and execute unit-level and/or cluster-level verification test plans. Design and implement test benches with test cases, stimulus, and monitors to verify the design's behavior and functionality. Work closely with architects to communicate verification progress, issues, and potential improvements. Create and write test cases to validate the design's features, functions, and robustness. Develop and drive continuous design verification improvements using the latest verification methodologies, tools, and industry technologies to detect bugs, glitches, or deviations. Review the architecture and micro-architecture specifications. Maintain efficient and clean regression status and drive functional and code coverage to closure. Generate and run test cases on logic simulation models. Code functional coverage models and System Verilog assertions. Prepare comprehensive reports and documentation detailing the verification process, results, and any issues identified. Job Requirements: Required Master's or foreign equivalent in Computer Science, Computer Information Systems, Management Information Systems, Engineering (Any), or any related field + 1 year of experience in the job offered, Software Engineer, Project Engineer, Design Engineer or related. Travel may be required to various unanticipated client sites throughout the US. The frequency of travel will be 10-15%. Salary Range: $156,853.00/Year to $160,000.00/Year Location of Work: Nextgen Technologies Inc. 1735 North 1st Street, Suite #102 San Jose, CA 95112 To contact or to apply please send resumes to HR, Nextgen Technologies Inc., 1735 North 1 st Street, Suite #102, San Jose, CA 95112 or email: **************************. #J-18808-Ljbffr

401(k) 401(k) matching Sr Design Verification Engineer Milpitas, CA Primary Responsibilities Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practices. Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective action. Overall, responsible for verification of ASIC designs to include such things as: Design Verification - Implement test benches in UVM and System Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design team. Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible for debugging designs for high throughput, low latency of pipeline and dynamic power management at full system level. Setup Verification Regression suites at RTL level and corresponding netlist level after synthesis to test any/all corner case conditions. Work closely with Socionext's design team to ensure the company is meeting design requirements for projects. This may include review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benches. Work closely with Socionext's Custom SoC department to provide great customer service to our clients and the projects at hand. Support, encourage and drive timely and accurate deliverables with customers within schedules. Qualifications BS or MS in Computer Science or Electrical Engineering. 5-10+ years of industry experience bringing silicon ICs into high volume production. Must have strong experience with UVM. Must have a full chip verification experience. Experience of leading a single project. Knowledge of industry standard interfaces. Extensive familiarity with Verilog, simulation tools & demonstrated ability to debug problems & troubleshoot in real time. Sound knowledge of ARMv8, interconnect, memory coherence and memory architectures. Familiarity with Formality & most popular verification tools. (Key knowledge should include such topics as IP validation, gate level verification, FPGA validation, emulation, silicon validation, reference board bring up verification, silicon bring up, DFx, low power verification) Expertise in writing Perl / Python, awk, sed & common scripts to automate the verification tasks for CPU plus all chip peripherals - USB, PCIe, MIPI, SDIO, PCI E & DDR controllers. Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation. Experience with low-level programming of systems in C/C++. Experienced in writing scripts in languages such as Perl, Python and Tcl. Functional understanding of constrained random verification process, functional coverage, and code coverage. Low power verification UPF. Team player with excellent communication skills and the desire to take on diverse challenges. Customer interaction. Other Qualifications Good knowledge of low power camera and imaging systems is a plus. Experience with formal verification tools is a plus. Familiarity with ARM architecture. Familiarity with scripting/programming with Perl/Python, Tcl, C/C++. Compensation: $150,000.00 - $160,000.00 per year. #J-18808-Ljbffr

Sr Design Verification Engineer (Remote) Full-time: Salary + Benefits + Bonuses / Contractor Work Status: US citizen or Lawful Permanent Resident. About the Role The ASIC Verification Engineer will play a crucial role in executing a comprehensive test strategy for future ASIC development. You will be part of a team creating automated regression suites, executing verification methodologies. As our ASIC Design Verification Engineer, you will: Test Strategy & Development Collaborate with design and other verification engineers to develop and execute test strategies. Write testbenches and test cases based on test plans. Develop and improve UVM frameworks. Contribute to unit-level and system-level verification deliverables. Become a key contributor to our ASIC verification framework, methodology, and test automation. Implement DSP verification environments to facilitate testing of the RTL against reference MATLAB and Python models Testing & Automation Run and automate regression tests. Analyze code and functional coverage and provide actionable feedback to the development and verification team. Prepare and present detailed reports on testing outcomes and verification strategies. Qualities of a Successful Candidate BS or MS in Electrical/Computer Engineering or equivalent. 10+ years of experience in ASIC verification. Proficiency in SystemVerilog and UVM for verification. Knowledge of verification for DSP algorithms and Mixed Signal systems. Nice to Have Familiarity with Cadence Xcelium simulators or similar tools. Knowledge of scripting languages such as Python or TCL. Experience working on Linux-based systems. The anticipated annual base salary for this position is between $135,000 to $165,000, which also includes a comprehensive benefits package. Full-Time Benefits 15 days of PTO per calendar year 10 paid Holidays per calendar year Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents Dental & Vision: Company covers 50% of premiums for Employee and Dependents Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance Employee Assistant Program (EAP) 401k - Traditional & Roth Life/AD&D and Long-Term Disability Tuition reimbursement Equal Opportunity Policy Statement Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances. Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status. #J-18808-Ljbffr

A leading technology company is seeking a skilled Design Verification Engineer to focus on functional and performance verification of GPU designs in San Jose, California. This role involves developing verification plans, maintaining UVM-based environments, and collaborating with multiple teams to ensure adherence to specifications. The ideal candidate should have a Bachelor's degree and significant experience in ASIC/SoC/GPU/CPU development, particularly in verification processes. It is a 6-month onsite contract position. #J-18808-Ljbffr

A leading technology company is seeking recent graduates for an ASIC engineering role in San Francisco. You'll be part of a dynamic team, collaborating with experts in the field to develop innovative communications and network processing solutions. Candidates should have a Bachelor's degree or be nearing completion, familiar with hardware description languages, and understand ASIC design flow. Join a company that is shaping the future of technology. #J-18808-Ljbffr

About the Team OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We're looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems-ranging from individual IP blocks to subsystems and full SoC-working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. Key Responsibilities Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. Define verification plans based on architecture and microarchitecture specs. Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. Drive bug triage, root cause analysis, and work closely with design teams on resolution. Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments. Qualifications BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification. Proven success verifying complex IP or SoC designs in industry-standard flows Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi). Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives. Familiarity with performance modeling, formal verification, or emulation is a plus. Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware. To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations. About OpenAI OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity. We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic. For additional information, please see OpenAI's Affirmative Action and Equal Employment Opportunity Policy Statement. Qualified applicants with arrest or conviction records will be considered for employment in accordance with applicable law, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations. To notify OpenAI that you believe this job posting is non-compliant, please submit a report through this form. No response will be provided to inquiries unrelated to job posting compliance. We are committed to providing reasonable accommodations to applicants with disabilities, and requests can be made via this link. OpenAI Global Applicant Privacy Policy At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology. #J-18808-Ljbffr

A joint venture in the automotive industry is seeking a Senior Embedded Software Engineer to support the development of the Infotainment Platform for next-generation electric vehicles. The role focuses on safety-critical embedded software development utilizing RTOS platforms, and requires extensive experience in low-level software as well as strong proficiency in C/C++. The position offers competitive compensation in the range of $146,900 to $194,610 based on experience, with robust employee benefits. #J-18808-Ljbffr

A leading technology company in San Francisco is seeking a highly skilled design verification engineer to ensure bug-free first silicon for new products. The role involves developing methodologies for verification, creating test plans, and utilizing advanced tools and techniques, including LLMs, to enhance efficiency and quality. The ideal candidate will have a BS degree and at least 10 years of relevant experience in the field. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Senior Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network‑on‑Chip (NoC), and cutting‑edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal‑based verification environments at both block and SoC‑level to achieve first‑pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre‑Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities: Lead the verification of high‑speed Crypto, Network‑on‑Chip (NoC), cutting‑edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal‑based verification environments at IP and SoC‑level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion‑based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. Proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analysed and verified system‑level Performance and QoS (Quality of Service) requirements. Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including assertion and coverage‑driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high‑performance IP and/or VLSI designs is a plus. Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate‑level simulation, power‑aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. ACADEMIC CREDENTIALS: BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include firmware, device drivers, RTOS porting, and board bring-up. A “Great Place To Work Certified™” company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of The Jhaver Group, which employs over 32,000 people across 80+ locations globally. Prodapt is seeking a highly skilled Design Verification Engineer to focus on functional and performance verification of cutting-edge GPU designs, ensuring they meet stringent quality and specification requirements. In this role, you will develop and execute verification plans, build and maintain UVM-based environments, and collaborate closely with design and architecture teams to drive verification closure on complex GPU blocks and subsystems. 6 month contract Onsite in Austin, TX Responsibilities Develop and execute comprehensive verification plans for GPU designs, including defining verification goals, test strategies, and coverage metrics. Design, develop, and maintain verification testbenches and environments using SystemVerilog, UVM, and C++ to verify GPU functionality, performance, and power-related features. Create complex test scenarios and test cases to achieve comprehensive functional and performance coverage of GPU features and micro-architecture. Analyze simulation and regression results, debug complex GPU designs, identify root causes, and drive bug resolution in collaboration with design and architecture engineers. Work closely with cross-functional teams, including design, architecture, and software, to align verification efforts with project milestones and product requirements. Maintain accurate and up-to-date documentation for verification plans, testbenches, test cases, and results to support traceability and reviews. Requirements Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field; or equivalent practical experience. 10+ years of industry experience with a Bachelor's, 8+ years with a Master's, or 6+ years with a PhD in relevant domains of ASIC/SoC/GPU/CPU development. 5+ years of hands-on experience in GPU/CPU design verification or closely related IP/subsystem verification. Strong proficiency in SystemVerilog and UVM for block-level and/or subsystem-level verification. Experience with industry-standard verification tools and simulators (e.g., VCS, Xcelium, Questa, Verdi or similar) and coverage-driven verification flows. Proficiency with scripting languages such as Python and Perl for automation, regression management, and data analysis. Demonstrated strength in debugging, root-cause analysis, and driving verification closure in complex designs. Excellent communication and interpersonal skills, with the ability to work effectively in a collaborative, cross-functional environment. #J-18808-Ljbffr

We are seeking a Design Verification Engineer. The role is technical, hands-on, in charge of the verification environment for new silicon projects and developments. We are looking for an experienced professional with Passion & Drive to succeed. Qualifications BS or MS in Computer Science or Electrical Engineering. 5-10+ years of industry experience bringing silicon ICs into high volume production. Must have strong experience with UVM. Must have a full chip verification experience Experience of leading a single project. Knowledge of industry standard interfaces. Extensive Familiarity with Verilog, Simulation tools & demonstrated ability to debug Problems & Troubleshoot in Real Time. Sound knowledge of ARMv8, interconnect, memory coherence and memory architectures Familiarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verification) Expertise in writing Perl / Python , awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals - USB, PCIe, MIPI, SDIO, PCI E & DDR Controllers. Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation Experience with low-level programming of systems in C/C++. Experienced in writing scripts in languages such as Perl, Python, and Tcl. Functional understanding of constrained random verification process, functional coverage, and code coverage. Low power verification UPF Team player with excellent communication skills and the desire to take on diverse challenges. Other Qualifications Good knowledge of low power cameras and imaging systems is a plus Experience with formal verification tools is a plus. Familiarity with ARM architecture Familiarity with scripting/programming with Perl/Python, Tcl, C/C++ Compensation: $140,000.00 - $150,000.00 per year #J-18808-Ljbffr

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. Meet the Team The ASIC Group works closely with other development teams within Cisco, including marketing, system hardware, software, product engineering, and manufacturing. Through this collaboration, members of our group play a major role in defining, developing and bringing new products to market across Cisco's product line. Open-minded, driven, diverse and deeply creative people at Cisco craft the hardware that makes the internet work. Bring your knowledge of computers and networking and take it to a new level in any one of the following product categories including: cloud, social, mobile/wireless, video, VoIP, collaboration, web, Internet of Things, routing, switching, IPv6, data center, HPC, TelePresence and many more. Your work will affect billions globally. Your Impact Join our award-winning ASIC team, where you'll collaborate with top industry talent to design and deliver ground breaking communications and network processing silicon. You'll contribute to system and processor architecture, high-speed logic design and verification, digital signal processing, memory and custom library development, physical design, DFT, signal integrity, and advanced packaging. Work with the latest VLSI techniques and deep submicron technologies, owning projects from concept to in‑house physical implementation. Minimum Qualifications Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelor's degree program. Familiarity with hardware description languages (HDLs), such as Verilog or VHDL. Experience with RTL design and simulation tools (e.g., Synopsys, Cadence, Mentor Graphics). Exposure to scripting languages (e.g., Python, Perl, TCL) for automation. Familiarity with ASIC/SoC design flow including synthesis, place & route, and timing closure. Preferred Qualifications Experience with ASIC verification methodologies (e.g., UVM, SystemVerilog) Understanding of physical design and DFT (Design for Test) principles Familiarity with Linux-based development environments Ability to adapt to new technologies and problem‑solve sophisticated engineering challenges Excellent organizational, teamwork, and communication skills Why Cisco At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada Individual pay is determined by the candidate's hiring location, market conditions, job‑related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non‑exempt employees 1 paid day off for employee's birthday, paid year‑end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non‑exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full‑time employees Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non‑sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance‑based incentive pay on top of their base salary, which is split between quota and non‑quota components, subject to the applicable Cisco plan. For quota‑based incentive pay, Cisco typically pays as follows: 0.75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non‑quota‑based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $94,200.00 - $137,500.00 Non‑Metro New York state & Washington state: $84,000.00 - $122,200.00 For quota‑based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Employees in Illinois, whether exempt or non‑exempt, will participate in a unique time off program to meet local requirements. Cisco is an affirmative action and equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records. #J-18808-Ljbffr