SiFive CEO and leadership

Krste Asanović from the University of California, Berkeley has written and co-authored many academic papers concerning computer architecture. He is currently Chairman of the Board of the RISC-V Foundation.

Andrew serves as SiFive’s Chief Engineer and co-founder. Andrew received his PhD in Computer Science from UC Berkeley, where, weary of the vagaries of existing instruction set architectures, he co-designed the RISC‑V ISA and the first RISC‑V microprocessors with Yunsup Lee. Andrew is one of the main contributors to the open-source RISC‑V based Rocket chip generator and the Chisel project. Andrew also has an MS from UC Berkeley and a BSE from Duke University.

Yunsup is SiFive’s Chief Technology Officer and co-founder. Yunsup received his PhD from UC Berkeley, where he co-designed the RISC‑V ISA and the first RISC-V microprocessors with Andrew Waterman, and led the development of the Hwacha decoupled vector-fetch extension. Yunsup also holds an MS in Computer Science from UC Berkeley and a BS in Computer Science and Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST).

Jay leads SiFive's global finance function as well as working with the leadership team on business strategy. He brings more than 25 years of experience in corporate finance, accounting, M&A, corporate governance, and investor relations. Jay was previously CFO of Open-Silicon, where he helped the company grow to profitability and more than $100m in revenue. Prior to Open-Silicon, Jay was VP, Finance, and Corporate Controller at Oxford Semiconductor. Prior to Oxford, he was VP, Finance for Semiconductor Operations at Cree and led a successful spin-off of Ultra RF, the Semiconductor Division of Spectrian. Jay holds a degree in accounting and is certified accountant from the UK.

Krste Asanović from the University of California, Berkeley has written and co-authored many academic papers concerning computer architecture. He is currently Chairman of the Board of the RISC-V Foundation.

Andrew serves as SiFive’s Chief Engineer and co-founder. Andrew received his PhD in Computer Science from UC Berkeley, where, weary of the vagaries of existing instruction set architectures, he co-designed the RISC‑V ISA and the first RISC‑V microprocessors with Yunsup Lee. Andrew is one of the main contributors to the open-source RISC‑V based Rocket chip generator and the Chisel project. Andrew also has an MS from UC Berkeley and a BSE from Duke University.

Yunsup is SiFive’s Chief Technology Officer and co-founder. Yunsup received his PhD from UC Berkeley, where he co-designed the RISC‑V ISA and the first RISC-V microprocessors with Andrew Waterman, and led the development of the Hwacha decoupled vector-fetch extension. Yunsup also holds an MS in Computer Science from UC Berkeley and a BS in Computer Science and Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST).